JP3450835B2 - Data reproduction system from optical disk - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording data reproducing system applied to an optical disk device such as a magneto-optical disk device.

A magneto-optical disk device has a large capacity, replaceability,
Due to high reliability and the like, it is rapidly spreading from recording / reproducing image information to code recording capable for computer.

[0003]

2. Description of the Related Art The basic structure of a conventional optical disk recording system is shown in FIG. In FIG. 74, an optical disc 1, an optical head 2, a data output unit 3, a modulator 4 and a laser drive unit 5 are provided. First, the data from the data output unit 3 is modulated by the modulator 4, and the modulation signal is sent to the laser driving unit 5. Then, the laser drive unit 5 drives the laser diode (LD) of the optical head 2 based on the modulation signal to record data on the optical disc 1. The data, the laser (LD) drive signal, and the pits formed on the optical disc 1 at this time are as shown in FIG. 75, for example. That is, a pit is formed at a position where the laser diode (LD) is turned on according to the recording data. Further, in the magneto-optical disk, pits are formed by magnetic domains.

Next, the basic structure of the reproducing system is shown in FIG. In FIG. 76, an optical disc 1, an optical head 2, an amplifier 6, a filter / equalizer 7, a peak detector 8, a PLL circuit 9 and a demodulator 10 are provided. The laser diode (LD) of the optical head 2 is turned on with the power Pr to irradiate the optical disc 1 with laser light. A reflected signal obtained from the optical disc 1 produces a reproduction signal as shown in FIG. The reproduction signal passes through the amplifier 6 and is AGC.
(Auto gain controller), LPF (low-pass filter) and Eq (equalizer) waveform-shaped and then supplied to the peak detector 8. Peak detector 8
Is to differentiate the reproduction signal and detect the zero-cross point of the differentiation signal to detect the peak point of the reproduction signal,
It outputs a pulse signal called Row Data. This raw data is sent to the PLL circuit 9, and separate data synchronized with the clock is output from the PLL circuit 9. Then, the separate data is demodulated by the demodulator 10 into the original data.

[0005]

The state of the reproduction signal when the data recording density on the optical disc 1 is low is as shown in FIG. 78 (a), for example. The state of the reproduction signal when the data recording density on the optical disc 1 is high is as shown in FIG. 78 (b), for example. Noise generated in the circuit is superimposed on the reproduced signal waveform in addition to the noise due to the laser diode (LD) and the noise of the optical disk. When the recording density of data on the optical disc is increased, the amplitude of the reproduction signal is reduced due to thermal interference during recording and waveform interference during reproduction. Therefore, in the conventional detection system, the detection margin becomes small and an error is likely to occur.

The present invention has been made in view of the above problems, and a recorded data reproducing system for an optical disk which ensures a detection margin for data detection and enables correct data detection even when the recording density of the optical disk is improved. Is intended to provide.

[0007]

In order to solve the above problems, the present invention records a stationary pattern signal modulated according to a recording rule of a predetermined partial response characteristic, as described in claim 1. In a system for reproducing data from an optical disc in which information is recorded in each unit area having a first area for recording and a second area for recording a random recording data signal, a signal for reproducing a signal from the optical disk. Reproducing means, sampling means for sampling the reproduced signal at a predetermined timing and outputting the sampling data, and equalization processing means for performing equalization processing of the sampling data from the sampling means based on the equalization target value. And most likely to be reproduced based on the sampling data processed by the equalization processing means. From the data determined by the maximum likelihood data detection means based on the sampling data processed by the equalization processing means in the second area in each unit area. Data generation means for generating recording data, and equalization target value calculation means for calculating an equalization target value used by the equalization processing means based on sampling data obtained in the first area in each unit area. Is configured to have.

In such a data reproducing system, the equalization target value calculating means is used in the equalization processing means based on the sampling data of the pattern signal obtained in the first area of each unit area on the optical disk. Calculation target value. After that, the equalization processing means executes the equalization processing of the sampling data sampled in the second area of each unit area based on the equalization target value calculated by the equalization target value calculation means. Then, the maximum likelihood data detection means determines the most probable data to be reproduced based on the sampling data processed by the equalization processing means.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

A recording system of an optical disk device according to an embodiment of the present invention is constructed, for example, as shown in FIG. In FIG. 1, an optical disc 1, an optical head 2, a data output unit 3, a laser drive unit 5, a travel length limiting modulator 11 and a partial response modulation precoder (P
R modulation precoder) 12 is provided. The running length limit modulator 11 performs 1/7 modulation of the data (bit string) from the data output unit 3 according to the rule of converting 2-bit data to 3-bit data as shown in FIG. The data that is 1/7 modulated by the running length limiter 11 is P
The R precoder 12 further modulates according to the characteristic corresponding to the partial response class 1. As shown in FIG. 2, the PR precoder 12 has a delay element (D) 15 in which a delay time for one data is set, and output data is input data via the delay element (D) 15. Have been returned to. In this case, the PR modulation precoder 12
Then, [1 / (1 + D)] mod2 modulation is performed. [1 /
(1 + D)] The data obtained by the mod2 modulation is supplied to the laser drive unit 5, and the laser drive unit 5 outputs the laser drive signal corresponding to the input data. A laser drive signal (recording signal) from the laser drive unit 5 is supplied to a laser diode (LD) of the optical head 2, and the laser diode driven by this laser drive signal records data on the optical disc 1. The conversion of the data from the data output unit 3 into the laser drive signal (recording signal) as described above is performed by, for example, FIG.
It is shown in (1), (2), (3) and (4).

Next, a reproducing system for reproducing data from the optical disc 1 on which data is recorded by the recording system as described above is constructed as shown in FIG. 4, for example. 4, an optical disc 1, an optical head 2, an amplifier 6, a filter / equalizer 7, a PLL circuit 9, a demodulator 10, an A / D converter 13, a maximum likelihood decoder 14 and a binarization circuit 17 are provided. . A reproduction signal corresponding to the recorded data is obtained from the optical disk 1 via the optical head 2, and the reproduction signal is amplified by the amplifier 6 and then waveform-shaped by the filter / equalizer 7. The waveform-shaped signal is A
The signal is converted into a digital signal by the / D converter 13, and this digital signal is demodulated by the maximum likelihood decoder 14. The binarization circuit 17 converts the signal waveform-shaped by the filter / equalizer 7 into a binarized signal using, for example, a certain slice level. Then, the PLL circuit 9 generates a timing clock signal based on the binarized signal. A
The / D converter 13 and the maximum likelihood decoder 14 operate in synchronization with the timing clock signal from the PLL circuit 9. The states of the respective signals from the generation of the reproduction signal to the maximum likelihood decoding are shown in, for example, FIGS. 7 (5), (6), (7), (8) and FIGS. Shown. (Note that FIG.
(8) and FIG. 8 (8) show the same signal transition states. ) Then, the signal obtained by the maximum likelihood decoding is further demodulated into final data by the demodulator 10 (1/7 demodulation).

In FIG. 7, the characteristic of converting the recording signal (4) into the reproduction signal (6) which is the output of the filter / equalizer 7 corresponds to the characteristic of the partial response class 1. Therefore, the reproduction signal (6) corresponds to the signal obtained by (1 + D) converting the recording signal (4). The signal obtained by converting the recording signal (4) into (1 + D) is
As shown by the broken line in FIG. 7 (6), it can take three values.
Now, let that value correspond to -2, 0, 2. Then, the maximum likelihood decoder 14 demodulates the converted signal of the reproduction signal (6) by the A / D converter 13 into a recording signal. In the maximum likelihood decoder 14, when probable data is detected from the input signal,
The most probable data transition path leading to the detected data is determined, and the data on that path is determined as the recording signal data to be reproduced. Between the recording signal data “+1” and “0”, as shown in the trellis diagram of FIG. 5, the data transition path from “1” to “1”, the data transition from “0” to “0”. There can be a path, a data transition path from "1" to "0" and a data transition path from "0" to "1". Then, these state transitions are collectively shown in the state transition diagram of FIG. The data transition path from "1" to "1" corresponds to "+2" of the signal (see FIG. 7 (6)) obtained by the above (1 + D) conversion, and the state of this data transition is + merge (plus merge). ) Is defined.
The data transition path from “0” to “0” is (1+
D) Corresponding to "-2" of the signal obtained by the conversion, the state of this data transition is defined as -merge (minus merge). Also, the transition paths from "0" to "1" and "1" to "0" correspond to "0" of the signal obtained by the above (1 + D) conversion, and are either of these data transitions. The unconfirmed state is defined as no merge.

The maximum likelihood decoder 14 as described above is constructed, for example, as shown in FIG. In FIG.
The maximum likelihood decoder 14 connected to the A / D converter 13 includes a first adder 51, a first comparator 52, and a first sign inverter 5.
3, second adder 54, Δ memory 55, second comparator 5
6, a second sign inverter 57, a switch circuit SW ₁ and a third adder 58. The maximum likelihood decoder 14 further includes a memory controller 59, a data memory 60, a comparator 6
1, a register 62, a (1 + D) mod2 converter 63, and an output register 64.

The first adder 51 adds the input data y from the A / D converter 13 (corresponding to a reproduced signal containing noise) and a reference value Δ described later, and adds value Z (= y + Δ). Is output. The added value Z of the first comparator 52 is Z> 1, Z
<-1 and -1 ≤ Z ≤ 1 are discriminated, and "+1" when Z> 1 and "-1" when Z <-1.
And when −1 ≦ Z ≦ 1, “0” is output. The first sign inverter 53 inverts the sign of the output value from the first comparator 52 and outputs the data a. That is, the first comparator 52
When the output value from is "+1", the first sign inverter 53 outputs the data "a" (a = -1) of "-1",
When the output value from the first comparator 52 is “−1”,
Data “a” of “+1” (a = +) from the first sign inverter 53
1) is output. When the output value from the first comparator 52 is "0", the data "a" (a = 0) of "0" is output from the first sign inverter 53. The second adder 54 adds the input data y from the A / D converter 13 and the data a and outputs the added value y + a. The switch circuit SW ₁ has a terminal (1) connected to the second sign inversion circuit 57 and a terminal (2) connected to the second adder 54, and has a terminal (1) or a terminal (2). Is selected according to the state of the data a. When the data a is not "0" (a = +
1 or a = −1) terminal (2) is selected, and the added value y + a from the second adder 54 is stored as the reference value Δ in the Δ memory 55 via the switch circuit SW ₁ (Δ = y +
a). On the other hand, when the data a is “0”, the terminal (1) is selected, and the output value −Δ from the second sign inverter 57, which inverts the sign of the reference value Δ from the Δ memory 55, becomes the new reference value. It is stored in the Δ memory 55 via the switch circuit SW ₁ (Δ = −Δ). The second comparator 56 has a Δ memory 55.
It is determined whether the sign SGN (Δ) of the reference value Δ supplied from is positive or negative. Reference value Δ sign SGN (Δ)
Is positive, the second comparator 56 outputs the discrimination signal “+1”, and when the sign SGN (Δ) of the reference value Δ is negative, the second comparator 56 outputs the discrimination signal “−1”. Third adder 5
Reference numeral 8 adds the discrimination signal (0, ± 1) from the first comparator 52 and the discrimination signal (± 1) from the second comparator 56, and adds the sum (0, ± 1, ± 2). ) Is supplied to the memory controller 59.

The discrimination signal (+1 or -1) from the second comparator 56 is written in the data memory 60. Then, the memory controller 59 inputs the added value (0, ± 1, ± 2) as a control signal and controls the data memory 60 according to the algorithm shown in Table 1.

[0016]

[Table 1] Each data (+1 or − written in the data memory 60
1) is compared with the reference value “0” by the comparator 61, and “+”
1 ”is converted to“ 1 ”and“ −1 ”is converted to“ 0. ”The binary data obtained by the comparator 61 is set in the register 62, and the set data is stored in
+ D) mod2 converter 63 is supplied. And (1+
D) mod2 converter 63 receives (1 + D) mo for the input data.
The d2 conversion is performed to obtain the original 1/7 modulated data. The 1/7 modulated data is set in the output register 64. Then, the data set in the output register 64 is supplied to the demodulator 10 and demodulated in accordance with the 1/7 running length limit.

Maximum likelihood decoder 14 constructed as described above
Operates according to the flowchart shown in FIG. The operation of the maximum likelihood decoder 14 will be described with reference to the examples shown in FIGS.

Input data y from the A / D converter 13_k 
However, as shown in FIG. k y_k           k y_k 1 -1.98 8 -0.1 2-2.05 9 +1.9 3 0.1 10 +2.0 4 +1.95 11 +2.1 5 +1.85 12 +0.1 6-0.113-1.9 7-2.1 And changes. This input data y_k Is shown in Fig. 7 (6).
It is the sampling value of the raw data, including the noise component.
There is.

For example, when k = 2, input data y_k
= -2.05 is input (S100), the first adder
51 is the reference value Δ = obtained from the Δ memory 55 at k = 1
-0.98 and input data y_k = -2.05 and add
The added value Z = −3.03 (= −0.98−2.05)
Is output (S101). Here, this added value Z is -1
Since it is smaller, it is determined that the state of data transition is -merge.
Is determined (S102, S103) from the first comparator 52
The determination result "-1" is output. As a result, "+1"
The data a is supplied from the sign inverter 53 to the second adder 54.
(S110). Also, the reference value from Δ memory 55
Since Δ (= − 0.98) is negative, the second comparator 56
Outputs the determination result "-1" (S111). the above
Switch circuit SW according to the data a of "+1"₁ Is the terminal
(2) is selected, and the added value y in the second adder 54
+ A (= −2.05 + 1 = −1.05) is the Δ memory 55
(S113). Then, the memory controller 59
Inputs the control signal "-2" from the third adder 58
Reset the pointer P of the data memory 60 to "0".
(S114) (see Table 1). And the data memo
The data in Re60 is a _i → a_i-1 Is shifted so that
And the determination result output from the second comparator 56
"-1" (SGN (Δ)) is a0 of the data memory 60
(Corresponding to p = 0) is written (S105).

Next, at k = 3, the input data y _k =
When 0.1 is input (S100), the first adder 51 causes the reference value Δ = −1.
05 and input data y _k = 0.1 are added and the added value Z
= -0.95 (-1.05 + 0.1) is output (S1
01). Here, since the added value Z is in the range of −1 ≦ Z ≦ 1, it is determined that the data transition state is no merge (S102, S103), and the determination result “0” is output from the first comparator 52. Is output. As a result, the data a of "0"
Is output from the sign inverter 53, and this data a
The switch circuit SW ₁ is switched from the terminal (2) to the terminal (1) by (“0”). At this time, the second comparator 56 outputs the determination result “−1” (SGN (Δ)) based on the reference value Δ = −1.05 in the Δ memory 55. Therefore, the memory controller 59 uses the third adder 5
The control signal "-1" is input from 8 and the pointer P of the data memory 60 is incremented to P + 1 (S1).
04) (see Table 1). Then, the sign of the reference value Δ = −1.05 stored in the Δ memory 55 is the second sign inverter 57.
And the new reference value Δ = 1.05 is stored in the Δ memory 55 (S104). This new reference value Δ
= 1.05 is supplied from the Δ memory 55 to the second comparator 56, and the second comparator 56 outputs the determination result “+1”. After that, the data in the data memory 60 is changed to a _i → a
_The determination result “+1” (SGN (Δ)) shifted to _i−1 and output from the second comparator 56 is written in a 0 of the data memory 60 (S105).

Further, when k = 4, the input data y _k =
When +1.95 is input (S100), the first adder 5
1 is the reference value Δ = obtained from Δ memory 55 at k = 3
1.05 and the input data y _k = 1.95 are added and the added value Z = 3.0 (= 1.05 + 1.95) is output (S101).

Since the added value Z is larger than 1, it is determined that the data transition state is + merge (S
102), the determination result “+1” is output from the first comparator 52. As a result, the data "a" of "-1" is supplied from the sign inverter 53 to the second adder 54 (S120).
Further, since the reference value Δ (= 1.05) from the Δ memory 55 is positive, the determination result “+1” from the second comparator 56.
(SGN (Δ)) is output (S121). Above "-
The switch circuit SW ₁ has a terminal (1) according to the data a of 1 ″.
To the terminal (2), and the added value y + a (= + 1.95-1 = 0.95) in the second adder 54 is the Δ memory 5
5 is stored (S123). And the memory controller 5
9 receives the control signal "+2" from the third adder 58, and the pointer P (= 1) of the data memory 60 is reset to "0" (S114) (see Table 1). Then, the data in the data memory 60 is shifted so that a _i → a _i−1, and the determination result “+1” (SGN (Δ)) output from the second comparator 56 is the data memory 60. Is written to a0 (corresponding to P = 0) (S10
5).

The above-mentioned processing is repeated.
In the process of the process, the content of the data memory 60 is fixed every time the pointer P is reset to "0". As described above, in the no merge state, the pointer P is incremented and “+1” or “−1” corresponding to the sign of the reference value Δ is sequentially written in the data memory 60. Then, in the + merge state, the reference value Δ is positive or -me.
When the reference value Δ becomes negative in the state of rge, the data stored in the data memory 60 in the no merge state and the subsequent +
The data stored in the data memory in the merge or − merge state is fixed. On the other hand, after no merge state, +
In the state of merge, the reference value Δ becomes negative, or in the state of − merge, the reference value Δ becomes positive.
sagree), data memory 60 with no merge
A0 to aP stored in (where P is the value of pointer P)
Is calculated (S112, S122), and the data a _{0 to} a _P in the data memory 60 is rewritten to its complement. After that, the pointer P is reset to "0" (S
113, S123) The contents of the data memory 60 are confirmed.

The above processing is based on the fact that the data transition path is not fixed in the no merge state. That is, the data transition path in the no merge state is 0 → depending on whether the state is + merge or − merge.
1 or 1 → 0 (see FIG. 5) is determined. In this way, the most probable transition path is established.

In the data memory 60, as described above,
"+1" or "-1" is stored. Each data (“+
1 "or" -1 ") is a reference value" 0 "by the comparator 61.
Is converted into “1” or “0” by comparison with the output data of the comparator 61 (see FIG. 8 (17)).
Are stored in the register 62. The data string stored in the register 62 corresponds to the data transition path shown in FIG. 8 (8). Thereafter, the (1 + D) mod2 converter 63 converts the data in the register 62 according to the (1 + D) mod2, and the converted data is stored in the output register 64 (see (18) in FIG. 8). The data obtained by this (1 + D) mod2 conversion is the original 1/7 modulated data (see FIG. 7).
(See (2)). And the output register 6
The data stored in No. 4 is supplied to the demodulator 10, and the demodulator 10 performs 1/7 running length limited demodulation to obtain the original data (see FIG.
(See (1)) is obtained.

Next, referring to FIGS. 11 and 12, 1 /
An embodiment of a maximum likelihood decoder that performs a maximum likelihood signal in consideration of the rule of 7 running length limitation will be described.

In a bit string arranged according to the rule of 1/7 running length restriction, there is always one or more "0" between "1" and eight or more "0" s. Are not continuous. According to such a rule, the bit next to "1" is always "0", and the bit next to seven consecutive "0" s is always "1". 1/7 from the input data
The data of running length limitation (hereinafter referred to as 1/7 data) is demodulated.

The maximum likelihood decoder according to this embodiment is configured as shown in FIG. 11, for example. 11, in the same manner as shown in FIG. 9, a first adder 51, a first comparator 52,
First sign inverter 53, second adder 54, Δ memory 5
5, second comparator 56, second sign inverter 57, switch SW ₁ , third adder 58, memory controller 59, data memory 60, comparator 61, register 62, (1 + D)
A mod2 converter 63 and an output register 64 are provided. The maximum likelihood decoder further includes a fourth adder 70, a third comparator 71, a fifth adder 72, a fourth comparator 73, a switch controller 74, and switches SW ₂ and SW ₃ . ing.

The fourth adder 70 adds the least significant bit a ₀ and the next bit a ₁ in the data memory 60 (a ₀ + a ₁ ), and outputs the addition result Σ2 to the third comparator 71.
Supply to. The third comparator 71 outputs "1" when the addition result Σ2 of the fourth adder 70 is "0" (Σ2 = 0), and when the addition result Σ2 is not "0" (Σ2 ≠
0) and "0" are output. The possible values of a ₀ and a ₁ and the corresponding addition result Σ2 are as follows.

A ₀ a ₁ Σ2 +1 +1 +2 +1 -1 0 -1 +1 0 -1 -1 -2 Therefore, the third comparator 71 has a ₀ = + 1 and a ₁ = -1.
And a ₀ = −1, a ₁ = + 1, “1” is output, and a ₀
= + 1, a ₁ = + 1 and a ₀ = −1, a ₁ = −1, “0” is output. with c ₁ corresponding to c ₀ and a ₁ corresponds to _{a 0 (1 + D) mod2} d 0 after conversion is obtained. In this case, d ₀ = 1 when the output of the third comparator 71 is “1”, and d ₀ = 0 when the output of the third comparator 71 is “0”. Here, in order to satisfy the above condition that the bit next to “1” must be “0”, if the output of the third comparator 71 becomes “1”, the next input y = d ₀ = a ₀ of the data memory 60
The value must be set to 0.

The fifth adder 72 is provided in the data memory 60.
All bits (8 bits) a0 to a7 of (a₀ + A₁
 + A₂ + ... + a₇ ), The fourth comparison of the addition result Σ8
Supply to the container 73. The fourth comparator 73 is a fifth adder
When the addition result Σ8 at 72 is ± 8 (Σ8 = ± 8),
When "1" is output and the addition result Σ8 is not ± 8
(Σ8 ≠ ± 8), “0” is output. That is, data memo
All bits a in re 60 ₀ ~ A₇ Is “+1” or all
Bit a₀ ~ A₇ Is "-1", the fourth comparator
73 outputs “1”, otherwise, the fourth comparison
The device 73 outputs "0". All in data memory 60
Bit a₀ ~ A₇ Is "+1" or all the bits are "-"
When 1 ", all bits d of 1/7 data₀ ~ D₆ But
It becomes "0". Therefore, the above seven consecutive "0" s
Condition that the next bit must be "1"
To satisfy the condition, the output of the fourth comparator 73 is “1”.
, The next input y is a in the data memory 60.₀ 
To d₀ Must be set to a value such that = 1
Yes.

The input data y from the A / D converter 13 is supplied to the terminal a of the switch SW _2, the switch SW ₂
Is connected to the output terminal of the switch SW ₃ . The output terminal of the switch SW ₂ is connected to the first and second adders 51 and 54 and also to the terminal a of the switch SW ₃ . The input data y input through the switch SW ₂ is further supplied to the third sign inverter 75, and the output of the third sign inverter 75 is the switch SW.
It is connected to terminal b of ₃ . The switch control unit 74
Output signals from the third comparator 71 and the fourth comparator 73 are input, and switching control of the switches SW2 and SW3 is performed so that the above-described conditions are satisfied according to the states of these output signals. To do. That is, the switching control of the switches SW2 and SW3 is performed according to the rules of Table 2.

[0033]

[Table 2] The maximum likelihood decoder configured as described above operates according to the flowchart shown in FIG.

In FIG. 12, when new input data y is given to the maximum likelihood decoder (S200), the input data y0 given last time is defined as the previous data y1, and the new input data y is the current data y0. Is defined as (S
201). Then, all bits a ₀ to
The sum Σ8 of a ₇ is not “± 8”, but the sum of a ₀ and a ₁ (Σ
2) is not "0" (when the output of the third comparator 71 is "0" and the output of the fourth comparator 72 is "0")
(S202, S203), current data y0 is processed data y
Defined as 2. . That is, the switch SW ₂ has the terminal a
Is selected (see Table 2) and the current data y0 is supplied to the first and second adders 51 and 54 as the data y2 to be processed. (S207, S223, S233). In this case, as in the case described with reference to FIGS. 9 and 10, the data y2
Is processed. That is, when the data transition state is determined to be + merge (S208), step S1 in FIG.
20, S121, S123, S114, S105, steps S230, S231, S233, S22.
4, the processing is performed in accordance with S211, and the data memory 6
Each bit a _{0 to} a _{7 of 0} is shifted by one bit, and the code data SGN (Δ) of the reference value Δ (= y 2 −1) stored in the Δ memory 55 in step S233 is stored in the data memory 60. It is stored in the lower bit a ₀ . Then, the third and fourth adders 71 and 73 are updated with a ₀
The addition results Σ2 and Σ8 are output using the data a to a ₇ (step S212). Also, the state of data transition is −
If it is determined to be merge (S208, S209), FIG.
Steps S110, S111, S113, S1 in
14 and S105, steps S220 and S22
1, S223, S224, S211 processing is performed in accordance with, with a ₀ ~a ₇ is shifted, step S2
Reference value Δ (= y2 + stored in Δ memory 55 at 23)
The code data AGN (Δ) of 1) is stored in the least significant bit a ₀ of the data memory 60. Furthermore, when the data transition state is determined to be no merge (S208, S209), the same as step S104 and S105 in FIG.
Processing is performed according to steps 210, S211, and S212. That is, the pointer P is incremented by 1, the reference value code is inverted from the second sign inverter 57 delta is stored in the delta memory 55, it is further shifted a ₀ ~a _7, in step S210 The code data SGN (Δ) of the reference value Δ (= − Δ) stored in the Δ memory 55 is stored in the least significant bit a ₀ of the data memory 60.

On the other hand, when the sum Σ2 of a ₀ and a ₁ of the data memory 60 becomes "0" (S202, S204), that is, the output of the third comparator 71 is "1" and the fourth comparator 73. When the output of the switch becomes "0", the switch SW ₂ turns to the terminal a.
To terminal b and switch SW ₃ selects terminal a (see Table 2). As a result, the previous input data y is supplied again to the first adder 51 via the switches SW ₃ and SW ₂ . That is, the previous data y1 is the data y to be processed.
It is defined as 2 (S205). Sum of a ₀ and a ₁ Σ
The fact that 2 is “0” means that the values of a ₀ and a ₂ obtained last time are different (+1 and −1), and in this case, 1
The least significant bit d ₀ of the / 7 data is “1”. Here, as described above, before the defined as data y2 to process data y1, obtained by a ₀ (the current process obtained by values and the previous process of a ₀ obtained in the current processing a
The values of ₁ ) are equal. In this case, the corresponding comparator 61
Since the values of the output bits c ₀ and c ₁ are also equal to each other, the least significant bit d ₀ of the newly obtained 1/7 data is “0”. That is, the 1/7 running length restriction rule that one or more "0" s exist between "1" s is satisfied.

As described above, a _{0 of the} data memory 60
And the sum Σ2 of a ₁ becomes “0”, no matter what input data y is given, the previous data y 1 is defined as the data y 2 to be processed, so that the rule of 1/7 running length limitation is satisfied. To be done.

On the other hand, all bits of the data memory 60
a₀ ~ A₇ When the sum Σ8 of the two becomes “± 8” (S20
2) That is, the output of the third comparator 71 is "0" and the fourth
When the output of the comparator 73 of “1” becomes “1”, the switch SW₂ 
Holds terminal b, switch SW ₃ Is terminal a to terminal b
(See Table 2). As a result, the input data yButFirst
Three sign inverter 75, switch SW₃ And SW₂ Through
Are supplied to the first adder 51. That is, the previous data y1
Data y2 in which the sign of the data is inverted-data y2 to be processed
Is defined as (S203). All of the data memory 60
Bit a₀ ~ A₇ That the sum Σ8 of is ± 8
All bits a₀ ~ A₇ Are all equal (-1 or +
1), which is 7 bits d of 1/7 data in this case.
₀ ~ D₆ Are all "0". Where, as above,
The data -y1 with the sign of the previous data inverted must be processed.
Defined as data, a obtained by this process₀ The value of the
And a obtained in the previous processing₀ (A obtained by this process
₁ ) Is different. In this case, the output of the corresponding comparator 61
Force bit c₀ And c₁ Since the values of are different (“1” and
"0" or "0" and "1"), newly obtained 1/7
Least significant bit d of data₀Becomes "1". That is, the above
1/7 run that 8 or more "0" s are not consecutive
Satisfies the long limit rule.

As described above, when the sum Σ8 of all the bits a _{0 to} a ₇ of the data memory 60 becomes "± 8", no matter what input data y is given, the data obtained by inverting the sign of the previous data y1. By defining -y1 as the data y2 to be processed, the rule of 1/7 running length limitation is satisfied.

The data transition states are + merge and −.
In the case of merge, when the comparison result SGN (Δ) (code data) in the second comparator 56 is different from the value that it should originally take (disagree), as in the embodiments of FIGS. 9 and 10, the data memory The values from a0 of 60 to aP designated by the pointer p are replaced by their complements.

According to the above embodiment, since maximum likelihood decoding is performed in consideration of the rule of 1/7 running length limitation, it is possible to more reliably reproduce data from the optical disc.

In the above embodiment, whether or not the least significant bit d ₀ of 1/7 data is “0” is determined based on the value of the sum Σ2 of a ₀ and a _{1 in} the data memory 60. ing. Furthermore, it is also possible to make a determination based on the values of the output bits c ₀ and c ₁ of the comparator 61. Exclusive OR of output bits c ₀ and c ₁ of the comparator 61 (c ₀ EXOR c ₁ )
Is as follows.

[0042] a₀     a₁     c₀     c₁     c₀ EXOR c₁ +1 +1 1 1 0 +1 -1 1 0 1 -1 +1 0 1 1 -1 -1 0 0 0 The least significant bit d0 of 1/7 data becomes "0"
This is when the exclusive OR (c0 EXOR c1) is 0. Servant
Therefore, the output bit c of the comparator 61₀ And c₁ Exclusive Theory
Sum (c₀ EXOR c₁ ), The bottom of the 1/7 data
Place bit d₀ It is possible to determine whether is "0"
Wear.

Furthermore, it is also possible to directly control the switches SW ₂ and SW ₃ based on the value of the least significant bit d ₀ of the 1/7 data stored in the output register 64.

Next, referring to FIGS. 13 and 14, 2 /
An embodiment of a maximum likelihood decoder that performs maximum likelihood decoding in consideration of the rule of 7 running length limitation will be described. In this case, 2 /
Data is written to the optical disc in accordance with the rule of 7 running length limitation.

In a bit string arranged according to the rule of 2/7 running length limitation, there are always two or more "0" s between "1" and "1" and eight or more "0" s. Not continuous. According to this rule, the next bit of "1" is always "0", the next bit of "1,0" is always "0", and the next bit of seven consecutive "0" s is always "0". 1 ”. This 2/7 running length limited data (hereinafter referred to as 2/7 data) is demodulated from the input data.

The maximum likelihood decoder according to this embodiment is configured as shown in FIG. 13, for example. 13, the same components as those shown in FIG. 11 are designated by the same reference numerals. In this example, an adder 70 'is provided in place of the fourth adder 70 shown in FIG. The adder 70 ′ adds the least significant bit a ₀ and the third bit a ₂ of the data memory 60, (a ₀ + a ₂ ), and supplies the addition result Σ3 to the third comparator 71. The third comparator 71 is similar to that shown in FIG. 11, and the addition result Σ in the adder 70 ′ is
When 3 is “0” (Σ3 = 0), “1” is output, and when the addition result Σ3 is not “0” (Σ3 ≠ 0), “0”
Is output. The possible values of a ₀ , a ₁ and a ₀ and the corresponding addition result Σ3 are as follows.

A ₀ a ₁ a ₂ Σ3 +1 +1 +1 +1 +2 +1 +1 −1 0 +1 −1 +1 +1 +2 −1 +1 +1 0 0 +1 −1 −1 0 −1 +1 −1 −2 −1 −1 +1 0 −1 −1 −1 −2 Therefore, the third comparator 71 has (a ₀ , a ₁ , a ₂ ) =
(+1, +1, -1), (-1, +1, +1), (+
"-1," when 1, -1, -1), (-1, -1, + 1)
Is output, and (a ₀ , a ₁ , a ₂ ) = (+ 1, +1, +
1), (+ 1, -1, + 1), (-1, + 1, -1),
When it is (-1, -1, -1), "0" is output. Above a
Output bits c of the comparator 61 for 0, a1 and a2
_{The 0} , c ₁ , c ₂ and corresponding 2/7 data are as follows.

[0048]       a₀     a₁     a₂     c₀   c₁   c₂       d₀   d₁     +1 +1 +1 1 1 1 1 0 0     +1 +1 -1 1 1 0 0 1     +1 -1 +1 1 0 1 1 1 1     -1 +1 +1 0 1 1 1 1 0     +1 -1 -1 1 0 0 1 1 0     -1 +1 -1 0 1 0 1 1 1     -1 -1 +1 0 0 1 0 1     -1 -1 -1 0 0 0 0 0 0 Here, the bit next to the above "1" is always "0".
If the bit next to "1,0" is always "0",
In order to satisfy the condition, the output of the third comparator 71
Becomes "1", the next input y causes the data memory 60
Of a₀ To d₀ If a value such that = 0 is not set
I won't.

The fifth adder 72 and the fourth comparator 73 are the same as those shown in FIG. 11, and in the reproduced 2/7 data (d _{0 to} d ₆ ), "0" is 7 consecutively. It is determined whether or not it is lined up.

Since the maximum likelihood decoding is performed in consideration of the rule of the 2/7 running length limitation described above, the switch controller 74 operates as shown in FIG.
Similarly to the one shown in (1), the output signals from the third comparator 71 and the fourth comparator 73 are input, and the switches SW2 and SW3 are controlled according to the rules of Table 2.

The maximum likelihood decoder constructed as described above operates according to the flowchart shown in FIG.

This operation is performed by the flow chart shown in FIG.
Is almost the same as the operation according to. That is, the third comparator 7
When the outputs of the first and fourth comparators 73 are "0" (S20
2, S204 '), normal maximum likelihood decoding is performed. However
But it cannot happen (d₀ , D ₁ ) = (1,1)
Corresponding (a₀ , A₂ , A₃ ) = (+ 1, -1, +
1) and (-1, +1, -1), the third comparator 71
Output becomes "0". In this example, if
When a problem occurs, allow such a state and
Normal maximum likelihood decoding is performed (without particular correction).

On the other hand, the output of the third comparator 71 is "1",
When the output of the fourth comparator 73 is "0", the previous data y is set so that the least significant bit d0 of the 2/7 data becomes "0".
1 is defined as the data y2 to be processed. When the output of the third comparator is “0” and the output of the fourth comparator 73 is “1”, the previous data y1 is set so that the least significant bit d ₀ of the 2/7 data becomes “1”. The data -y1 whose sign is inverted is defined as the data y2 to be processed. The subsequent processing is the same as the processing shown in FIG.

In the above embodiment, the exclusive OR (c ₀ EXOR c ₂ ) of the output bits c ₀ and c ₂ of the comparator 61, or the least significant bit d ₀ and the second bit d 2 of 2/7 data. 2 based on exclusive OR with ₁ (d ₀ EXOR d ₁ )
It is possible to determine whether or not the least significant bit d ₀ of the / 7 data should be set to “0” ((d ₀ , d ₁ ) = (0, 1), (1, 0)). .

Also in this embodiment, since maximum likelihood decoding is performed in consideration of the rule of 2/7 running length limitation, it is possible to more reliably reproduce data from the optical disc.

By the way, the reproduction waveform of the optical disk has a band up to direct current (DC), but an actual circuit for processing the reproduction waveform has a band in order to remove the influence of DC offset or the like. Since the low frequency band such as DC is limited to the cut region, the signal waveform processed by the circuit is
Low frequency fluctuation occurs depending on the recording pattern. In addition, a substrate made of polycarbonate is often used for the optical disc, but in general, the polycarbonate that is the material of the substrate of the optical disc has a large unevenness of the reflected light due to the birefringence, and the reproduction signal envelope fluctuates to detect the signal (slice detection). Has a disadvantage that the margin of is small. That is, as shown in FIG. 15, the reproduction signal corresponding to the recording signal (LD drive signal) does not change centering on the zero level (0), but the center level Ck thereof gently changes.
In this way, if the reproduced signal fluctuates in the low frequency range due to DC or the envelope fluctuates and shifts in the amplitude direction during A / D conversion,
For example, the added value Z of the reference value Δ and the sampling value y obtained in the maximum likelihood decoding process shown in FIG. 10 emphasizes the DC component. Further, since the detected data is the code SNG (Δ) representing the code of the reference value Δ, the code SNG (Δ) is affected by the DC component of the reproduction signal. As a result, accurate data detection is impaired and the error rate deteriorates.

Further, in the maximum likelihood decoder 14 described above, the detected data is converted into a running length limiting code before precoding (for example, 1/7).
The detected data is (1 + D) mo for decoding into a modulated signal).
d2 needs to be converted. Since (1 + D) mod2 conversion is performed using two detection data at adjacent timings (see (18) in FIG. 8), if one detection data error occurs, finally two demodulation data errors occur. Will occur.

Therefore, the following embodiment is intended to further improve the above problems.

The maximum likelihood decoder 14 according to this embodiment is similar to that shown in FIG.
It is configured as shown in FIG. In FIG. 16, the maximum likelihood decoder 14 has a merge determination unit 141, a center value calculation unit 142, a reference value calculation unit 143, and a merge detection unit 144. Merge determination unit 141 performs the merge determination for the input data y _k by using the reference value delta _k from the reference value calculation unit 143 to be described later as the input data y _k from the A / D converter 13, the determination value Output M _k .

This merge judgment unit 141 is shown in FIG.
Processing according to the flow shown in is performed. That is, using the new input data y _k and the reference value Δ _k , Z _k (= y _k −Δ
_k ), and depending on its value, + merge, -merge, no mer
Determine ge. When + merge (Z _k > 1), the judgment value M _k =
( _{M k1} , m _k2 ) = 01 is output, and -merge (Z _k <-1)
, The judgment value M _k = 10 is output, and no merge

[0061]

[Equation 1] When, the judgment value M _k = 00 is output. The process in the merge determination unit 141 is step S1 in FIG.
It corresponds to 00 to S103. In order to realize the processing as described above, the merge determination unit 141 is, for example, as shown in FIG.
, The subtractor 1411 (Z _k = y _k −Δ _k ), the first comparator 1412 (Z _k <−1), and the second comparator 1
413 (Z _k > 1).

The central value calculation unit 142 performs processing according to the flow shown in FIG. That is, when a new input signal y _k is given, the central value data C _kd corresponding to the Z _k value obtained by the merge determination unit 141 is calculated. Z
_{When k} > 2, the center value data C _kd is calculated according to C _kd = y _k −2,

[0063]

[Equation 2] In case of, the central value data C_kdBut, C_kd= C_k-1ave According to Z_k If <-2, the median value
Data C_kdBut, C_kd= Y_k +2 Is calculated according to. Z_k When> 2, surely input
Data y_k Is the state of + merge, so its input data
y_k By subtracting the ideal amplitude value “2” from
Heart value data C_kdIs obtained (see FIG. 7 (6)). Z_k 
When <-2, the input data y is definitely_k But-merge
The input data y_k From an ideal negative swing
By reducing the width value "-2", the center value data C_kdTo
Looking for. Also

[0064]

[Equation 3] The case of is a case where it cannot be reliably determined as + merge or -merge (including no merge), so the previous center value C _k-1ave calculated as described later is used as the center value data C _kd . The center value C _kave is calculated by using the center value data C _kd calculated as described above and the previously obtained center value C _{k- 1ave.}
Is calculated according to C _kKave = [(n-1) C _k-1ave + C _kd ] / n. Central value C calculated in this way
_kave corresponds to the average value of the n pieces of center value data C _kd .
The curve _{connecting the} center values C _kave represents the center level C _k of the reproduction signal shown in FIG.

In order to realize the above processing, the central value
The arithmetic unit 142 is configured, for example, as shown in FIG.
Is made. In FIG. 23, the central value calculation unit 142
Is Z_k First comparator 1421, Z for judging <-2_k 
Second comparator 1422, constant output circuit 1 for determining> 2
423 (Rk), adder 1424, multiplexer 14
25, subtractor 1426, divider 1427, adder 142
8, the multiplier 1429 and the count value n are set
It has a register 1430. The first comparator 1421
Z of Z_k <-2 judgment result l1 and second comparator 1422
From Z_k Constant output circuit 1 according to the determination result l2 of> 2
423 is a constant R_k Output (8 bits). This constant R
_k Is-(l₁ = 0, l₂ = 1) or 2 (l₁ = 1,
l₂ = 0). The adder 1424 receives the input data y_k When
Constant R_k Add (-2 or 2). Multiplexer 1
425 is from the first and second comparators 1421, 1422
Judgment result L_k = (L₁ , L₂ ) According to
Addition result y from 4_k + R _k Or in the adder 1428
Central value C calculated twice_k-1aveCentral value data
C_kdTo choose as. The judgment result L_k = (L₁ , L₂ )
When is (0,0) (corresponding to no merge), it is calculated last time
Center value C_k-1aveIs selected. Subtractor 1426 is round
Center value data C from the Chiplexer 1425_kdFrom last performance
Calculated central value C_k-1aveSubtract. The divider 1427 is
Calculation result C from the subtractor 1426_kd-C_k-1aveThe regis
Data is divided by the count value n set in the data 1430 and calculated.
Value ([C_kd-C_k-1ave] / N) is output. Adder 14
28 is a calculated value ([C_kd−
C_k-1ave] / N) and the center value Ck-1ave calculated last time
Central value C of this time_kave C_kave= C_k-1ave+ [C_kd-C_k-1ave] / N Is output. Multiplier 1429 is inside adder 1428
Heart value C_ave Is doubled to 2C_kaveIs output. Twice this
Center value 2C_kaveIs used in the reference value calculation unit 143.
Be done.

The reference value calculation unit 143 is, for example, as shown in FIG.
Processing is performed according to the flow shown in 19. That is, merge format
Judgment value M from the constant unit 141_k Reference value according to
_{k + 1} Is output. Judgment value M_k = 01 (Z_k > 1: + merg
In case of e), the reference value Δ_{k + 1}= 2C _kave-Y_k +1 is output
To be done. Judgment value M_k = 10 (Z_k <-1: -merge)
Standard value Δ_{k + 1} = 2C_kave-Y_k -1 is output.
Also, the judgment value M_k = 00

[0067]

[Equation 4] In the case of, the reference value Δ _{k + 1} = 2C _kave −Δ _k is output.
These reference values Δ _{k + 1} are the reference values (Δ _{k + 1} = y _k −1), (Δ _{k + 1} = y _k +1) and (Δ _{k + 1} = −) obtained by the processing of FIG. Δ _k ) is corrected by the center value C _kave .

In order to realize the above processing, the reference value calculation unit 143 is constructed, for example, as shown in FIG. That is, the reference value calculation unit 143 includes the constant output circuit 1431, the adder 1432, and the multiplexer 14
33 and a subtractor 1434. The constant output circuit 1431 outputs a constant Q _k (8 bits) according to the determination value M _k . When the judgment value M _k = 01 (+ merge),
The constant Q _k = -1 is output, and the determination value M _k = 10 (-merg
In the case of e), the constant Q _k = 1 is output, and the determination value M _{k is} further output.
= 00 (no merge), the constant Q _k = 0 is output. The adder 1432 adds the input data y _k and the constant Q _k from the constant output circuit 1431 to obtain the added value y _k + Q.
Output _k . The multiplexer 1433 selects either the added value y _k + Q _k from the adder 1432 or the previously calculated reference value Δ _k from the subtractor 1434 according to the determination value M from the merge determiner 141. That is, M _k = 0
When 1 and 10, the added value y _k + from the adder 1432
Q _k is selected, when the determination value M _k = 00, the reference value delta _k which is previously calculated is selected. The subtractor 1434 uses the value W _k (y _k + Q _k or Δ selected by the multiplexer 1433 from the 2C _kave from the central value calculation unit 142.
_k ) is subtracted and the above-mentioned next reference value Δ _{k + 1} is output.

The merge detection unit 144 changes the input data y _k from -merge to + merge and + merge to -merge based on the determination value M _k from the merge determination unit 141.
Change to. The specific processing of the merge detection unit 144 is performed according to the flow shown in FIG. In the process, variables A _k = (a _k1 , a _k2 ) ≠ (0,
0) (1,1) is defined and M _k = 00 (no merge) and M _k = A _k (no change at + merge or -merge),
The previous variable A _k is not changed (A _k = A _{k + 1} ). Also, M _k ≠ A _k (change from + merge to -merge or -merge
Change from + to + merge), the variable A _{k + 1} is set to the previous determination value M _k (A _{k + 1} = M _k ). Then, the data d _k is

[0070]

[Equation 5] Is calculated according to. The above no merge and + merge or -mer
When there is no change in ge, d _k = 0, and the change of input data y _k from + merge to -merge and -merge to + merge
If there is a change to, then d _k = 1 (see FIG. 25). The output data d _k from this merge detection unit 144 is further demodulated to 1/7 and becomes the output data of the maximum likelihood decoder 14.

In order to realize the above processing,
For example, as shown in FIG.
Composed. That is, the merge detection unit 144 determines
Value M _k And A_{k + 1} And from a_{k + 11}To

[0072]

[Equation 6] According to the first arithmetic unit 1441, _{ak + 12}

[0073]

[Equation 7] Second computing unit 1442 and the determination value M _k for calculating according to
And the data d _k from a _{k + 11} and a _{k + 12}

[0074]

[Equation 8] And a third computing unit 1443 for computing according to.

According to the maximum likelihood decoder 14 having the above configuration
For example, as shown in FIG. 25, the reproduced signal has a low-frequency envelope.
Criteria for determining the merge status even if there is
Value Δ _k Is the input data y_k Center value C of_k Gently following the
The reference value Δ_k More certainty
Data can be demodulated. Also, (1+
D) Merge determination unit 1 without using mod2 conversion
Judgment value M from 41_k Direct input data based on
Rise (change from -merge to + merge) and fall
To detect (change from + merge to -merge), temporarily enter
Force data y_k Even if one is wrong, the error is one
It only affects the demodulated data of. Therefore, the error
It is possible to improve the environment.

FIG. 26 shows the relationship between the low band noise amplitude (%) and the error rate. The characteristic Q2 of the maximum likelihood decoding according to the present embodiment is improved with respect to the characteristic Q1 of the maximum likelihood decoding according to the process shown in FIG. Note that, in FIG. 26, the low-frequency noise amplitude is represented with the amplitude of the reproduced signal being 100 (%).

The size of the marks recorded on the optical disk (length in the direction in which the track extends) fluctuates due to uneven sensitivity of the optical disk, environmental temperature changes during data recording, and fluctuations in light spot control. In this way, when the size of the mark recorded on the optical disc changes, the reproduced signal waveform obtained from the optical disc also changes. In particular, since the maximum likelihood decoder 14 reproduces the data signal corresponding to the edge of the recording mark, the mark size changes in the reproduced data signal corresponding to the leading edge and the reproduced data signal corresponding to the trailing edge. The direction of the phase change with is different. That is, as shown in FIG. 27, when recording pits (recording marks) become large by writing data on the optical disc at high temperature, and as shown in FIG. 28, recording pits by writing data on optical disc at low temperature. When the (recording mark) becomes small, the interval between the front edge and the rear edge in each recording pit is different. Therefore, the data corresponding to each edge cannot be obtained by one synchronization signal. However, even if each recording pit changes due to a change in environmental temperature, the front edge interval and the rear edge interval of the adjacent recording pits are substantially constant as shown in FIGS. 27 and 28. Therefore, the front edge synchronization clock synchronized with the front edge of the recording pit (corresponding to the rising edge of the reproduction signal),
Rear edge of recording pit (corresponding to falling of playback signal)
Accurate demodulation is possible by sampling the data by the edge clock after synchronizing with. In this case, the configuration of the signal reproduction system is as shown in FIG.

In FIG. 29, this signal reproduction system has a center level binarization circuit 21, an edge detection circuit 22, a first PLL circuit 23 and a second PLL circuit 24. The center level binarization circuit 21 binarizes the reproduced signal waveform (1) using the reference level (Lc) corresponding to the midpoint of the amplitude. The edge detection circuit 22 detects the rising and falling edges of the binary signal (2) supplied from the center level binarization circuit 21, and detects the leading edge detection signal (3) corresponding to the rising edge and the falling edge. The edge detection signal (4) is output. Then, the first PLL circuit 23 generates the front edge synchronization clock (5) based on the front edge detection signal (3), and the second PLL circuit 24 outputs the rear edge detection signal (4).
A rear edge synchronization clock (6) is generated based on

The states of the signals (1) to (6) are shown in FIG.
Shown in.

The signal reproduction system further includes a first maximum likelihood data detection circuit 25a, a second maximum likelihood data detection circuit 25b, and an OR circuit 26. The first maximum likelihood data detection circuit 25a operates in synchronization with the front edge synchronization clock (5), and the second maximum likelihood data detection circuit 25b operates in synchronization with the rear edge synchronization clock (6). The first and second maximum likelihood data detection circuits 25a and 25b have the same configuration as shown in FIG. And the merge detection unit 1
44 is configured as shown in FIG. 31, and the processing is performed according to the flow shown in FIG. That is, as in the above embodiment,
The merge detection unit 144 includes a first arithmetic circuit 1441 for calculating a _{k + 11} and a second arithmetic circuit 1 for calculating a _{k + 12.}
442 with front edge data def _k

[0081]

[Equation 9] According to the third arithmetic circuit 1444 and the rear edge data der _k

[0082]

[Equation 10] It has a fourth arithmetic circuit 1445 which calculates in accordance with. In the first maximum likelihood data detection circuit 25a which operates in synchronization with the front edge synchronization clock (5), the input signal y
_The leading edge data def _k = 1 due to the change from -merge to + merge corresponding to the rise of _k . Further, in the second maximum likelihood data detection circuit 25b which operates in synchronization with the rear edge synchronization clock (6), the rear edge data is changed by the change from + merge to -merge corresponding to the fall of the input signal y _k. der _k = 1. First maximum likelihood data detection circuit 25a
Edge data after the leading edge data def _k and the second maximum likelihood data detecting circuit 25a from der _k is an OR circuit 26
And the final decoded data is obtained.

According to the above embodiment, it is possible to provide a maximum likelihood data detection circuit capable of independently detecting the leading edge corresponding to the rising edge of the reproduced signal and the trailing edge corresponding to the falling edge of the reproduced signal. It will be possible. As a result, accurate data can be obtained by maximum likelihood demodulation even if the size of the recording pit (recording mark) changes due to environmental temperature or the like.

In each of the above-mentioned embodiments, data is recorded on the optical disk (magneto-optical disk) by the so-called elongated hole method, and the edge of the reproduction signal has a meaning as data. Therefore, in the above-mentioned embodiment, it was not possible to directly reproduce data from the optical disc on which the so-called recording pit itself was recorded by the short hole method corresponding to the data "1". Therefore, a system capable of reproducing data by maximum likelihood decoding will be described next, even for an optical disc on which data is recorded by either the long hole method or the short hole method.

FIG. 33 shows a magneto-optical disk according to this embodiment.
The playback system of the device is shown. In Fig. 33, the playback system is
4, the optical disc 1, the optical head 2,
Amplifier 6, filter / equalizer 7, first and second P
LL circuits 9a and 9b, demodulator 10, first and second A /
D converters 13a and 13b, maximum likelihood decoder 14, binarization circuit
21 and an edge detection circuit 22. This playback system
Further, the switching logic circuit 15 and the recording system detection
It has a container 16. The maximum likelihood decoder 14 is similar to the one shown in FIG.
It is composed of one circuit and a second circuit, each of which is shown in FIG.
And its merge detection unit
144 is configured as shown in FIG. 31, and the first circuit is
Edge data def_k And the second circuit detects the trailing edge
Data der _k It is designed to detect Recording method detection
The device 16 does not record data on the optical disc 1 by the long hole method.
Output level 1 select signal sel
However, if data is recorded by the short hole method, the level is
The selection signal sel of "0" is output. Switching logic
The circuit 15 is, for example, as shown in FIG.
Front edge data from 14 def_k And recording method detector 1
AND circuit 151 for inputting the selection signal sel from 6 and
The output signal from the AND circuit 151 and the maximum likelihood decoder 14
Trailing edge data der_k And the OR circuit 152 for inputting
Have

In the magneto-optical disk device having the above-described structure, when the recording method detector 16 detects that data is recorded on the optical disk 1 by the long hole method, the level is set to "1" (high level). Outputs the selection signal sel. As a result, the AND circuit 151 enters the allowable state, and the front edge data signal def _k and the rear edge data signal der _k from the maximum likelihood decoder 14 are supplied to the demodulation circuit 10 in the subsequent stage via the switching logic circuit 15. On the other hand, the recording system detector 16
When it detects that data is recorded on the optical disc 1 by the short hole recording method, it outputs the selection signal sel of level "0" (low level). As a result, the AND circuit 151 is disabled, and only the trailing edge data signal der _k from the maximum likelihood decoder 14 is supplied to the demodulation circuit 10 via the switching logic circuit 15.

FIG. 35 shows an example of signal processing for detecting short hole recording data maximum likelihood decoding. In this case, the laser drive signal and the reproduction signal are different from the case of the long hole recording data maximum likelihood decoding detection shown in FIGS. 7 and 8. Then, only the trailing edge data der _k is 1/7 demodulated as the final data.

According to the above embodiment, it is possible to reproduce the record data recorded by both the long hole method and the short hole method by the maximum likelihood decoding process.

In the above-described embodiment, each data is handled by 8 bits, but it may be 7 bits or more.

When the maximum likelihood detection method for independently detecting the leading edge and the trailing edge described above and the maximum likelihood detection method for the record data recorded by the long hole method and the short hole method are both performed, FIG. The OR circuit 26 may be replaced with the logic control circuit 15 shown in FIG.

In the reproducing system in the optical disc apparatus using the maximum likelihood decoder 14 as described above, as shown in FIGS. It is converted into a binarized signal by using the PLL circuit 9 (9a, 9b), and the binarized signal is used as a synchronizing signal to generate a clock signal.

Since the reproduction signal has a band up to direct current (DC) as described above, if the frequency characteristic of the actual circuit that constitutes the reproduction system extends to direct current (DC), that circuit The generated signal is, as shown in FIG.
Correctly distributed to the ground level GND. In this case, if slice detection is performed at the ground level, an accurate binarized signal as shown in FIG. 36B is obtained, and the clock signal generated based on the binarized signal is also reproduced. Synchronize with the signal. However, in the actual circuit of the reproducing system, as described above, since the frequency characteristic is obtained by cutting the low frequency band such as direct current (DC), in the reproducing system circuit, as shown in FIG. Unlike a sine wave, a reproduced signal whose on-time and off-time are not equal is level-shifted in the positive or negative direction. When such a reproduced signal is converted into a binarized signal with the ground level GND as a slice level, a binarized signal accurately synchronized with the reproduced signal cannot be obtained as shown in FIG. 37 (b). As described above, the reproduction signal level shifts due to the difference in the recording patterns, so that the envelope of the reproduction signal changes as described above. Further, as described above, the envelope of the generated signal also fluctuates due to uneven birefringence on the substrate (polycarbonate or the like) of the optical disc. Therefore, the slice level required to obtain the binarized signal must change in accordance with the change in the envelope of the reproduction signal.

However, as shown in FIG. 38, while the reproduction signal envelope variation due to the difference in the recording pattern is relatively gentle, the reproduction signal envelope variation due to the birefringence unevenness of the optical disk substrate does not. It is relatively sharp. Therefore, if slice level detection is performed so as to follow the envelope fluctuation of the reproduction signal due to the difference in the recording pattern (for example, integral slice detection),
As shown in FIG. 38, it is impossible to detect the slice level that follows the envelope fluctuation of the reproduction signal due to the uneven birefringence of the optical disc substrate. On the other hand, if an attempt is made to detect the slice level so as to follow the envelope variation of the reproduced signal caused by the uneven birefringence of the optical disk substrate (for example, integral slice detection), as shown in FIG. 39, the gentle envelope variation of the reproduced signal will occur. Even in this case, the detected slice level will follow even small variations in the reproduced signal. In this case, a stable slice level cannot be obtained.

Therefore, the next embodiment aims at extracting from the reproduced signal a stable binarized signal used as a synchronizing signal in the PLL circuit even if the reproduced signal gradually or abruptly changes in envelope. There is.

FIG. 40 is a block diagram showing a reproducing system of the magneto-optical disk device according to this embodiment.

In FIG. 40, the reproduction system is the same as that shown in FIG. Device 13, maximum likelihood decoder 14
And a binarization circuit 17. The reproduction system further has a D / A converter 18. Maximum likelihood decoder 14
Is the same as in the above-described embodiment.
1, central value calculation unit 142, reference value calculation unit 1
43 and a merge detection unit 144. Each unit 141, 142, 143, 14 of the maximum likelihood decoder 14
Reference numeral 5 operates in synchronization with the clock signal from the PLL circuit 9. The center value calculation unit 142 calculates the center value C _kd of the reproduction signal level. The central value data C _kd is obtained as a digital value in the central value calculation unit 142, and this central value data C _kd is converted into an analog signal level by the D / A converter 18. The signal level output from the D / A converter 18 always represents the center value of the reproduced signal, and this signal (called center value signal) is supplied to the binarization circuit 17 as a signal representing the slice level. The binarization circuit 17 uses the center value signal level from the D / A converter 18 as a slice level to generate a binarized signal.

The binarized signal from the binarization circuit 17 is a PLL.
The signal is supplied to the circuit 9, and the PLL circuit 9 generates a clock signal for synchronization based on the binarized signal. And P
In synchronization with the clock signal generated by the LL circuit 9, A
/ D converter 13, maximum likelihood decoder 14 and D / A converter 18
Works.

As described above, the central value data C calculated by the central value calculation unit 142 in the maximum likelihood decoder 14 is used.
_Since the center value signal level corresponding to _kd is set as the slice level of the reproduced signal, the slice level is maintained at the center level of the reproduced signal, as shown in FIG. 41, even if the envelope of the reproduced signal changes gently or abruptly. However, it changes following the envelope change. The reproduced signal is binarized by this slice level, and the PLL circuit 9 generates a clock signal based on the binarized signal. Therefore,
The PLL circuit 9 can generate a clock signal that is stably synchronized with the reproduction signal, and the maximum likelihood decoder 14 can perform stable synchronization processing.

By the way, as described above, the PLL circuit 9
The clock signal generated by using is synchronized with the rising point (front edge point) and the falling point (rear edge point) of the reproduction signal. However, when data is reproduced from an optical disc on which data is recorded at a higher density,
Due to the delay in the circuit that generates the clock signal from the reproduction signal (binarization circuit 17, PLL circuit 9, etc.), in the A / D converter 13, the front edge point and the rear edge point of the reproduction signal are in phase with the clock signal. It will shift slightly. Thus, A
If the clock signal is out of phase with the front edge point or the rear edge point of the reproduction signal in the / D converter 13, the reproduction signal is not A / D converted at an appropriate phase, and accurate data reproduction cannot be guaranteed. Therefore, in the following embodiments, the above-mentioned problems are improved by compensating for the phase shift between the clock signal and the front edge point or the rear edge point of the reproduction signal supplied to the A / D converter 13. It is a thing.

The reproducing system according to this embodiment is shown in FIG.
It is configured as shown in. In FIG. 42, the reproducing system is similar to the embodiment shown in FIG. 40. Bowl 1
4, a binarization circuit 17 and a D / A converter 18. The reproducing system further includes a PLL circuit 30 and a D / A converter 35, which have a new structure.

The maximum likelihood decoder 14 is, for example, as shown in FIG.
Is configured. In FIG. 43, the maximum likelihood decoder 1
4 is a merge determination unit 1 as in the above-described embodiment.
41, center value calculation unit 142, reference value calculation unit
143 and a merge detection unit 144. So
In addition, the maximum likelihood decoder 14 further includes a phase error detection unit.
145. This phase error detection unit 1
45 is the central value from the central value calculation unit 142
C_kave, Sampling data y in the A / D converter 13 _k 
And the leading edge data d from the merge detection unit 144
ef_k And rear edge data der_k Based on the phase error data
DT_k Is calculated. This phase error data dT_k Is calculated as
This is done according to the procedure shown in FIG. That is, the clock
With iming k, the merge detection unit 144 receives a new
Data def_k ("1" or "0") and trailing edge data der
_k Each time ("1" or "0") is output (S1), the leading edge position
Phase error data dTf_k But at the previous clock timing k-1
Center value C obtained by_k-1aveAnd sampling data y
_k-1 And front edge data def_k , According to the following formula
Calculated, dTf_k = (C_k-1ave -Y_k-1 ) ・ Def_k Also, the trailing edge phase error data dTr_k But the previous clock
Center value C obtained at timing k-1_k-1aveAnd sump
Ring data yk-1 and trailing edge data der_k Using,
It is calculated according to the following equation (S2).

DTr_k = (Y_k-1 -C_k-1ave) ・ Der_k Front edge data def_k Is the front edge point (
Rising) is only "1", so the leading edge phase error data
DTf_k Is the center value of the playback signal at the front edge and
It corresponds to the difference with the ring data. Also same
, The trailing edge phase error data dTr_k At the trailing edge point
It corresponds to the difference between the center value of the playback signal and the sampling data.
It Then, the phase error data dT_k Is the front edge phase
Error data dTf_k And trailing edge phase error data dTr_k With
The sum is obtained (S3). Obtained phase error data
dT_k Is supplied to the D / A converter 35 (S4).

Front edge data def _k and rear edge data
der _k should ideally be obtained at clock timings corresponding to the front edge point and the rear edge point of the reproduction signal. That is, the phase error data dT _k is used for the front edge point and the rear edge point of the reproduction signal and the synchronization clock signal (A /
The phase error with the D converter 13 and the maximum likelihood decoder 14) is quantitatively expressed.

Phase error data according to the procedure described above.
The phase error detection unit 145 that calculates dT _k is configured as shown in FIG. 45, for example.

In FIG. 45, this phase error detection unit is
The switch 145 includes a first shift register 1451 and a second shift register 1451.
Shift register 1452, constant setter 1453, first decrement
Calculator 1454, second subtractor 1455 and selector 14
It is equipped with 56. In the first shift register 1451
Center value C from center value calculation unit 142_kaveIs next
It is held until the lock timing. Second shift register
The sampling value y in the A / D converter 13 is stored in the data 1452.
_k Are held until the next clock timing. First decrease
The calculator 1454 is the inside of the first shift register 1451.
Heart value C_k-1aveFrom the second shift register 1452
Sampling value y_k-1 Subtract. Corresponds to the front edge point
This first subtractor 1454 at the clock timing
The value output from is calculated as shown in S2 of FIG.
Leading edge phase error data dTf_k Becomes (front edge
Data def_k Is "1"). The second subtractor 1455 is
Sampling value y from shift register 1452_k-1 Or
Center value C from the first shift register 1451_k-1ave
Subtract. Clock timing corresponding to the rear edge point
The value output from this second subtractor 1455 is
After the edge phase error calculated as shown in S2 of 44,
Difference data dTr_k Becomes (rear edge data der _k Is "1")
 . For example, the constant “0” is previously stored in the constant setter 1453.
It is set. Selector 1456 has three input terminals
It has A, B, and C. Set in the constant setter 1453
The constant value "0" is input to the input terminal A, and the first subtractor 1454
From the second subtractor 1455 to the input terminal B
Values are supplied to the input terminals C, respectively. Selector 145
6 is the input terminal from three input terminals A, B, C according to the following table.
Data def_k And rear edge data der_k Corresponding to
Select the output terminal.

[0106]

[Table 3] That is, at the clock timing corresponding to the front edge point of the reproduction signal (def _k = "1", der _k = "0"), the front edge phase error data (C _k-1ave −y _{k- 1} )
Is output from the selector 1456, and at the clock timing corresponding to the trailing edge point of the reproduction signal, (def _k = "0", d
er _k = “1”), the trailing edge phase error data (y _k-1 −C _k-1ave ) input to the input terminal C is output from the selector 1456. Also, at clock timings corresponding to points other than the leading edge point and the trailing edge point of the reproduced signal, (def _k =
"0", der _k = "0"), constant value input to input terminal A "0"
Is output from the selector 1456. Both front edge data def _k and rear edge data der _k are "1" at the same time.
Although such a situation is theoretically impossible, if such a state occurs due to a malfunction of the circuit or the like, the selector 1456 outputs the constant value "0" input to the input terminal A.

As described above, the phase error of the maximum likelihood decoder 14 is
From the difference detection unit 145, the front edge point and the rear edge point
Phase error data dT for each clock timing corresponding to_k 
Is output. This phase error data dT_k Is a D / A converter
35, and from this D / A converter 35,
For example, as shown in FIGS. 46 and 47, the phase error data dT
_k A square wave signal (phase error signal) with an amplitude corresponding to
Be done. Fig. 46 shows the actual clock signal phase (marked with ●)
Ideal sample points of reproduced signal (marked with ○) (front edge point and
And the trailing edge point are included) the phase error dτ is positive (+)
Is shown. In this case, the front edge point and the rear
Phase error data dT for each timing corresponding to the edge point_k 
The phase error signal that has a positive (+) amplitude value corresponding to
It is output from the A converter 13. Also, FIG. 47 shows the actual
The phase of the clock signal (marked with ●) and the ideal sampling of the reproduced signal
The phase error dτ between the pull point (marked with ○) is negative (-).
The case is shown. In this case, the leading edge point and the trailing edge
Phase error data dT for each timing corresponding to the point_k Corresponding to
The phase error signal with negative (-) amplitude value is D / A converted.
It is output from the device 35.

The PLL circuit 30 shown in FIG. 42 is constructed, for example, as shown in FIG. In FIG. 48, the PLL circuit 30 includes a phase comparator 31, low pass filters (LPF) 32-1 and 32-2, and a voltage controlled oscillator (VCO) 33. From the binarization circuit 17,
An edge detection signal (corresponding to the front edge and the rear edge of the reproduced signal) corresponding to the rising and falling of the binarized signal obtained by binarizing the reproduced signal with the center value as the slice level is output. The phase comparator 31 compares the phases of the clock signal output from the PLL circuit 30 and the edge detection signal (input 1) from the binarization circuit 17, and outputs a signal according to the phase difference. The signal from the phase comparator 31 is converted into a voltage level corresponding to the phase difference by the low pass filter 32-1. Further, the phase error signal from the D / A converter 35 described above is a low-pass filter 32-
At 2, it is converted to a voltage level corresponding to the phase error signal. When the phase error described above is positive (+), the voltage level output from the low pass filter 32-2 is
When the phase error is positive (+) as shown in FIG. 46 and the phase error is negative (-), the output voltage level from the low pass filter 32-2 becomes negative (-) as shown in FIG. . The voltage levels output from the low pass filters 32-1 and 32-2 are added and supplied to the voltage controlled oscillator 33. The voltage controlled oscillator 33 controls, for example, the phase of a clock signal having the same frequency as the reference clock signal used for data recording according to the input voltage level, and outputs this phase-adjusted clock signal. The clock signal from the voltage controlled oscillator 33 is used as the output clock signal of the PLL circuit 30 for the A / D converter 13 and the maximum likelihood decoder 1.
4 is supplied. Since the PLL circuit 30 operates in a state in which the phase difference signal is offset by the phase error, the phase of the clock signal output from the PLL circuit 30 is locked so that the phase error is canceled. That is, the phase of the synchronization clock signal supplied to the A / D converter 13 and the maximum likelihood decoder 14 is the same as that of the A / D converter 13
It converges to the ideal sampling point of the reproduced signal input to.

Further, as shown in FIG. 49, the voltage supplied to the voltage controlled oscillator 33 is initially set to the rotor pass filter 3
Even if the PLL is pulled in by the voltage of 2-1 and the phase error signal is switched to the voltage obtained through the low-pass filter 32-2 by the changeover switch 100 later, the phase error is canceled in the same manner. Locks and converges on the ideal sample point.

The operations of the A / D converter 13 and the maximum likelihood decoder 14 synchronized with this clock signal are similar to those of the embodiment shown in FIG. For example, as shown in FIG. 50, at every clock timing (k = 4, 9, ...
Phase error data calculated in _{·) (C 3 -y 3,} C 8 -
y ₈ · · ·) and the trailing edge clock timing each corresponding to the point (k = 7, 13, the phase error data is computed to _{···) (y 6 -C 6,} y 12 -C 12 ···) The reproduced signal is sampled in synchronism with the clock signal whose phase is adjusted based on, and the central value C _k , the judgment value M _k , and the variable A _k are calculated based on the sampled value. The leading edge data def _{k and the} trailing edge data der _k obtained based on the judgment value M _k and the variable A _k are output from the maximum likelihood decoder 14 in synchronization with the phase-adjusted clock signal. The decoder 10 decodes the data string in which the edge data def _k and the trailing edge data der _k are alternately arranged.

In FIG. 51, as in the embodiment shown in FIGS. 27 to 32, the leading edge synchronizing clock signal synchronized with the rising edge of the reproduced signal and the trailing edge synchronizing clock signal synchronized with the falling edge of the reproduced signal are used to detect the leading edge. 7 shows an embodiment of a reproducing system in which data and trailing edge data are independently calculated, and in this reproducing system, the front edge synchronizing clock signal and the trailing edge synchronizing clock signal whose phases have been adjusted as described above are respectively generated. can get.

In FIG. 51, this reproducing system comprises an optical disc 1, an optical head 2, an amplifier 6, an equalizer 7a, a low pass filter 7b, a D / A converter 18 and a binarization circuit 1.
Have 7. Further, as a system related to the front edge synchronization clock signal, a first A / D converter 13-1, a first maximum likelihood decoder 14-1, a first PLL circuit 30-1 and a first D / A. The converter 35-1 is provided, and the second A / D converter 13-2 is provided as a system related to the rear edge synchronization clock signal.
Second maximum likelihood decoder 14-2, second PLL circuit 30-2
And a second D / A converter 35-2. First maximum likelihood decoder 14-1 and second maximum likelihood decoder 14-2
The basic configuration of is similar to that shown in FIG. 43, and the merge detection unit 144 is particularly similar to that shown in FIG. Then, only the leading edge data def _k is output from the merge detection unit 144 in the first maximum likelihood decoder 14-1, and only the trailing edge data der _k is output from the second maximum likelihood decoder 14-2. It The phase error detection unit 145 in the first maximum likelihood decoder 14-1 is configured in the same manner as in FIG. 45, and its selector 1456 has three input terminals A, B and C according to the following table, leading edge data def _k and trailing edge data. Select the input terminal corresponding to the data der _k .

[0113]

[Table 4] That is, only at the clock timing corresponding to the front edge point of the reproduction signal (def _k = “1”, der _k = “0”), the front edge phase error data (C _k-1ave − y) input to the input terminal B is input.
_k−1 ) is output from the selector 1456, and at other timings, the constant value “0” which is always input to the input terminal A is output from the selector 1456.

Center value C from the first maximum likelihood decoder 14-1
_k is converted into a signal level by the D / A converter 18, and the binarization circuit 17 generates a binarized signal by using this signal level as a slice level, and corresponds to the rising edge of the generated binarized signal. The binarization circuit 17 outputs an edge detection signal and a post-edge detection signal corresponding to the trailing edge of the binarized signal. Then, the leading edge phase error data dTf _k from the first maximum likelihood decoder 14-1 is converted into the first D / A converter 35.
The phase error signal is converted into a phase error signal at -1, and the leading edge detection signal and the phase error signal are supplied to the first PLL circuit 30-1 configured as shown in FIG. Based on the phase error signal and the leading edge detection signal, the first PLL circuit 30-1 adjusts the phase of the clock signal internally generated so that the phase error at the leading edge point is eliminated, as described above. And the phase-adjusted clock signal is output from the first PLL circuit 30-1 as a front edge synchronization clock signal.

The phase error detection unit 145 in the second maximum likelihood decoder 14-2 is constructed in the same manner as in FIG. 45, and its selector 1456 has three input terminals A, B and C.
From, select the input terminals corresponding to the front edge data def _k and the rear edge data der _k according to the following table.

[0116]

[Table 5] That is, only at the clock timing corresponding to the trailing edge point of the reproduced signal (def _k = "0", der _k = "1"), the trailing edge phase error data (y _k-1 -C) input to the input terminal C is input.
_k-1ave ) is output from the selector 1456, and at other timings, the constant value "0" input to the input terminal A is output from the selector 1456. Based on the trailing edge detection signal output from the binarization circuit 17 and the trailing edge phase error data from the second maximum likelihood decoder 14-2, the second PLL circuit 30-2 and the second D / A The phase of the clock signal is adjusted in the system including the converter 35-2. As a result, the second PL
The L circuit 30-2 outputs a rear edge synchronization clock signal whose phase is adjusted so that there is no phase error at the rear edge point.

The first and second maximum likelihood decoders 14-1 and 14-1 and 14 are synchronized with the leading edge synchronizing clock signal and the trailing edge synchronizing clock signal whose phases have been adjusted as described above.
-2, the leading edge data def _k and the trailing edge data der _k are combined by a combining circuit 36 such as an OR circuit. Then, the combined data from the combining circuit 36 is the decoder 1
Decoded by 0.

FIG. 52 shows an embodiment of a reproducing system in which the synchronous clock signal is generated without using the binarized signal generated from the reproduced signal. In FIG. 52, this reproducing system has an optical disc 1, an optical head 2, an amplifier 6, an equalizer 7a, a low-pass filter 7b, an A / D converter 13, a maximum likelihood decoder 14, and a decoder 10. This reproduction system further includes a D / A converter 35, a low pass filter 32, and a voltage controlled oscillator 33 (VCO). Maximum likelihood decoder 1
Reference numeral 4 is configured as shown in FIG. 43, and outputs phase error data as in the above-mentioned embodiment. And the maximum likelihood decoder 1
The phase error data from 4 is converted into a phase error signal (rectangular wave signal) by the D / A converter 35. The phase error signal is converted into a voltage level by the low pass filter 32, and the voltage controlled oscillator 33 controls the phase of the output clock signal according to the voltage level. The voltage controlled oscillator 33 generates the same clock signal as the data recording synchronization signal as a reference clock signal, and the phase of the reference clock signal is adjusted according to the voltage level corresponding to the phase error data. Then, the clock signal from the voltage adjustment oscillator 33 is supplied to the A / D converter 13 and the maximum likelihood decoder 14, and the A / D converter 13 and the maximum likelihood decoder 14 operate in synchronization with this clock signal.

In the reproduction system having the configuration shown in FIG. 52, the phase error detection unit 145 of the maximum likelihood decoder 14 and the D / A converter 3
5, the low pass filter 32 and the voltage controlled oscillator 33 constitute a so-called PLL circuit. When the phase of the reproduction signal does not change significantly, a clock signal that is correctly synchronized with the reproduction signal can be obtained even in the reproduction system having such a simple structure.

FIG. 53 shows an embodiment in which the phase adjusting method shown in FIG. 52 is applied to a reproducing system for independently detecting the leading edge data and the trailing edge data. In FIG. 53, the reproducing system includes an optical disc 1, an optical head 2, an amplifier 6, an equalizer 7a and a low pass filter 7b. Further, this reproduction system is a system related to the front edge synchronization clock signal, and includes a first A / D converter 13-1 and a first maximum likelihood decoder 1.
4-1, a first D / A converter 35-1, a first low pass filter 32-1 and a first voltage controlled oscillator 33-1 are provided, and as a system related to the rear edge synchronization clock signal, Second A / D converter 13-2, second maximum likelihood decoder 1
It has 4-2, the 2nd D / A converter 35-2, the 2nd low pass filter 32-2, and the 2nd voltage control oscillator 33-2. First and second maximum likelihood decoders 14-1, 14
-2 is configured similarly to the embodiment shown in FIG. The system related to the front edge synchronization clock signal and the system related to the rear edge synchronization clock signal are the A / D converter 13, the maximum likelihood decoder 14, the D / A converter 35, the low-pass filter 32, and the voltage shown in FIG. It is configured similarly to the controlled oscillator 33. Second maximum likelihood decoding in synchronization with the front edge data output from the first maximum likelihood decoder 14-1 and the phase adjusted rear edge synchronization clock signal in synchronization with the phase adjusted front edge synchronization clock signal. The trailing edge data output from the device 14-2 is combined by the combining circuit 36. The synthesizing circuit 36 is, for example, a FIFO (First-In, First-
Out) configured by using a memory, and the front edge data is synchronized with the front edge synchronization clock signal, and the rear edge data is synchronized with the rear edge synchronization clock signal.
Stored in O. The stored leading edge data and trailing edge data are alternately FI synchronized with either the leading edge synchronizing clock signal or the trailing edge synchronizing clock signal.
It is read from the FO and the data strings are combined. The combined data string is decoded by the decoder 10.

FIG. 54 also shows an embodiment of a reproducing system having a system related to the leading edge synchronization clock signal and a system related to the trailing edge synchronization clock signal. In each system, the slice level for generating the binarized signal from the reproduced signal is corrected so that the phase error is canceled. As a result, the front edge synchronization clock signal and the rear edge synchronization clock signal are correctly synchronized with the front edge point and the rear edge point of the reproduction signal, respectively.

In FIG. 54, the reproducing system comprises an optical disc 1, an optical head 2, an amplifier 6, an equalizer 7a and a low pass filter 7b. This reproduction system further includes a first A / D as a system related to the front edge synchronization clock signal.
Converter 13-1, first maximum likelihood decoder 14-1, first center value D / A converter 18-1, first binarization circuit 17-
1, the first phase error D / A converter 35-1 and the first P
The second A / D converter 13-2, the second maximum likelihood decoder 14-2, and the second center value D / A are provided as a system having the LL circuit 9-1 and related to the rear edge synchronization clock signal. Converter 18-2,
It has a second binarization circuit 17-2, a second phase error D / A converter 35-2, and a second PLL circuit 9-2.

In the system related to the front edge synchronization clock signal
The first A / D converter 13-1, the first maximum likelihood decoder 1
4-1 and the first phase error D / A converter 35-1 are shown in FIG.
51 and a first phase error D /
A leading edge phase error signal is output from the A converter 35-1
It Also, the central value C from the first maximum likelihood decoder 14-1 _k 
To the voltage level at the first center value D / A converter 18-1
Converted to this voltage level the first phase error D / A conversion
The level of the leading edge phase error signal from the device 35-1 is added
To be done. Then, the added voltage level is the slice level
Is supplied to the first binarization circuit 17-1. That is,
This slice level is from the center value of the reproduced signal to the front edge.
It should be offset by a level corresponding to the phase error.
It Then, the first binarization circuit 17-1 is supplied with
Generate a binarized signal based on the rice level
Outputs the leading edge detection signal corresponding to the rising edge of the digitized signal
To do. The first PLL circuit 9-1 is the first binarization circuit 17
-1 to synchronize with the leading edge detection signal from -1.
Adjust the phase of the lock signal. First PLL circuit 9-1
The phase-adjusted clock signal output from the
The first A / D converter 13-
1 and the first maximum likelihood decoder 14-1.

As shown in FIGS. 46 and 47, the leading edge data is ideally obtained when the reproduced signal has the center value (corresponding to the no merge state). Here, when the sampling value y _k deviates from the center value C _k at the front edge point of the reproduction signal, the center value is corrected (offset) so that the front edge phase error represented by the deviation amount is canceled,
A binarized signal is generated with the corrected center value as a slice level. The leading edge synchronization clock signal obtained based on the leading edge detection signal corresponding to the rising edge of the binarized signal is accurately synchronized with the leading edge point of the reproduction signal.

Also in the system related to the rear edge synchronization clock signal, the second A / D converter 13-2, the second maximum likelihood decoder 14-2, and the second phase error D / A converter 35-2. Is
The configuration is similar to that shown in FIG. Further, a second center value D / A converter 18-1 and a second binarization circuit 17-
The second and second PLL circuits 9-2 are configured to correspond to those of the system related to the front edge synchronization clock signal. In this case, the voltage level corresponding to the center value of the reproduction signal is corrected by the level corresponding to the trailing edge phase error, and the slice level is used as the second binarization circuit 17-.
2 generates a binarized signal from the reproduced signal. Then, the phase of the internal clock signal of the second PLL circuit 9-2 is adjusted so as to be synchronized with the post-edge detection signal corresponding to the fall of the binarized signal, and the phase-adjusted clock signal is output later. The edge synchronization clock signal is supplied from the second PLL circuit 9-2 to the second A / D converter 13-2 and the second maximum likelihood decoder 14-2. Also in the system related to the trailing edge synchronization clock signal, if the sampling value y _k deviates from the center value C _k at the trailing edge point of the reproduction signal, the trailing edge phase error represented by the deviation amount is canceled. The center value is corrected (offset), and the binarized signal is generated with the corrected center value as the slice level. The trailing edge synchronization clock signal obtained based on the trailing edge detection signal corresponding to the trailing edge of the binarized signal is accurately synchronized with the trailing edge point of the reproduced signal.

FIG. 55 shows an embodiment of the reproducing system in which the phase adjustment element is used to adjust the phase of the clock signal. In FIG. 55, this reproducing system is similar to that shown in FIG. 40, and includes an optical disc 1, an optical head 2, an amplifier 6, an equalizer 7a, a low-pass filter 7b, and an A / D converter 1.
3, maximum likelihood decoder 14, D / A converter 18, binarization circuit 1
7, a PLL circuit 9 and a decoder 10. The maximum likelihood decoder 14 is configured to include a phase error detection unit 145, as shown in FIG. The reproducing system further has a phase adjusting element 40. This phase adjustment element 40
Adjusts the phase of the clock signal from the PLL circuit 9 based on the phase error data from the phase error detection unit 145 of the maximum likelihood decoder 14 so as to cancel the phase error. The phase adjusting element 40 is composed of, for example, a delay amount variable type delay circuit in which the connection of a plurality of delay lines is switched according to a phase error signal.

According to such a reproducing system, the PLL circuit 9
Since the phase of the clock signal output from is adjusted by the phase adjusting element 40 so that the phase error is canceled, the phase of the clock signal can be brought close to the ideal sampling point of the reproduction signal.

The phase error data from the phase error detection unit 145 of the maximum likelihood decoder 14 is converted into an analog phase error signal by the D / A converter, and the phase of the clock signal is converted based on this phase error signal. It is also possible to configure the phase adjustment element 40 so as to adjust

FIG. 56 shows an embodiment in which the phase adjusting method shown in FIG. 55 is applied to a reproducing system for independently detecting the leading edge data and the trailing edge data. In FIG. 56, the reproducing system includes an optical disc 1, an optical head 2, an amplifier 6, an equalizer 7a, a low pass filter 7b, and a decoder 10. The reproduction system further includes a first A / D converter 13-1, a first maximum likelihood decoder 14-1, and a first D / A converter 18-as a system related to the front edge synchronization clock signal. 1, a first binarization circuit 17-1, a first PLL circuit 9-1 and a first phase adjusting element 40-1, and a second A / D as a system related to the rear edge synchronization clock signal. Converter 13-
2, second maximum likelihood decoder 14-2, second D / A converter 1
8-2, the 2nd binarization circuit 17-2, the 2nd PLL circuit 9-2, and the 2nd phase adjustment element 40-2.

The phase error detection unit 145 of the first maximum likelihood decoder 14-1 outputs the leading edge phase error data, and the first binarization circuit 17-1 outputs the leading edge detection signal. The phase of the clock signal synchronized with the leading edge detection signal output from the first PLL circuit 9-1 is adjusted by the first phase adjusting element 40-1 according to the leading edge phase error data. The clock signal whose phase has been adjusted by the first phase adjusting element 40-1 is supplied to the first A / D converter 13-1 and the first maximum likelihood decoder 14-1 as a front edge synchronization clock signal. .

The phase error detection unit 145 of the second maximum likelihood decoder 141-2 outputs the trailing edge phase error data,
The second binarization circuit 17-2 outputs the trailing edge detection signal. The phase of the clock signal synchronized with the trailing edge detection signal output from the second PLL circuit 9-1 is adjusted by the second phase adjusting element 40-2 according to the trailing edge phase error data. The clock signal whose phase has been adjusted by the second phase adjusting element 40-2 is used as the rear edge synchronization clock as the second A / D converter 13-2 and the second maximum likelihood decoder 1.
4-2 is supplied.

Normally, in the optical disc 1 used as the recording medium of the above-mentioned magneto-optical disc device, information is recorded in the sectors arranged on the tracks. The recording format is, for example, as shown in FIG. In FIG. 59, each sector has a VFO area, a Sync area, and a data (DATA) area. In the VFO area, a densest continuous repetitive pattern modulated according to the partial response characteristic is recorded, and a PLL circuit is pulled in and locked with a pulse signal corresponding to this repetitive pattern to generate a synchronizing signal. Therefore, even if the optical disc 1 changes in rotation, a synchronization signal that follows the change can be obtained, and reliable data sampling can be performed using this synchronization signal. In the Sync area, a specific pattern indicating the start position of the data area is recorded. In the data (DATA) area, a signal obtained by modulating desired data according to the partial response characteristic as described above is recorded.

By the way, data of each sector (DATA)
In the area, the maximum likelihood data detection described above is performed,
Various constant values used in the maximum likelihood data detection are
Since the data is not recorded in each sector at the same time, the optimum value varies depending on the change in the recording condition. Therefore,
In the next embodiment, various constant values used in maximum likelihood data detection are determined based on the reproduction signal (closest continuous repeating pattern) from the VFO area of each sector.

Further, when the information obtained by the maximum likelihood data detector (maximum likelihood decoder) is used to determine various constants used in the maximum likelihood data detection based on the reproduced signal from the VFO area, it is optimal. The initial value must be provided to the maximum likelihood data detector.

In the reproducing system of the magneto-optical disk device having the AC coupling circuit, a transient as shown in FIG. 57 occurs in the reproduced signal of the repetitive pattern starting from the head portion of the VFO area. That is, the reproduction signal input to the A / D converter 13 greatly changes at the beginning of the VFO area. In such a situation, as described above, in the maximum likelihood data detector 14 that performs maximum likelihood data detection using the central value C _kave of the reproduced signal, if a fixed initial value of the central value is used, a transient of the reproduced signal occurs. The follow-up accurate maximum likelihood data cannot be detected. Therefore, in the next embodiment, further, when various constant values used in the maximum likelihood data detection are obtained based on the reproduced signal from the VFO area of each sector, an accurate center value C that follows the fluctuation of the reproduced signal is obtained. The initial value of _kave is provided to the maximum likelihood data detector.

Further, in the above-mentioned reproduction system, the equalization (equalizer) 7a equalizes the waveform of the reproduction signal. This equalizer (equalizer) 7a is, for example, an analog transversal. It is composed of a type equalizer. However, if the optical disc 1 has, for example, MCAV (Modi
When high density data recording is performed by the fied-Constant Angular Velocity) method, the delay time in the equalizer inside and outside the optical disc 1 (depending on the radial position of the sector of the optical disc 1) Must be changed, and adjustment is difficult with an analog transversal equalizer. Even if the equalizer is simply digitized, it is difficult to finely variably set the equalization target value according to the position of the sector.
Therefore, in the next embodiment, an equalizer that can perform adaptive equalization while changing the characteristics according to the position of the sector is provided.

The maximum likelihood decoder 14 (maximum likelihood data detector) according to the present embodiment is constructed, for example, as shown in FIG.

In FIG. 58, the maximum likelihood decoder 14
Similar to the embodiment shown in FIG. 43, the merge determination unit 14
1, central value calculation unit 142, reference value calculation unit 1
43, a merge detection unit 144 and a phase error detection unit 145. Further, the maximum likelihood decoder 14 further includes an initial center value setting unit 146, a calculation unit 147, a comparison reference value setting unit 148, a timing setting unit 149 and a comparator 151, and replaces the analog equalizer 7a. It includes a digital transversal equalizer 150.

The maximum likelihood decoder 14 performs various processes in the VFO area of each sector according to the timing chart shown in FIG. That is, the maximum likelihood decoder 14 is in the reset state at the time when the power-on reset signal rises due to power-on or forced reset. When the MO read gate signal RDGT rises near the beginning of the VFO area, the timing setting unit 1
The clock counter in 49 becomes valid, and the initial center value setting unit 146 starts the process for calculating the initial value of the center value based on the reproduction signal from the VFO area. In this case, the sampled value y _k of the reproduced signal is transferred from the A / D converter 13 operating in synchronization with the clock signal CLK from the PLL circuit to the initial center value setting unit 146 via the transversal type equalizer 150. Provided. The constants in the transversal type equalizer 150 are set to default values. The center value obtained when the value of the clock counter in the timing setting unit 149 reaches j1 is latched in the initial center value setting unit 146 as an initial value.

The value of the clock counter reaches j1, the initial value of the center value is latched in the setting unit 146, and P
Gate signal I indicating that the LL circuit is locked
When NITGT rises, the clock counter value i
Is reset to "0", and calculation of various constants used in the maximum likelihood decoder 14 is started. In this embodiment, comparison reference values Δ1 and Δ2, which will be described later, and target values for adaptive equalization used in the transversal type equalizer 150 are calculated. The comparison reference values Δ1 and Δ2 are the comparison reference setting unit 1
48, and the target value for adaptive equalization is calculated in the arithmetic unit 147. Then, when the value of the clock counter reaches j2, the comparison reference values Δ1 and Δ2
Is latched in the comparison reference value setting unit 148, and the target value for adaptation is calculated from the arithmetic unit 147 to the comparator 1
51 and latched in the comparator 151.

The comparison reference values Δ1 and Δ2 are the following values.

Merge decision unit 14 of maximum likelihood decoder 14
In No. 1, as described above, the merge state (transition state of data) corresponding to each sampling value is determined according to the procedure shown in FIG. In this case, + merge (M _k
= 01), -merge (M _k = 10) and no merge (M _k =)
It becomes the judgment standard of 00)

[0143]

[Equation 11] Shows the positive peak value of the reproduction signal as shown in FIG.
It is an optimum value when 2 "and a negative peak value are assumed to be" -2 ". The constants" 1 "and" -1 "are shown in FIG.
It is also used in the processing in the reference value calculation unit 143 shown in (Δ _{k + 1} = 2C _kave −y _k −1, Δ _{k + 1} =
2C _kave −y _k +1). The constant used for determining the merged state is generally defined as the comparison reference value Δ1. The absolute value of the constant (1, -1) is a quarter value of the ideal reproduction signal amplitude value "4 (= 2-(-2))". Therefore, the comparison reference value Δ1 is also set to be a quarter of the amplitude value of the reproduction signal.

The central value calculation unit 142 of the maximum likelihood decoder 14 calculates the central value data C _kd according to the procedure shown in FIG. 18, as described above. In this case, it serves as a criterion for selecting an arithmetic expression for _obtaining the central value data C _kd.

[0145]

[Equation 12] Is also the optimum value when the positive peak value of the reproduction signal is assumed to be "2" and the negative peak value is assumed to be "-2". Generally, the constant used as the judgment standard is the comparison standard value Δ
Defined as 2. The absolute value of this constant (2, -2) is a half value of the ideal reproduction signal amplitude value "4". Therefore, the comparison reference value Δ2 is also set to a half of the amplitude value of the reproduction signal.

Central value C _kave to be used for maximum likelihood data detection
The principle of the operation for obtaining the initial value of is shown in FIG.
That is, when the difference between the maximum value y _max and the minimum value y _min of the sampling values becomes equal to or more than the predetermined value y _com , it is determined that the reproduction signal corresponding to the repetitive pattern of the VFO area has risen, and then j1 Calculate the average value of the sampling values. This average value is set as the initial value of the center value. Here, the number of sampling rings j1 is an integral multiple of the number of sampling rings for one cycle of the reproduction signal. in this way,
By setting the number j of sampling rings to an integral multiple of the number of sampling rings for one cycle of the reproduction signal, even if the sampling operation is synchronized with the clock CLK from the PLL circuit that is not in phase synchronization, the average value of the sampling values is It is always the center value of the reproduced signal.

The initial center value setting unit 146, which calculates the initial value of the center value according to the above-mentioned principle, executes the processing in the procedure as shown in FIG. 62, for example.

When the sampling value y _k is input, it is determined whether or not the value is larger than the maximum value y _max obtained so far. If it is larger, the maximum value y _max is updated to that value ( y _max = y _k ). If the sampling value y _k is smaller than the minimum value y _min obtained so far, the minimum value y _min is updated to the sampling value y _k (y
_min = y _k ). Then, the maximum value y _max and the minimum value y _min
If any of is updated, the difference between the maximum value y _max and outermost small value _{y min yd (= y max -y} min) is calculated.
The maximum value y _max and the minimum value y _min are updated until the difference y _d becomes larger than the predetermined value y _com . Here, when the difference y _d between the maximum value y _max and the minimum value y _min exceeds the predetermined value y _com , it is determined that the reproduction signal corresponding to the repeating pattern in the VFO area has risen, and the central value is calculated. In the arithmetic processing of the central value, the count value i of the clock signal is initialized to "0", and thereafter, every time a new sampling value y _k is given, C _init =
C based on {(j1-1) · C _i-1init + y _k } / j1
_iinit is calculated. Then, the count value i is incremented (i = i + 1), and j1 sampling values (i
= J1) is reached, this operation is executed. The calculated value C _j1init when the count value i reaches j1 is the average value of j1 sampling values, that is, the center value of the reproduced signal sampled. Therefore, when the count value i reaches j1, the calculated value C _j1init obtained at that time is used as the initial value of the central value C _kave to set the initial central value setting unit 1
Latch in 46 (C _kave = C _j1init ).

As described above, when the initial value of the central value is latched by the initial central value setting unit 146, the initial value is given to the central value calculation unit 142, and the initial value of the central value is used to set the reference value. The calculation in the calculation unit 143 is performed (see FIG. 19), and thereafter, the central value calculation unit 142 sequentially updates the central value from this initial value based on the sampling value (see FIG. 18). In addition, after the initial value of the central value is determined, until the later-described comparison reference values Δ1 and Δ2 are determined, in the merge determination unit 141 and the reference value calculation unit 143, the comparison reference value Δ1 is a constant
1 ”is used. In the meantime, in the central value calculation unit 142, the constant“ 2 ”is used as the comparison reference value Δ2.

The comparison reference values Δ1 and Δ2 are calculated by the calculation unit 147 and the comparison reference value setting unit 148 as follows.

First, the principle of calculation for obtaining the amplitude value of the reproduction signal corresponding to the repeating pattern in the VFO area is shown in FIG.
3 is shown. When the PLL circuit is locked (the state where INITGT has risen), substantially positive and negative peak values of the reproduction signal are sampled in synchronization with the clock signal from this PLL circuit. When the positive peak value is sampled, the merge determination unit 1
41 outputs a + merge determination result (M _k = 01), and when a negative peak value is sampled,
The merge determination unit 141 determines the result of determination of -merge (M _k
= 10) is output. Therefore, the comparison reference value setting unit 148 calculates the average value of the sampling values y _p when the judgment result from the merge judgment unit 141 is + merge,
The determination result is the average value of the sampling values y _m when the -merge, is calculated and the amplitude value of the difference _{dy pm (= y p -y m} ) a reproduced signal.

The arithmetic unit 147 and the comparison reference value setting unit 148 execute the processing according to the procedure shown in FIG. First, in the arithmetic unit 147, after resetting the clock counter value i to “0”, the sampling value y
An operation for obtaining the average value of the positive peak values y _p of the sampling value and the negative peak value y of the sampling value based on the judgment result from the merge judgment unit 141 for _k .
Perform an operation to obtain the average value of _m . Then, the difference between the positive average value and the average value of negative peak values y _m of the peak values y _p d
Calculate y _pm . Then, the comparison reference value setting unit 14
8, the difference dy _pm in the quarter prompted a comparison reference value .DELTA.1, further, obtains a comparison reference value Δ2 and the difference dy _pm to one-half. The clock count value i is calculated by the arithmetic unit 147 and the comparison reference value setting unit 148.
The calculation unit 147 obtains the difference dy _pm at the time when the clock count value is j2 as the amplitude value of the final reproduced signal, and the comparison reference values Δ1 and Δ2 at that time. Is latched by the comparison reference value setting unit 148 as the final value.

The arithmetic unit 147 performs the arithmetic operation for obtaining the average value of the positive peak values y _p and the arithmetic operation for obtaining the average value of the negative peak values y _m according to the procedures shown in FIGS. 65 and 66, respectively. ing.

That is, from the merge determination unit 141 to + me
When the determination result of rge (Z _k > 1) is obtained, the variable y _kpd
Using the sampling value y _k as (y _kpd = y _k ), the average value y _kp of the positive peak values is calculated according to y _kp = {(i−1) · y _k-1p + y _kpd } / i ( Figure 6
5). In this case (+ merge), the new sampling value y _k is used to update the average value y _kp of the positive peak values. Further, when the determination result of the merge determination unit 141 is + merge, the variable y _{kmd is set} as the previous value (i = k-
Using the average value y _k-1m of the negative peak values obtained in the calculation of 1) (y _kmd = y _k-1m ), y _km = {(i−1) · y _k-1m + y _kmd } / The average value ykm of the negative peak values is calculated according to i (FIG. 6).
6). In this case (+ merge), the average value y _km of negative peak values of this time (i = k) becomes equal to the average value y _{k-1 m} of negative peak values of the previous time (i = k−1), and this sampling The value y _k is not used in the update operation of the average value of the substantially negative peak values.

From the merge determination unit 141 -merge
When the determination result of (Z _k <-1) is obtained, the average value y _k-1p of the positive peak values obtained by the previous calculation (i = k-1) is _used as the variable y _kpd (y _kpd = Y _k-1p ), the average value y _kp of the positive peak values is calculated according to the above equation (see FIG. 65). In this case (-merge), the average value y _kp of the positive peak values of this time (i = k) becomes equal to the average value y _k-1p of the positive peak values of the previous time (i = k−1), and Sampling value y
_k is not used for the update calculation of the average value of the substantially positive peak values. Also, the judgment result of the merge judgment unit is −
In the case of merge, the sampling value y _k is used as the variable y _kmd (y _kmd = y _k ), and the average value y _km of the negative peak values is calculated according to the above equation (see FIG. 66). In this case (-
merge), the average value y _km of the negative peak values is updated using the new sampling value y _k .

From merge judgment unit 141 no merge
When the determination result of (−1 <Z _k <1) is obtained, in each of the update calculation of the average value y _kp of the positive peak values and the update calculation of the average value y _km of the negative peak values, variables y _kpd , y
_{As kmd} , the average values y _k-1p and y _k-1m of the positive and negative peak values obtained by the previous calculation (i = k-1) are used (y
_{kp d} = y _k-1p , y _kmd = y _k-1m ), and the average values y _kp and y _{km of the} positive and negative peak values are calculated according to the above equation (FIG. 6).
5 and FIG. 66). In this case (no merge), this time (i
= K) the averages of the positive and negative peak values y _kp and y _km are equal to the previous (i = k-1) averages of the positive and negative peak values y _k-1p and y _k-1m , respectively. , The current sampling value y _k is not used for the update calculation of the average value of the positive and negative peak values.

As described above, when the comparison reference values Δ1 and Δ2 are latched at the time when the clock count value reaches j2, the comparison reference value Δ1 is set to the merge determination unit 14
1 and the reference value calculation unit 143. As a result, after that, the merge determination unit 141 and the reference value calculation unit 143 perform processing according to the procedure shown in FIG. 67 instead of the procedure shown in FIGS. 17 and 19, respectively. Also,
The comparison reference value Δ2 is given to the central value calculation unit 142, and thereafter, the central value calculation unit 142 performs the process according to the procedure shown in FIG. 68 instead of the procedure shown in FIG.

As described above, in the VFO region, the comparison reference values Δ1 and Δ2 are calculated after the initial value of the center value is obtained. In the calculation process for obtaining the comparison reference values Δ1 and Δ2, The signal dy _kpm (corresponding to the amplitude value of the repetitive pulse signal in the VFO region) between the average value y _kp of the positive peak values and the average value y _km of the negative peak values obtained at the time when the clock count value is j2 Equalization target value dy
It is latched in the comparator 151 as _lat .

The transversal type equalizer 150 includes delay elements 1501 and 15 as shown in FIG. 69, for example.
02, a multiplier 1503 that multiplies the sampling value via the two-stage delay elements 1501 and 1502 by an equalization coefficient (gain) k, and the sampling value from the A / D converter 13 directly equalizes the coefficient (gain) k. A multiplier 1504 that multiplies by
The sampling value via the one-stage delay element 1501, the inverted value of the output value of the multiplier 1053, and the multiplier 1504
Adder 15 for obtaining the equalized value by adding the inverted value of the output value of
05 and a gain controller 1510 for controlling the value of the gain k used in the multipliers 1503 and 1504. The gain controller 1510 controls the equalization coefficient (gain) k based on the gain control signal (k control signal) from the comparator 151.

In the VFO area, the gain k of the transversal equalizer 150 is controlled so as to be fixed to the default value. In the area after the VFO area of each sector, the equalization coefficient k of the transversal type equalizer 150 is the above-mentioned target value dy _lat and merge determination unit 1
It is controlled based on the determination result from 41.

That is, the arithmetic unit 147 makes an average value y _kp of the positive peak value of the signal based on the judgment result from the merge judgment unit 141 which performs the judgment calculation using the comparison reference value Δ1 determined as described above. Is calculated according to the procedure shown in FIG. 70 (corresponding to the procedure shown in FIG. 65), and the negative peak value y _km of the signal is calculated according to the procedure shown in FIG. 71 based on the determination result from the merge calculation unit 141 ( (This corresponds to the procedure shown in FIG. 66). The difference d between the average value y _kp of the positive peak values and the average value y _km of the negative peak values calculated in this way
y _pm is further calculated. This difference dy _pm is synchronized with the clock signal and the comparator 15 in which the equalization target value dy _lat is latched
1 is provided.

The gain controller 1510 of the comparator 151 and the transversal type equalizer 150 performs processing according to the procedure shown in FIG.

First, the arithmetic unit 147 to the comparator 15
Every time the difference dy _pm between the average value y _kp of the positive peak value and the average value y _km of the negative peak value is given to 1, the difference between the difference dy _pm and the equalization target value dy _lat is detected by the comparator 151. , That is, the amplitude difference d
y _diff is calculated, and the calculated amplitude difference dy _diff is given to the gain controller 1510 of the transversal equalizer 150 as a gain control signal. next,
The gain controller 1510 uses the predetermined equalization coefficient ko as a reference value to calculate the equalization coefficient k as k = ko + dy _diff /
m, and the equalization coefficient (gain) used in the multipliers 1503 and 1504 is controlled to be the determined equalization coefficient value k. Here, m is the amplitude difference dy
It is a constant for adjusting _diff to the size of the equalization coefficient to be corrected. Each of the multipliers 1503 and 1504 multiplies the sampling value from the A / D converter 13 by the equalization coefficient controlled as described above, and supplies the result to the adder 1505.

If the equalization coefficient of the transversal equalizer 150 is controlled as described above, when the signal amplitude value dy _pm fluctuates and deviates from the equalization target value dy _lat , the deviation dy _diff is calculated according to the above equation. The equalization coefficient k is controlled so as to correct. Therefore, a stable equalized output can be obtained.

Also, the equalization target value is the VF of each sector.
In the O region, it can be easily determined based on the amplitude value dy _pm of the reproduction signal. That is, in the equalizer,
The equalization target value can be easily variably set according to the sector position.

Furthermore, since the equalizer obtains an equalized output by digital processing, it is difficult to change the delay time depending on the inner circumference and outer circumference of the optical disc 1 which has been difficult in analog equalization. It is easily achieved by changing.

Each of the multipliers 1503 and 1504 of the transversal type equalizer 150 can be realized by an ordinary circuit that performs multiplication of two numbers, but as shown in FIG. It is also possible to configure so that multiplication of can be performed simply and at high speed.

In FIG. 73, this multiplier is the data X (t) (7 bits) from the A / D converter 13 or the data X (t-2 through the delay elements 1501 and 1052.
τ) (7 bits) are sequentially shifted by 1 bit and stored therein. Registers Rg1, Rg2, Rg3, Rg4, Rg5
Rg6 and Rg7 and selectors Sel1 and Sel2
And an adder ADD. The input data is set in the register Rg1 as it is, and the input data is shifted by 1 bit in the register Rg2 to obtain 1/2 of the input data.
Is set, the register Rg3 is set to 1/4 of the input data obtained by shifting the input data by 2 bits, and the register Rg4 is set to 1/8 of the input data obtained by shifting the input data by 3 bits. Is set, register Rg5 is set to 1/16 of the input data obtained by shifting the input data by 4 bits, and register Rg6 is set to 1/32 of the input data obtained by shifting the input data by 5 bits. Then, 1/64 of the input data obtained by shifting the input data by 6 bits is set in the register Rg7. Each selector Sel1
And Sel2 are any one of the values of 1/4, 1/8, 1/16, 1/32 and 1/64 of the input data set in each register according to the gain control signal from the comparator 151. Select. And the adder AD
D is the selector Se selected by the selector Sel1
The value (+) selected in l2 or its sign inversion value (-) is added, and the final multiplication value (k · X (t) or k · X
Thus, each multiplier 150 outputs (t-2τ)).
If 2 and 1503 are configured, the multiplication can be performed by the shift operation and the addition, so that the multiplication processing can be performed easily and at high speed.

[0169]

As described above, according to the optical disk recording / reproducing apparatus of the present invention, the maximum likelihood decoding can be applied to the data reproduction from the optical disk, and the amplitude of the reproduced signal waveform becomes smaller due to the higher recording density. Even if the noise-to-noise ratio becomes small, the most likely data can be detected by maximum likelihood decoding. In addition, the first area (VFO) of each unit area (sector)
Region), the equalization target value used in the equalization processing means is calculated based on the sampling data obtained, and the most likely to be reproduced from the sampling data equalized based on the equalization target value. The data is confirmed. Therefore, even if the recording condition in each unit area changes, the data can be stably reproduced from the signal recorded in the second area (data area) of each unit area.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an optical disc recording system of the present invention.

FIG. 2 is a block diagram showing a configuration of a PR precoder.

FIG. 3 is a chart showing a rule of 1/7 modulation.

FIG. 4 is a block diagram showing an embodiment of an optical disc reproducing system of the present invention.

FIG. 5 is a trellis diagram of a partial response characteristic of class 1.

FIG. 6 is a diagram showing a state transition of a partial response characteristic of class 1.

FIG. 7 is a timing chart (No. 1) showing signal processing in the recording system and the reproducing system.

FIG. 8 is a timing chart (No. 2) showing the signal processing in the reproducing system.

9 is a block diagram showing a configuration example of a maximum likelihood decoder shown in FIG.

FIG. 10 is a flowchart showing a maximum likelihood decoded signal.

11 is a block diagram showing another configuration example of the maximum likelihood decoder shown in FIG.

12 is a flowchart showing processing in the maximum likelihood decoder shown in FIG.

FIG. 13 is a block diagram showing still another configuration example of the maximum likelihood decoder shown in FIG.

FIG. 14 is a flowchart showing processing in the maximum likelihood decoder shown in FIG.

FIG. 15 is a diagram showing a reproduction signal including envelope fluctuation.

FIG. 16 is a block diagram showing another configuration example of the maximum likelihood decoder.

17 is a flowchart showing processing in the merge determination unit shown in FIG.

FIG. 18 is a flowchart showing a process in the central value calculation unit shown in FIG.

19 is a flowchart showing processing in the reference value calculation unit shown in FIG.

20 is a flowchart showing a process in the merge detection unit shown in FIG.

21 is a block diagram showing a configuration of a merge determination unit shown in FIG.

22 is a block diagram showing a configuration of a reference value calculation unit shown in FIG.

23 is a block diagram showing a configuration of a central value calculation unit shown in FIG.

24 is a block diagram showing a configuration of a merge detection unit shown in FIG.

FIG. 25 is a timing chart showing signal processing timings in a recording system and a reproducing system.

FIG. 26 is a graph showing a state of an error rate with respect to a low frequency noise amplitude.

FIG. 27 is a diagram showing data on recording pits recorded at a high temperature.

FIG. 28 is a diagram showing data on recording pits recorded at a low temperature.

FIG. 29 is a block diagram showing another application example of the maximum likelihood decoder.

FIG. 30 is a timing chart showing a generation timing of a synchronous clock.

31 is a block diagram showing a configuration example of a merge detection unit in maximum likelihood data detection shown in FIG. 29. FIG.

FIG. 32 is a flowchart showing processing in the merge detection unit shown in FIG.

FIG. 33 is a block diagram showing another example of the reproducing system of the magneto-optical disk device.

FIG. 34 is a diagram showing a configuration example of the switching logic circuit shown in FIG. 33.

FIG. 35 is a timing chart showing a signal processing state of a recording system and a reproducing system by the short hole method.

FIG. 36 is a waveform diagram showing an ideal reproduction signal and a binarized signal (synchronization signal) obtained from the reproduction signal.

FIG. 37 is a waveform diagram showing an actual reproduction signal and a binarized signal (synchronization signal) obtained by slice-detecting the reproduction signal at the ground level.

FIG. 38 is a waveform diagram showing an example of slice levels detected from a reproduced signal whose envelope varies.

FIG. 39 is a waveform diagram showing another example of slice levels detected from a reproduced signal whose envelope varies.

FIG. 40 is a block diagram showing another example of the reproducing system of the magneto-optical disk device.

41 is a waveform chart showing an example of slice levels obtained by the reproduction system shown in FIG. 40.

FIG. 42 is a block diagram showing another example of a reproducing system of the magneto-optical disk device.

43 is a block diagram showing a configuration example of a maximum likelihood decoder in the reproduction system shown in FIG. 42.

FIG. 44 is a flowchart showing the procedure of calculation for obtaining phase error data.

FIG. 45 is a block diagram showing a configuration example of a phase error detection unit.

FIG. 46 is a diagram showing a positive phase error.

FIG. 47 is a diagram showing a negative phase error.

48 is a block diagram showing a configuration example of a PLL circuit in the reproduction system shown in FIG. 42.

FIG. 49 is a block diagram showing another configuration example of the PLL circuit.

FIG. 50 is a timing chart showing signal processing in the recording system and the reproducing system.

FIG. 51 is a block diagram showing another example of the reproducing system of the magneto-optical disk device.

FIG. 52 is a block diagram showing another example of a reproducing system of the magneto-optical disk device.

FIG. 53 is a block diagram showing another example of a reproducing system of the magneto-optical disk device.

FIG. 54 is a block diagram showing another example of a reproducing system of the magneto-optical disk device.

FIG. 55 is a block diagram showing another example of a reproducing system of the magneto-optical disk device.

FIG. 56 is a block diagram showing another example of the reproducing system of the magneto-optical disk device.

FIG. 57 is a waveform diagram showing a state of a reproduced signal in the VFO area.

[Fig. 58] Fig. 58 is a block diagram illustrating another configuration example of the maximum likelihood decoder.

FIG. 59 is a diagram showing an example of a recording format of an optical disc.

FIG. 60 is a timing chart showing processing timing in each sector.

FIG. 61 is a diagram showing a principle of calculation for obtaining an initial value of a central value.

FIG. 62 is a flowchart showing a procedure for obtaining an initial center value.

FIG. 63 is a diagram showing a principle for obtaining comparison reference values Δ1 and Δ2.

FIG. 64 is a flowchart showing a procedure for obtaining comparison reference values Δ1 and Δ2.

FIG. 65 is a flowchart showing a procedure for calculating an average value of positive peak values.

FIG. 66 is a flowchart showing a procedure for calculating an average value of negative peak values.

FIG. 67 is a flowchart showing a processing procedure in a merge determination unit and a reference value calculation unit in which a comparison reference value Δ1 is set.

FIG. 68 is a flowchart showing a processing procedure in the central value calculation unit in which the comparison reference value Δ2 is set.

FIG. 69 is a block diagram showing a configuration of a transversal type equalizer.

FIG. 70 is a flowchart showing a procedure for calculating an average value of positive peak values using the comparison reference value Δ1.

FIG. 71 is a flowchart showing a procedure for calculating an average value of negative peak values using the comparison reference value Δ1.

FIG. 72 is a flowchart showing a procedure for controlling the equalization coefficient in the transversal type equalizer.

FIG. 73 is a block diagram illustrating a configuration example of a multiplier in the transversal equalizer.

FIG. 74 is a block diagram showing a conventional optical disc recording system.

FIG. 75 is a diagram showing a relationship between recording data and pits formed on the optical disc.

FIG. 76 is a block diagram showing a conventional optical disc reproducing system.

[Fig. 77] Fig. 77 is a diagram illustrating a relationship between a conventional reproduction signal system and demodulation data.

FIG. 78 is a diagram showing reproduced signal waveforms in high density recording and low density recording.

[Explanation of symbols]

1 optical disc 2 Optical head 3 Data output unit 4 modulator 5 Laser drive unit 6 amplifier 7 Filter / Equalizer 8 peak detector 9 PLL circuit 10 demodulator 11 Length limit modulator 12 PR modulation precoder 13 A / D converter 14 Run-length limited maximum likelihood decoder 17 Binarization circuit 18 D / A converter

─────────────────────────────────────────────────── ─── Continuation of front page (31) Priority claim number Japanese Patent Application No. 6-167206 (32) Priority date July 19, 1994 (July 19, 1994) (33) Country of priority claim Japan (JP) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 20/10 321 G11B 20/14 341

Claims (2)

(57) [Claims] 1. A unit having a first area for recording a stationary pattern signal modulated according to a recording rule of a predetermined partial response characteristic and a second area for recording a random recording data signal. In a system for reproducing data from an optical disc in which information is recorded in each area, a signal reproducing unit for reproducing a signal from the optical disc, and a sampling unit for sampling the reproduced signal at a predetermined timing and outputting the sampling data. , The equalization processing means for performing the equalization processing of the sampling data from the sampling means based on the equalization target value, and the most likely to be reproduced based on the sampling data processed by the equalization processing means The maximum likelihood data detection means for fixing the data and the second area in each unit area Data generating means for generating recording data from the data determined by the maximum likelihood data detecting means based on the sampling data processed by the processing means, and sampling data obtained in the first area in each unit area. A data reproducing system having an equalization target value calculation means for calculating an equalization target value used in the equalization processing means based on the above. 2. The data reproducing system according to claim 1, wherein the unit area is a sector having a VFO area as a first area and a data area as a second area.