JP3450299B2 - Collection method and apparatus for implementing the method - Google Patents

Abstract

An acquisition method for identifying a transmitter, and a correlator for carrying out the method includes correlating a received binary-coded spread sequence having m bits at a frequency f with a locally generated spread sequence by phase-shifting a multiplicity of locally generated spread sequences with respect to the received spread sequence, where f is the frequency of the incoming spread sequence. The received spread sequence is correlated with a locally generated spread sequence at the frequency f. The received spread sequence is stored and the stored, received spread sequence is processed at an oversampling rate i*f. The received, stored spread sequence is split into i sections and the correlation is carried out in i steps.

Description

Detailed Description of the Invention

The present invention relates to a method for collecting by a receiver a transmitter transmitting a binary coded spreading sequence. The invention further relates to a device for implementing this method. US-PS 5768306 and corresponding EP 0668663B1 relate to a sliding correlator having a memory circuit for storing a received signal and a time control generator for generating a clock signal. The clock signal is used to read the received signal stored in the memory circuit at a frequency much higher than the memory rate of the received signal. Further, the sliding correlator is a spread code sequence copy generator for copying the spread code sequence, a multiplier for multiplying the read received signal by a copy of the spread code, this multiplication over a predetermined time. It has an accumulator device for storing the output signal of the device and a threshold detection device for detecting whether the output signal of the accumulator device exceeds a predetermined threshold value. Further, a clock generator for controlling the spread code copy generator for generating the spread code sequence at the same rate as the clock signal is provided, and when the detection output signal of the threshold detection device is smaller than the threshold, The clock generator is adapted to change the phase of a copy of the spreading code sequence.

The basic spreading method is the direct sequence method. In this case, the information is modulated by a relatively high frequency pseudo-random binary sequence before transmission. From the pseudo noise signal generated in this case, the receiver
Extract information by knowing the binary sequence.

Such methods are used in data communications, localization and navigation. The problem then arises that the receiver receives signals from several transmitters and then has to determine the temporal state of these signals in order to identify them.

An important area of use of such a method is inter alia system NAVSTAR GPS (Nav igation S ystem with T imi
ng A nd R anging, a real-time satellite navigation by G lobal P ositioning S ystem). A large number of satellites are used here as transmission networks controlled by ground stations or control stations. At least 4 for 3D positioning of the receiver
There must be one satellite in view of this receiver. The transmitter information is demodulated at the receiver and the necessary calculations are made from this information. In order for the receiver to be able to identify the satellite and evaluate this satellite's information, it must know the transmitter's unique code (Gold code). This transmitter-specific code is transmitted as a periodic signal sequence of preset length. To find this code, all codes of the satellite are stored at the receiver. Usually, the code for any satellite is first generated and compared to the received code. Usually, but if it is not the expected satellite, the comparison with the stored code must be performed until a match is detected.

Furthermore, since the phase of each arriving signal is not known, in some cases the signal with the received code must be shifted until a match is detected. The comparison is done via the correlation function of the signal which will be approximately 1 when synchronization is present. If all possible stored codes and their phases are considered for this search process,
In principle, a long search time must be taken.

Schroedter, GPS-Satelliten-Navigation,
A method for reducing the collection time is known from Franzis-Verlag Muenchen, 1994. For example, receivers with multiple channels are used, these receivers being able to search correspondingly to the number of channels. However, this results in a relatively large circuit cost.

The object of the present invention is to provide a method and a device of the type mentioned at the outset in which the acquisition time is reduced.

In the method, the above problems are solved by the following. That is, in a method for collecting by a receiver a transmitter that transmits a binary coded spreading sequence, the receiver sends a spreading sequence having m bits of binary coded input at a frequency f to multiple locals. Correlating with the generated spreading sequence, the locally generated spreading sequence is divided into k intervals each having n bits, and the correlation with the locally generated spreading sequence has the following steps:
That is, a step of dividing the received and stored spreading sequence into k sections each having n bits, each section of the received spreading sequence belonging to a locally generated spreading sequence and a frequency of k * f. Correlating the bits in each interval after correlation with each of the intervals of the received spreading sequence by one bit to the right, and the arriving bit is used as the least significant bit of the first interval. , For other intervals, the most significant bit of the preceding interval is buffered and stored in the position of the least significant bit of this other interval.

In the device, the above problems are solved by the following. That is, it has a first memory, in which a section of a spreading sequence locally generated in this first memory is stored, has a second memory and this second memory
In the memory of the received spreading sequence is stored and has a feedback-coupled shift register for serial accommodation of the received signal sequence, the shift register being parallel on the input side with a second shift register. Connected to the output side of the data memory and to the input side of this second data memory in parallel on the output side, for comparing the duration of the locally generated spreading sequence with the duration of the received spreading sequence Is solved by having a comparator of

The present invention has the following advantages: That is, a transmitter synchronization or a match between the received and stored codes is performed more quickly than in the case of a detection in which the detection is normally sequential by the oversampling rate. If operated at an oversampling rate of 32 times, for example, the synchronization process is done 32 times faster than with conventional methods.

For simple and fast processing, the correlation results obtained for each interval are advantageously summed and then a maximum search is carried out over all summed correlation results.

In this way the signal sequence is divided into data word lengths, which are processed in a simple manner by conventional data processing modules such as shift registers, memories and the like. Further, it has the following advantages. That is, the shifting of the position of the individual bits of the received signal sequence is performed by a feedback coupled shift register in the form of a FIFO memory.

The invention will now be further described on the basis of the embodiments illustrated in the drawings.

FIG. 1 schematically shows a receiver known per se of a GPS navigation system, FIG. 2 schematically shows a detail of the receiver of FIG. 1 and FIG. 3 a detail of the circuit arrangement of FIG. The arrangement of the adder is schematically shown as.

FIG. 1 shows a receiver for implementing the spreading method as used, for example, in data communications, mobile radio and localization and navigation. The structure and function of this receiver will now be described for application in GPS localization and navigation systems. This is because these operations are basically typical of the operations applied in all other receivers of the spreading method. In this case, in addition to the completely determined transmitter signal, the received signal, which also contains all other valid transmitter information, is found from the noise level of the whole signal.

All signals arriving as a spreading sequence from an antenna (not shown) are quadrature modulated and mixed to baseband by a quadrature modulator. The quadrature component Q and the in-phase component I are each quantized by an analog / digital converter (not shown) having a word width of 1 bit.

These signals are then fed to two branch path correlators 2 or 2'of identical construction. In these two branch path correlators, the Gold code of the satellite to which each belongs is found from the noise level of all signals. The output signals of the correlators 2, 2 ′ are fed to a power calculator 30, in which the absolute square values are calculated in the units 3, 3 ′ from these two branches, respectively, and in the adder 4 they are summed. To be done. From this summed signal, the root is determined in unit 5, and finally, for improved reliability, the signal strength is accumulated M times in accumulator 6 over the determined result.

The Gold code generator 8 supplies to the correlators 2 and 2'the Gold code which is a problem during the search.

FIG. 2 shows details of the correlator 2 of FIG. Since both correlators have the same structure, the description is limited to the correlator 2.

Each time generated Gold code, also called a chip with a length of m = 1023 bits, is stored in the data memory 24 and held for the search duration.
The Gold code is in this case divided into k = 32 intervals, each with n = 32 bits, resulting in 32 memory locations each with 32 bits (or 31 bits).
Is stored. The input signal I is input clock controlled serially via the 1-bit register 20 bit by bit to the FIFO shift register 21, for example, by the first frequency f of 1 MHz. In this case, the FIFO shift register 21 has 32 register positions. This FIF
The O shift register 21 operates at an oversampling rate of i * f, i.e. 32 MHz.

The data memories 23 and 24 have address pointers. These address pointers control reading and reading via the control unit 32 so that 32-bit words are stored in the order of input. The correlation starts at the latest 32-bit word and ends at the oldest 32-bit word.

Within the 32-bit word, the most recent, or last, read bit is the least significant and the oldest bit is the most significant.

The FIFO shift register 21 has 32 units one after another.
Used to generate bitwords, these 32
A bitword is distinguished from the preceding 32-bit word by shifting from the least significant bit to the most significant bit by one bit each time.

The correlation is carried out as follows: the instantaneous 32-bit word is in the most significant direction before the new spreading bit of the received spreading sequence or of the received signal I'is read into the least significant register location 20. And the most significant bit is read into the buffer register 33 used as a delay element. The bits of the received signal I'are written to the least significant. The FIFO shift register 21 now contains the newly received bit in the least significant register position and the older three in the remaining register positions.
It contains the 31 least significant bits of a 2-bit word. At the same time, the adder 28 is reset to the value zero. The new 32-bit word is stored in the data memory 23, which is formed as a RAM, under the address from which the preceding 32-bit word was read.

The memory contents are read out one after the other for all the remaining memory locations of the data memory 23 and compared in the XOR comparator 27 with the corresponding memory contents of the data memory formed as a RAM. Comparator 27 provides a 32-bit long result. In the post-adder 29, the sum of all the logical 1 values of this 32-bit word is determined.

At the same time, an instantaneous 32-bit word is written from the data memory 23 to the FIFO 21 and shifted by 1 bit from the least significant to the most significant. The bits previously buffered in the register 33 are now read into the bottom 20 of the FIFO shift register 21. The new word thus generated is stored in the data memory 23 under its old address. Then again the data memory 24
The comparison of the Gold code stored in the corresponding section with the corresponding section is carried out as described above.

In this way, when all 32 words stored in the data memory 23 are processed in 32 cycles, the correlation result is calculated by the adder 28.

The contents of the FIFO shift register 21 are 32
The data is stored in parallel at a first address of the data memory (RAM 23) via the bus 34 in MHz. After that, the address pointer of the RAM 23 is moved up by one position, and the FIFO shift register 21 has a new address of 3
A 2-bit long data word is loaded and the correlation process is started from the beginning.

A Gold code generator 8 (FIG. 1) in yet another data memory RAM 24 having 32 memory locations, each having 32 bits, like RAM 23.
The Gold code generated by is stored. The preset chip length n = 3 of the received chip sequence
In the same way that the section 2 is stored in the RAM 23, the Gold code is divided into sections of the preset length n = 32 in the further RAM 24 and stored under 32 consecutive addresses. It Both RAM2
The outputs of 3 and 24 are fed to the XOR comparator 25 via parallel buses 25 to 26, each having a width of 32 bits, and then checked bit by bit for a match. The bits indicating the coincidence are summed by the bit adder 27 and the accumulator 28 for 32 cycles.

FIG. 3 shows a particularly fast operating example of the bit adder 27 of FIG. This bit adder consists of a cascaded interconnection of 2-bit adders ADD, the output of each of the two adders ADD being connected to the input of the subsequent adder ADD of the next stage. Therefore, in the following example, 16 adders ADD are required to sum the 32 bits in the first stage. The second stage has 16 adders ADD and so on.

The possible maximum value search is carried out, for example, in the calculation unit 31 by carrying out a maximum value search over all the signals of the accumulator 6. [Brief description of drawings]

1 diagrammatically shows a receiver known per se of a GPS navigation system, FIG.

2 schematically shows details of the receiver of FIG.

FIG. 3 schematically shows the arrangement of adders as a detail of the circuit arrangement of FIG.

[Explanation of symbols]

2, 2'correlator 3,3 'unit 4 adder 5 units 6 Accumulator 8 Gold code generator 20 1-bit register 21 FIFO shift register 23 Data memory 24 data memory 25, 26 parallel bus 27 XOR comparator 28 Accumulator 29 adder 32 control unit 30 power calculator 31 Calculation Unit 34 bus

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 13/00-13/06 H04B 1/69-1/713

Claims (5)

(57) [Claims] 1. A binary coded spreading sequence
In the method for collecting the transmitter to be transmitted by the receiver
And the receiver is binary coded input at the frequency f.
Multiple spreading sequences with m bits
Locally generated correlations with the spreading sequences generated in
The generated spreading sequence is k with n bits each
Locally generated spreads divided into
Correlation with a sequence has the following steps:
The received and stored spreading sequences are each n bits
Dividing each section of the received spreading sequence locally into k sections with
Phase of the spread sequence and the frequency of k * f
The correlation step, after the correlation of each of the intervals of the received spreading sequence.
Shifts the bit in each section to the right by 1 bit
Then, the bit that arrives as the least significant bit of the first section
Is used, the highest rank of the preceding section for other sections
Bits are buffered and the least significant bit of the other
Binary encoded, with steps stored in position
The transmitter that transmits the spread sequence
How to gather. 2. Correlation results obtained for each interval are summed and then a maximum search is performed over all summed correlation results.
The method of claim 1, wherein the method is performed. 3. The number of sections having a preset length is k = 3.
3. The method according to claim 1, wherein the chip length is 2 and the chip length of the section is n = 32. 4. A device for carrying out the method according to claim 1.
A first memory, and a local memory in the first memory.
The interval of the spreading sequence generated in is stored,
Having a second memory and receiving at the second memory
The spread spectrum sequence section is stored and is used for serial accommodation of the received signal sequence.
A shift register coupled back to the shift register
Is connected to the output side of the second data memory in parallel on the input side.
Said second data memory connected in parallel on the output side
Is connected to the input side of and receives a section of the locally generated spreading sequence.
Has a comparator for comparing the intervals of the spread sequence
The method according to claim 1, characterized in that
Device. 5. An adder is present on the output side of the comparator, and as a result, the logical values generated at the coincident bit positions in the bit-by-bit comparison are summed up, and the adder is a cascade of 2-bit adders. 5. An apparatus as claimed in claim 4, characterized in that the output side of each of the two adders is connected to the input side of a subsequent adder.