JP3450217B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device which enables a smooth memory test for a product before shipment.

[0002]

2. Description of the Related Art In a semiconductor device equipped with a DRAM (Dynamic RAM), a RAS (Row Address Strobe) and a CAS (C
A pair of signals of “Olumn Address Strobe” is used. By using these signals, the same address line can be used for both row (row) addresses and column (column) addresses, and the number of device pins can be reduced to reduce the cost of the package.

FIG. 3 is a time chart showing an address fetch timing in a semiconductor device equipped with a DRAM. In this semiconductor device, the chip select signal and the row address signal are captured by the input RAS, and the column address signal is captured by the input CAS.

When the memory test of the DRAM is carried out prior to shipping, each signal of RAS and CAS is sent from one device pin from the test apparatus. This allows
In the first stage, the chip select signal and the row address signal are fetched by the RAS from the device pin, and in the second stage, the column address signal is CA from the same device pin.
Captured by S.

[0005]

However, in the above semiconductor device, when the chip select signal fetched from the device pin in the first step switches the internal circuit to the inactive state, the chip select signal is switched to the active state. Until the column is returned to the (active) state, even if a column address signal is input from the same device pin, it cannot be captured and the memory test may not be smoothly performed.

In view of the above, it is an object of the present invention to provide a semiconductor device capable of smoothly conducting a memory test even when an internal circuit is fixed in an inactive state by a chip select signal taken in from a device pin. And

[0007]

In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device having an internal circuit, and outputs a selection signal for activating the internal circuit in response to an input signal. Chip select circuit,
And a test circuit that responds to a test input signal and outputs a test active signal that forcibly switches the internal circuit to active regardless of whether the selection signal is active or inactive.

In the semiconductor device of the present invention, since the internal circuit can be forcibly switched to the active state by the operation of the test circuit, when the internal circuit is fixed to the inactive state by the chip select signal fetched from the device pin. However, the memory test can be smoothly performed.

Here, in the preferred semiconductor device of the present invention, it is preferable that the test circuit responds to a test input signal having a potential equal to or higher than a predetermined potential. In this case, the test active signal can be output in response to the test input signal.

The chip select circuit further includes an inverter for receiving an input signal, first and second PchMOS transistors connected in series between an input terminal and an output terminal,
It may also have third and fourth PchMOS transistors connected in series between the output of the inverter and the output terminal, and a fifth PchMOS transistor connected between the output terminal and the low potential power supply. This is a preferred embodiment of the present invention. In this case, the operation mode of the chip select circuit can be changed by appropriately selecting the depletion type PchMOS transistor.

For example, the third to fifth PchMOS transistors are enhancement type, and the first and second PchMOS transistors are
The transistor can be a depletion type.
In this case, the internal circuit can be activated when the input signal is low level.

Alternatively, it is also a preferable embodiment that the first, second and fifth PchMOS transistors are enhancement type and the third and fourth PchMOS transistors are depletion type instead of the above. In this case, the internal circuit can be activated when the input signal is at the high level.

Alternatively, in place of the above, the first to fourth
PchMOS transistor is an enhancement type, the fifth
It is also a preferable embodiment to use a depletion type PchMOS transistor. In this case, the internal circuit can be activated regardless of the level of the input signal.

Further, in the test circuit, a test PchMOS transistor and Nc are connected in series between a test input terminal and a low potential power source and each gate is connected to a high potential power source.
It is preferably composed of an hMOS transistor and a test inverter whose input is connected to the drains of the test PchMOS transistor and the NchMOS transistor.
In this case, during a memory test, a test active signal can be output by applying a potential equal to or higher than the sum of the power supply voltage and the threshold value of the test PchMOS transistor to the test input terminal.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail based on the embodiments of the present invention with reference to the drawings. Figure 1
FIG. 1 is a block diagram showing a main configuration of a semiconductor device according to an exemplary embodiment of the present invention. The semiconductor device has an internal circuit (not shown), an input protection circuit 24, an address buffer 25, a chip select circuit 10, and a test circuit 26.

The input protection circuit 24 transfers the address signal and the chip select input signal to the address buffer 25 and the chip select circuit 10, respectively. The address buffer 25 sends the received address signal to the internal circuit.

The chip select circuit 10 outputs a selection signal for switching the active / inactive state of the internal circuit in response to the chip select input signal. When necessary, the test circuit 26 outputs a test active signal for forcibly switching the internal circuit to the active state regardless of the active / inactive state by the selection signal.

FIG. 2 is a circuit diagram showing the chip select circuit 10, the test circuit 26, and their peripheral circuits. The chip select circuit 10 includes an inverter 12 having an input connected to an input terminal 28, PchMOS transistors 16 and 17 connected in series between the input terminal 28 and an output node (output terminal) 29, and an output of the inverter 12. And output node 2
PchMOS transistor 18 connected in series with 9
19, Pc connected between the output node 29 and Vss
and an hMOS transistor 20. The gates of the PchMOS transistors 16 and 17 are commonly connected to both drains and sources, the gates of the PchMOS transistors 18 and 19 are commonly connected to both drains and sources, and the gate of the PchMOS transistor 20 is connected to the drain (Vss). .

Any of the PchMOS transistors 16 to 20 is selectively changed from the enhancement type to the depletion type by implanting ions such as boron in the manufacturing process. The chip select circuit 10 having such a configuration selects valid / invalid of the chip select input signal input via the input protection circuit 24.

For example, when only the PchMOS transistors 16 and 17 are of the depletion type, if the chip select input signal is low level (L), both the PchMOS transistors 16 and 17 are turned on and the PchMOS transistor 1 is turned on.
Since both 8 and 19 are off and the PchMOS transistor 20 is off, the potential at the output node 29 becomes "L". As a result, one input of the NAND gate 11 is fixed to "L", so that the NAND gate 11 outputs a high level (H) regardless of the level of the other input. Further, this output is inverted by the inverter 15,
It is sent as an "L" chip select signal, and the internal circuit becomes active.

When only the PchMOS transistors 18 and 19 are of the depletion type, when the chip select input signal is "H", both the PchMOS transistors 18 and 19 are turned on and both the PchMOS transistors 16 and 17 are turned off. Since the PchMOS transistor 20 is off,
The potential at the output node 29 becomes "L". Therefore, similarly to the above, the NAND gate 11 outputs "H" regardless of whether the other input is "L" or "H", and the internal circuit becomes active.

On the other hand, when only the PchMOS transistor 20 is of the depletion type, the PchMOS transistor 16
All through 19 are turned off regardless of whether the chip select input signal is "L" or "H", and only the PchMOS transistor 20 is turned on. Therefore, the potential at the output node 29 becomes "L", so that the internal circuit becomes active similarly to the above.

As described above, in the manufacturing process, by selectively implanting ions into the channel region of the PchMOS transistor according to the purpose, when the chip select input signal is "H", "L", or , "H" or "L", the chip select circuit 10 for activating the internal circuit can be obtained. Table 1
Summarized in. 16 to 20 in the table correspond to the reference signs of PchMOS transistors. * Indicates that the ion implantation was used to form the depletion type.

[0024]

[Table 1]

The test circuit 26 includes a PchMOS whose gate is connected to Vdd and whose source is connected to the test input terminal 27.
The transistor 21 and the gate are connected to Vdd, and the drain is connected to the drain of the PchMOS transistor 21.
The NchMOS transistor 22, the gate is connected to Vdd, the drain is connected to the drain of the NchMOS transistor 22, the source is connected to Vss, and the input is commonly connected to the drains of the PchMOS transistor 21 and the NchMOS transistor 22. Inverter 13 that has been set.

The NAND gate 11 outputs the inverted value of the logical product of the outputs of both the chip select circuit 10 and the test circuit 26, and the inverter 15 inverts the output of the NAND gate 11 and outputs it as a chip select output signal to the internal circuit. Send to.

In the semiconductor device having the above structure, the power supply voltage (Vdd) and the PchMOS are applied to the test input terminal 27 during the memory test.
A potential equal to or higher than the potential obtained by adding the threshold value of the transistor 21 is applied. As a result, the PchMOS transistor 21 is turned on, and the test circuit 26 including the PchMOS transistor 21 and the NchMOS transistors 22 and 23 outputs "H". Therefore, while the above potential is applied to the test input terminal 27, the test circuit 26 drives the inverter 13
"L" is output as a test signal via the. Therefore, since the other input of the NAND gate 11 is fixed to "L", the internal circuit becomes active regardless of the level of the output signal of the chip select circuit 10.

In the present embodiment, the internal circuit is forcibly switched to the active state by the test signal from the test circuit 26 even if the internal circuit is fixed in the inactive state by the chip select signal fetched from the device pin. The memory test can be smoothly performed.

Pc in the chip select circuit 10
It is also possible to configure each of the hMOS transistors 16 to 20 by an NchMOS transistor so that the same effect as that of the above-described embodiment can be obtained.

Although the present invention has been described based on the preferred embodiments thereof, the semiconductor device of the present invention is not limited to the configurations of the above-described embodiments, and the configuration of the above-described embodiments is not limited thereto. Semiconductor devices that have undergone various modifications and changes are also included in the scope of the present invention.

[0031]

As described above, according to the semiconductor device of the present invention, even if the internal circuit is fixed in the inactive state by the chip select signal fetched from the device pin, the internal circuit is forced to the active state. The memory test can be smoothly performed by switching.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a chip select circuit, a test circuit, and peripheral circuits thereof.

FIG. 3 is a time chart showing an address fetch timing in a semiconductor device.

[Explanation of symbols]

10: Chip select circuit 11: NAND gate 12, 15: Inverter 16-21: Pch MOS transistor 22, 23: Nch MOS transistor 24: Input protection circuit 25: Address buffer 26: Test circuit 27: Test input terminal 28: Input terminal 29: Output node

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 29/00 G11C 11/401-11/419

Claims (7)

(57) [Claims] 1. A chip select signal and an address signal
For semiconductor devices that are input from common device pins
The internal circuit that takes in the address signal in the active state.
And road, in response to the chip select signal, a chip select circuit for outputting a selection signal for the internal circuit to the active state, in response to the test input signals, how the active state / inactive state by the selection signal A semiconductor device comprising: a test circuit that outputs a test active signal forcibly switching the internal circuit to the active state regardless of the internal circuit. 2. The semiconductor device according to claim 1, wherein the test circuit responds to a test input signal having a potential equal to or higher than a predetermined potential. 3. The chip select circuit comprises the device
An inverter that receives an input signal from the spin and first and second PchMOSs connected in series between the input terminal and the output terminal
A transistor, a third and a fourth PchMOS transistor connected in series between the output of the inverter and the output terminal, and a fifth PchMOS transistor connected between the output terminal and the low potential power supply. Having, claim 1 or 2
The semiconductor device according to. 4. The third to fifth PchMOS transistors are enhancement type, and the first and second PchMOS transistors are provided.
The semiconductor device according to claim 3, wherein the transistor is a depletion type. 5. The first, second and fifth PchMOS transistors are enhancement type transistors, and the third and fourth PchMOS transistors are enhancement type transistors.
4. The semiconductor device according to claim 3, wherein the PchMOS transistor is a depletion type. 6. The semiconductor device according to claim 3, wherein the first to fourth PchMOS transistors are enhancement type, and the fifth PchMOS transistor is depletion type. 7. The test circuit comprises a test PchMOS transistor and an NchMOS connected in series between a test input terminal and a low-potential power supply and having each gate connected to a high-potential power supply.
7. The semiconductor device according to claim 1, comprising a transistor and a test inverter whose input is connected to the drains of the test PchMOS transistor and the NchMOS transistor.