JP3450060B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer gate interposed between a bit line and a data bus of a semiconductor memory device.

In recent years, the operating speed of semiconductor integrated circuit devices connected to semiconductor memory devices has been increasing. In order to smoothly transmit signals between such a semiconductor integrated circuit device and a semiconductor memory device, it is necessary to improve the operating speed of the semiconductor memory device. Therefore, it is necessary to improve the read speed and the write speed of the semiconductor memory device.

[0003]

2. Description of the Related Art FIG. 7 shows an example of a conventional DRAM. A large number of bit lines BL, BL arranged in the cell array
Are connected to a large number of memory cells C, and each memory cell C is connected to a word line WL.

A precharge voltage VPR is supplied to the bit lines BL and bar BL via N channel MOS transistors Tr1 and Tr2, and N channel MOS transistors Tr3 and Tr4 are connected between the bit lines BL and bar BL. It

A reset signal RS is input to the gates of the transistors Tr1 to Tr4. Therefore, when the reset signal RS becomes H level, the transistors Tr1 to Tr4 are
Is turned on, and the bit lines BL and BL are reset to the precharge voltage VPR.

A sense amplifier SA is connected between the bit lines BL and BL, and the high potential side power supply PSG and the low potential side power supply NSG are supplied to the sense amplifier SA when activated.

The bit lines BL and bar BL are connected to the data buses DB and bar DB through a transfer gate Tg composed of an N channel MOS transistor. A column selection signal CL output from a column decoder (not shown) is input to the transfer gate Tg, and when the column selection signal CL becomes H level, the transfer gate Tg is turned on.

An amplitude suppressing circuit (not shown) is connected to the data bus DB and the bar DB, and the data bus DB and the bar DB are provided except during the read operation and the write operation.
Is maintained at a potential lower than the power supply Vcc by the threshold value of the transistor of the amplitude suppression circuit.

A write amplifier and a sense buffer are connected to the data buses DB and DB. Then, in the read operation, the cell information read to the data bus DB and the bar DB is output via the sense buffer and the output buffer, and in the write operation, write data input from the outside is transferred to the data bus DB via the write amplifier. , Is output to the bar DB.

When a word line is selected during a read operation of the DRAM thus constructed, cell information is read from the memory cell C connected to the word line to either the bit line BL or the bar BL. , A slight potential difference occurs between the bit lines BL and BL.

In this state, when the high potential side power source PSG and the low potential side power source NSG are supplied to the sense amplifier SA, the sense amplifier SA is activated and the potential difference between the bit lines BL and bar BL is enlarged. .

Next, when the column selection signal CL becomes H level, the transfer gate Tg is turned on, and the potentials of the bit lines BL and BL are changed to the data bus D via the transfer gate Tg.
It is transmitted to B and bar DB, and the same data bus DB and bar D
A potential difference occurs in B. And data bus DB, bar D
The cell information read in B is output via the sense buffer and the output buffer.

In the write operation, when the column select signal CL becomes H level while the write amplifier outputs the write data to the data buses DB and DB, the transfer gate Tg is turned on and the write data is transferred to the bit line B.
The write operation is performed on the memory cell selected by the word line based on the write data transmitted to the L and bar BL.

[0014]

DRAM as described above
Then, the output of the read data from the bit lines BL and bar BL to the data bus DB and bar DB, and the data bus DB and
Input of write data from the bar DB to the bit lines BL and BL is both performed via the transfer gate Tg.

Therefore, if the signal transmission speed at the transfer gate Tg is improved, the read speed and the write speed can be improved. Therefore, if the size of the transfer gate Tg is increased, the signal transmission speed from the data buses DB and bar DB to the bit lines BL and bar BL is improved, so that the writing speed can be improved.

However, during the read operation, the data buses DB and DB are maintained at the level near the power supply Vcc by the amplitude suppressing circuit. When the size of the transfer gate Tg is increased, when the transfer gate Tg is turned on, the same bit is generated due to the potential difference between the bit lines BL and bar BL from which the cell information is output from the sense amplifier SA and the data buses DB and bar DB. A current suddenly flows between the line BL, bar BL and the data bus DB, bar DB.

Then, the bit line potential at the high potential side level may fall and the bit line potential at the low potential side level may rise, and the output signal of the sense amplifier SA may be inverted by using this as a trigger. Even when the output signal of the sense amplifier SA is not inverted, the bit lines BL, B
Since the fluctuation of the potential of L is large, it takes time to restore the fluctuation by the sense amplifier SA. As a result, the signal transmission speed to the data bus DB and the bar DB decreases, and the reading speed decreases.

As described above, when the size of the transfer gate Tg is increased, erroneous data is read during the read operation or the read speed is reduced. Therefore, in order to improve the read speed, the size of the transfer gate Tg is increased. You cannot do it.

Therefore, since it is necessary to increase the size of the transfer gate Tg within the range where the read speed is not lowered, there is a problem that both the write speed and the read speed cannot be improved.

An object of the present invention is to provide a semiconductor memory device having a transfer gate which can contribute to improvement of writing speed and reading speed.

[0021]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the transfer gate interposed between the bit line BL, bar BL and the data bus DB, bar DB is
It is composed of a P-channel MOS transistor Trp and an N-channel MOS transistor Trn connected in parallel, and turns on only the N-channel MOS transistor Trn during a cell information read operation and at least the P-channel MOS transistor during a cell information write operation. Trp
The column selection signals CL and CLW for turning on are input from the column decoder 3 to the gates of the transistors Trn and Trp.

In addition, the bit lines BL,
The bar BL and the word line WL are connected to each other, and a transfer gate Tg for controlling transfer of read data and write data is interposed between the bit line BL, bar BL and the data bus DB, bar DB, and the data bus DB is connected. , Bar DB is a semiconductor memory device to which an amplitude suppressing circuit for suppressing the amplitude of the data bus at the time of reading cell information is connected, and is a P-channel MOS transistor T connected in parallel.
The transfer gate is formed by rp and the N-channel MOS transistor Trn, and the N-channel MOS transistor Trn is used during the read operation of the cell information from the memory cell C.
Column select signals CL, CLW for turning on only the above and for turning on at least the P-channel MOS transistor Trp at the time of writing the cell information are input from the column decoder to the gates of the transistors Trp, Trn.

Further, the column decoder outputs a first column selection signal CL which becomes H level when the column is selected.
Is output to the gate of the N-channel MOS transistor Trn, and the second column selection signal CLW which becomes L level when the column is selected is output to the gate of the P-channel MOS transistor Trp based on the write control signal WE in the write operation. To be done.

[0024]

When the cell information is read out, the cell information is transmitted from the bit lines BL and bar BL to the data buses DB and bar DB through the N-channel MOS transistor Trn forming the transfer gate, and the cell information write operation is performed. At times, among the transistors forming the transfer gate, write data is transmitted from the data buses DB and bar DB to the bit lines BL and bar BL through at least the P-channel MOS transistor Trp. Therefore, the transistor size can be changed between the read operation and the write operation.

During the cell information read operation, the bit lines BL and bar BL to the N channel MO are connected to the data buses DB and bar DB whose amplitudes are suppressed by the amplitude suppressing circuit.
Cell information is transmitted through the S transistor Trn. During the write operation, the write data is transmitted from the data buses DB and DB to the bit lines BL and BL via the P-channel MOS transistor Trp forming the transfer gate, and the voltage drop of the write data due to the transfer gate is reduced.

Further, during a read operation, an N channel M that constitutes a transfer gate based on a first column selection signal CL output from a column decoder when the column is selected.
The OS transistor Trn is turned on, and the N-channel MOS transistor Trn and the P-channel MOS transistor Trp forming the transfer gate are turned on based on the first and second column selection signals CL and CLW during the write operation.

[0027]

FIG. 2 shows an embodiment embodying the present invention. The same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

This embodiment differs from the prior art in that a transfer gate Tg is formed by connecting a P-channel MOS transistor Trp and an N-channel MOS transistor Trn in parallel.

The column selection signal CLW is input to the gate of the transistor Trp, and the column selection signal CL is input to the gate of the transistor Trn. The transistor Trn is formed to have a size suitable for a cell information reading operation.

A column decoder for generating the column selection signals CLW and CL is shown in FIG. Predecode signal Ga
Is input to the inverter circuit 1a, and the inverter circuit 1a
The output signal of a is input to the inverter circuit 1b. Then, the inverter circuit 1b outputs the column selection signal C
L is output.

P is connected to the input terminal of the inverter circuit 1b.
The drains of the channel MOS transistors Tr5 to Tr7 are connected, and the sources of the transistors Tr5 to Tr7 are the power source Vcc.
Connected to.

The source of the N-channel MOS transistor forming the inverter circuit 1a is connected to the power supply Vss via the N-channel MOS transistors Tr8 to Tr10 connected in series.

A predecode signal Gb is input to the gates of the transistors Tr8 and Tr5, a predecode signal Gc is input to the gates of the transistors Tr9 and Tr6, and a gate of the transistors Tr10 and Tr7 is input to the gates of the transistors Tr10 and Tr7.
The predecode signal Gd is input.

The input signal of the inverter circuit 1b is NO.
It is also input to one input terminal of the R circuit 2, and the write control signal WE is input to the other input terminal of the NOR circuit 2. The write control signal WE becomes H level during the read operation and becomes L level during the write operation.

The output signal of the NOR circuit 2 is input to the inverter circuit 1c, and the column selection signal CLW is output from the output terminal of the inverter circuit 1c. In the column decoder thus configured, when any of the 4-bit predecode signals Ga to Gd becomes L level, any of the transistors Tr8 to Tr10 is turned off, the inverter circuit 1a is inactivated, and the transistor Tr5 ~ Tr7
Is turned on.

Then, the output signal of the inverter circuit 1a becomes H level, the column selection signal CL output from the inverter circuit 1b becomes L level, and the column concerned is brought into the selected state. Further, the column selection signal CLW becomes H level regardless of the write control signal WE.

Further, the 4-bit predecode signal Ga ...
When all Gd become H level, the transistors Tr8 to T8
r10 is turned on, the inverter circuit 1a is activated,
The transistors Tr5 to Tr7 are turned off.

Then, the output signal of the inverter circuit 1a becomes L level, the column selection signal CL output from the inverter circuit 1b becomes H level, and the column is brought into the selected state.

Further, in this state, when the write control signal WE becomes H level, the column selection signal CLW becomes H level, and when the write control signal WE becomes L level, the column selection signal CLW becomes L level.

FIG. 4 shows an amplitude suppressing circuit connected to the data bus DB and the bar DB. The control signal SG1 which becomes H level during the read operation is input to the gates of the N-channel MOS transistors Tr11 and Tr12, and the drains of the transistors Tr11 and Tr12 are connected to the power supply Vcc.

The source of the transistor Tr11 is connected to the drain of the N-channel MOS transistor Tr13,
The source of the transistor Tr12 is connected to the drain of the N-channel MOS transistor Tr14.

The source of the transistor Tr13 is connected to the drain of the N-channel MOS transistor Tr15,
The source of the transistor Tr14 is connected to the drain of the N-channel MOS transistor Tr16. The gates of the transistors Tr13 and Tr14 have L
The level control signal SG3 is input.

A power supply Vcc is supplied to the gates of the transistors Tr15 and Tr16, and the transistors Tr15 and Tr1 are supplied.
The source of 6 is connected to the power supply Vss. Further, the transistors Tr15 and Tr16 are formed in a small size. Therefore, the transistors Tr15 and Tr16 are always turned on in the high resistance state.

A P-channel MOS transistor Tr17 is connected between the sources of the transistors Tr11 and Tr12. The gate of the transistor Tr17 is
A control signal SG2 that becomes L level during standby is input.

Vcc is applied to the data bus DB and the bar DB through P-channel MOS transistors Tr18 and Tr19.
A precharge voltage VPR of / 2 is supplied. A P channel M is provided between the drains of the transistors Tr18 and Tr19.
The OS transistor Tr20 is connected.

Then, the transistors Tr18 to Tr20 are provided.
The control signal SG3 is input to the gate of the. In the amplitude suppression circuit configured as above, the transistors Tr11 to Tr14 are turned off during standby, and the transistor T11 is turned off.
r17 to Tr20 are turned on. Then, the data bus DB,
The bar DB is precharged to the precharge voltage VPR.

In the read operation, the transistor T
The r11 to Tr12 are turned on, and the data bus DB and the bar DB are supplied with the potential lowered from the power supply Vcc by the threshold value of the transistors Tr11 to Tr12.

Next, the operation of the DRAM configured as described above will be described. During the read operation, when the predecode signals Ga to Gd input to the column decoder become H level and the bit lines BL and BL are selected,
As shown in FIG. 5, the column selection signal CL becomes H level.

Since the write control signal WE is at H level, the column selection signal CLW is maintained at H level. Then, the transistor Trn forming the transfer gate is turned on and the transistor Trp is turned off.

Then, cell information read from the memory cell C selected based on the selection of the word line to the bit lines BL and BL is read to the data bus DB and bar DB via the transistor Trn. It

At this time, when the transistor Trn is turned on based on the rising of the column selection signal CL, the potential of the bit line BL on the high potential side slightly decreases, and the potential of the bit line / bar BL on the low potential side decreases. It rises slightly.

However, since the size of the transistor Trn is formed to be suitable for the cell information reading operation, the potential fluctuations of the bit lines BL and BL are suppressed,
The cell information can be smoothly read into the data bus DB and the bar DB.

When the predecode signals Ga to Gd input to the column decoder become H level during the write operation and the bit lines BL and BL are selected,
As shown in FIG. 6, the column selection signal CL becomes H level.

Since the write control signal WE is at L level, the column selection signal CLW is at L level. Then, the transistors Trn and Trp forming the transfer gate are formed.
Are both turned on.

Then, from the write amplifier to the data bus D
The write data output to B and bar DB is transmitted to the bit lines BL and bar BL at high speed through the transistors Trn and Trp. Further, when the transistor Trp is turned on, the data bus DB and the bar D are transferred from the write amplifier.
The H-level write data output to B, that is, the power supply Vcc level write data is transmitted to the bit lines BL and BL without a voltage drop due to the transfer gate.

Therefore, in this DRAM, the write speed can be improved without decreasing the read speed by substantially changing the transistor size of the transfer gate during the read operation and the write operation.
Then, the writing voltage at the H level can be improved to improve the writing speed.

In the above-mentioned embodiment, P
Although both the channel MOS transistor Trp and the N-channel MOS transistor Trn are turned on, the P-channel MOS transistor having a large size may be turned on during the write operation.

[0058]

As described above in detail, the present invention can provide a semiconductor memory device having a transfer gate that can contribute to the improvement of writing speed and reading speed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an example.

FIG. 3 is a circuit diagram showing a column decoder of one embodiment.

FIG. 4 is a circuit diagram showing an amplitude suppression circuit.

FIG. 5 is a waveform diagram showing a read operation.

FIG. 6 is a waveform diagram showing a write operation.

FIG. 7 is a circuit diagram showing a conventional example.

[Explanation of symbols]

3 column decoder BL, bar BL Bit line BL, bar BL DB, bar DB data bus Trp P-channel MOS transistor Trn N-channel MOS transistor CL, CLW Column selection signal

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-314776 (JP, A) JP-A-6-251580 (JP, A) JP-A 64-19587 (JP, A) JP-A-4-19587 76894 (JP, A) JP-A-6-111575 (JP, A) JP-A-4-172692 (JP, A) JP-A-3-235294 (JP, A) JP-A-7-29368 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/401-11/4099

Claims (4)

(57) [Claims] 1. A transfer gate interposed between a bit line and a data bus is composed of a P-channel MOS transistor and an N-channel MOS transistor connected in parallel,
A column selection signal for turning on only the N-channel MOS transistor during a cell information read operation and for turning on at least the P-channel MOS transistor during a cell information write operation is input from a column decoder to the gates of the respective transistors. Semiconductor memory device. 2. A bit line and a word line are respectively connected to a large number of storage cells, a transfer gate for controlling transfer of read data and write data is interposed between the bit line and the data bus, and the data bus is connected to the data bus. Is a semiconductor memory device connected to an amplitude suppression circuit, wherein the transfer gate is composed of a P-channel MOS transistor and an N-channel MOS transistor connected in parallel,
Only the N-channel MOS transistor is turned on when reading cell information from the memory cell, and at least the P-channel MO transistor is turned on when writing cell information.
A semiconductor memory device characterized in that a column selection signal for turning on an S transistor is inputted from a column decoder to the gates of the respective transistors. 3. The column decoder outputs a first column selection signal, which becomes H level when the column is selected, to the gate of the N-channel MOS transistor, and selects the column based on a write control signal during a write operation. 3. The semiconductor memory device according to claim 1, wherein a second column selection signal which is sometimes at L level is output to the gate of the P-channel MOS transistor. 4. A DRAM memory cell connected to a bit line, and a switch circuit provided between the bit line and a data bus and operating in response to a column selection signal. The switch circuits are connected in parallel. Consists of N-channel MOS transistor and P-channel MOS transistor
And the N-channel MOS transistor during the read operation
Only operable, and at least before before the write operation
The semiconductor memory device comprising a this <br/> whose serial P-channel MOS transistor is operable.