JP3449888B2 - Analog interface liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an analog interface liquid crystal display device which takes in analog input data, converts it into digital data, and displays it.

[0002]

2. Description of the Related Art As described in Japanese Patent Publication No. 2-245793, a conventional analog interface liquid crystal display device converts a liquid crystal panel, an analog interface circuit, and analog data having a plurality of voltage levels into digital data. An analog-digital conversion circuit for conversion, a voltage generation circuit that generates gradation voltages of multiple levels according to gradations, and a gradation voltage is selected based on the display digital data converted by the analog-digital conversion circuit. And a driving means for applying to the liquid crystal panel.

[0003]

The voltage of the analog data input to the analog-to-digital conversion circuit of the analog interface liquid crystal display device varies in black level and amplitude depending on the specifications and temperature characteristics of the analog data supply source circuit. To do. Therefore, the conventional analog interface liquid crystal display device has a problem that the display digital data output from the analog-digital conversion circuit does not properly represent the original image, and the image quality of the display image on the liquid crystal panel deteriorates. .

Therefore, it is an object of the present invention to provide an analog interface liquid crystal display device which, even when inputting analog data having different black levels and amplitudes, converts it into appropriate digital data for display and performs good display. To do.

[0005]

In order to achieve the above object, the present invention provides a matrix type liquid crystal panel having data signal lines and scanning signal lines, analog type display data having a plurality of levels, and an offset level. Signal and
A gain level signal is taken in, the voltage level of the display data is shifted by the voltage level indicated by the offset level signal, and the shifted display data is converted into digital display data with a gain determined by the voltage level of the gain level signal. Analog-to-digital conversion means, X driving means for applying a gradation voltage corresponding to the converted display data value in digital format to the data signal line of the liquid crystal panel, and a selection voltage for the scanning signal line of the liquid crystal panel. Drive means for applying a voltage and one display period for scanning one screen
At every interval, the converted display data in digital format
A minimum value storage means for storing the minimum voltage value, and a predetermined value
Deviation between the initial value of the offset level and the minimum value stored in the minimum value storage means or a value obtained by multiplying the minimum value by a coefficient.
The offset level is determined based on the difference and the offset level
And an offset calculation adjusting means for generating the offset level signal indicating the analog level.

Further, in the above-mentioned analog interface liquid crystal display device, a maximum value storage for storing the maximum value of the voltage of the converted digital-format display data for each display period during which one screen is scanned. Means and current gain level
From the default gain level and the maximum value
Deviation from the maximum value stored in the storage means or the deviation
Determine the gain level by subtracting the value multiplied by the coefficient
An analog interface liquid crystal display device is further provided, which further comprises a gain calculation adjusting means for generating the gain level signal indicating an in-level .

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an analog interface liquid crystal display device according to an embodiment of the present invention. As shown in the figure, the present liquid crystal display device includes a clock generation unit 3, an analog-digital conversion unit 10 (hereinafter, A / D conversion unit 10), a minimum value storage unit 12, a maximum value storage unit 13, and an offset automatic calculation adjustment unit 16. , Gain automatic calculation adjustment unit 1
8, liquid crystal controller 20, gradation voltage generating section 25, X driving means 27, Y driving means 29, and liquid crystal panel 33.
Have.

The clock generator 3 generates a dot clock 5 and a black adjustment timing signal 4 from a vertical synchronizing signal 1 and a horizontal synchronizing signal 2 input from an analog interface (not shown).

The A / D converter 10 digitally converts the analog display data 6 input from the analog interface into a black adjustment timing signal 4, a dot clock 5, an offset level 7, a gain level 8 and a reference low level 9. It is converted into display data 11. Here, the reference low level 9 is a reference voltage on the low level side at the time of A / D conversion. In the present embodiment, the precision of the A / D converter 10 is set to 3 bits, and the digital display data 11
Also has a 3-bit configuration.

The minimum value storage unit 12 fetches the digital display data 11 of each dot in synchronization with the dot clock 5, holds the minimum value in each time, and holds it in synchronization with the vertical synchronization signal 1. This value is output to the automatic offset adjustment unit 16 as the minimum value data 14. The value held in the minimum value storage unit 12 is cleared when the minimum value data 14 is newly output. Therefore, the minimum value storage unit 12 outputs the minimum value of the digital display data 11 within one display period as the minimum value data 14 for each display period. Minimum value storage unit 12
Has a capacity for storing the number of bits of each digital display data of R (red), G (green), and B (blue). In this embodiment, a total of 9 bits (= 3 × 3 bits) are stored. Has capacity.

In this embodiment, the minimum data 14 is output in synchronization with the vertical sync signal 1. But,
It is also possible to output at an arbitrary timing only when performing automatic adjustment. However, the stored value is cleared according to the timing of the vertical synchronizing signal 1.

The offset automatic calculation adjustment unit 16 uses an A / D
The offset level 7 for adjusting the offset in the conversion unit 10 is generated. The offset automatic calculation adjustment unit 16 initially outputs the offset level 7 with a certain initial value. However, the offset adjustment start signal 1
When 7 is input, calculation is performed based on the minimum value data 14 and the offset level 7 is automatically adjusted to the optimum level. This adjustment is performed in synchronization with the vertical sync signal 1. In this embodiment, the offset adjustment start signal 17
Is a pulse signal that becomes “1” at the start of automatic adjustment of the offset level. The configuration and operation of the offset adjusting unit 16 will be described in more detail later. The offset level 7 includes the R offset level 3
7, G offset level 38, B offset level 39
(See FIG. 2).

The maximum value storage unit 13 fetches the digital display data 11 of each dot in synchronization with the dot clock 5, holds the maximum value in each time, and holds it in synchronization with the vertical synchronization signal 1. This value is output to the automatic gain adjustment section 18 as the maximum value data 15. Further, the value stored in the maximum value storage unit 13 is the maximum value data 1
It is cleared when 5 is output. Therefore, from the maximum value storage unit 13, the digital display data 11 within one display period is displayed.
The maximum value of is output as the maximum value data 15 for each display period. The maximum value storage unit 13 has a storage capacity of [bit number of digital display data + overflow bit] for each of R, G, and B. In this embodiment, the total storage capacity is 12 bits (= 4 × 3 bits).

In this case, the maximum value data 15 is output in synchronization with the vertical synchronizing signal 1. However, the output may be performed at an arbitrary timing only when the automatic adjustment is performed. However, the stored value is cleared according to the timing of the vertical synchronizing signal 1.

The automatic gain calculation adjustment section 18 generates a gain level 8 for adjusting the gain in the A / D conversion section 10. This automatic gain calculation adjustment unit 1
8 initially outputs the gain level 8 with a certain initial value.
However, when the gain adjustment start signal 19 is input, calculation is performed based on the maximum value data 15 and the gain level 8 is automatically adjusted to the optimum level. This adjustment is performed in synchronization with the vertical sync signal 1. In the present embodiment, the gain adjustment start signal 19 is a pulse signal that becomes “1” at the start. The configuration and operation of the automatic gain calculation adjustment section 18 will be described in more detail later. The gain level 8 includes an R gain level 46 and a G gain level 4
7 and B gain level 48 (see FIG. 2).

The liquid crystal controller 20 rearranges the pixels of the liquid crystal panel, which will be described later, of the digital display data 11 and outputs the digital display data 11 in synchronization with the latch clock 22.
Horizontal clock 23 that becomes the scanning timing for each line
And a head line signal 24 indicating the head of one display period.

The X driving means 27 outputs the gray scale voltage corresponding to each of the digital display data 11 for one line as panel data 28 in synchronization with the latch clock 22 and the horizontal clock 23. X drive means 27
Sets the digital display data 11 to 1 by the latch clock 22.
Lines are sequentially captured, and one level of the grayscale voltage levels 26 generated by the grayscale voltage generation unit 25 is selected according to the data of each dot. And next horizontal clock 2
In synchronization with 3, the selected grayscale voltage level is output as panel data 28. In the present embodiment, the liquid crystal panel 33
The number of dots in the horizontal direction is set to 640, and the X signal line is 640 ×
3 (1 dot for R, G, and B) = 1920, and the gradation voltage level 26 is 8 levels.

The Y drive means 29 outputs one selection voltage 31 to the scanning signal line 32 sequentially in synchronization with the head line signal 24 and the horizontal clock 23. When the Y drive means 29 takes in the head line signal 24, the first line of the scanning signal line 32 is set to the selection voltage 31, and thereafter, the selection voltage 31 is set in synchronization with the horizontal clock 23.
The second line, the third line, and so on. At this time, all the lines except the selected voltage 31 are set to the non-selected voltage 30. In this embodiment, the number of dots in the vertical direction of the liquid crystal panel 33 is 480, and the number of Y signal lines is 480.

The liquid crystal panel 33 displays data according to the panel data 28 output from the X driving means 27 on the line of the scanning signal line 32 having the selection voltage 31. Further, the liquid crystal panel 33 has R, G, and B color filters, and one pixel is composed of three pixels, and color display is performed by additive color mixing. Therefore, in the present embodiment, the resolution of the liquid crystal panel 33 is 640 × 480,
It is possible to display a total of 512 colors with 8 gradations for each of R, G, and B.

The clock generation unit 3 generates a dot clock 5 based on the vertical synchronization signal 1 and the horizontal synchronization signal 2 input from the analog interface, and each unit (A / D conversion unit 10, liquid crystal controller 20, minimum). It is supplied to the value storage unit 12 and the maximum value storage unit 13). In addition, the black adjustment timing signal 4 is generated, and the black adjustment timing signal 4 is generated.
Output to. The black adjustment timing signal 4 is used for offset adjustment described later.

Here, an outline of the operation of the present liquid crystal display device will be described.

The A / D converter 10 has an offset level 7
According to the above, the black level of the analog display data 6 is adjusted. Then, with the gain level 8 and the reference low level 9 as references, the analog display data 6 is converted into digital display data 11, and this is output to the liquid crystal controller 20. The liquid crystal controller 20 includes an X drive means 27 and a Y drive means.
By controlling the driving means 29, the inputted digital display data 11 is displayed on the liquid crystal panel 33. In this case, the gradation voltage applied to the liquid crystal panel 33 is separately generated by the gradation voltage generator 25.

The gain and offset value of the A / D conversion by the A / D converter 10 must be adjusted according to the input analog display data. Therefore, in the present embodiment, the minimum value storage unit 12 holds the minimum value of the digital display data 11. Then, the offset automatic calculation adjustment unit 16 adjusts the offset level 7 according to the minimum value. Further, the maximum value of the digital display data 11 is held in the maximum value storage unit 13. Then, the automatic gain calculation adjustment unit 18 adjusts the gain level 8 according to the value.

The A / D converter 10 has an offset level 7
And the offset and gain of the A / D conversion are adjusted according to the gain level 8. This automatically keeps the offset and gain optimal.

The offset automatic calculation adjustment unit 16 and the gain automatic calculation adjustment unit 18 are provided at the time of power-on.
Outputting a certain initial level. When the offset adjustment start signal 17 and the gain adjustment start signal 19 are input, the offset level 7 and the gain level 8 are automatically adjusted. The offset adjustment start signal 17 and the gain adjustment start signal 19 may be arbitrarily input, or may be always input when the apparatus is started up.

The A / D conversion section 10, the automatic offset calculation adjustment section 16 and the automatic gain calculation adjustment section 18 involved in the adjustment processing of the offset level and the gain level will be described in detail below.

First, the A / D converter 10 is shown in FIG.
~ It demonstrates using FIG.

The A / D converter 10 converts the input analog display data 6 into digital display data 11. The analog display data 6 includes analog R display data 34, analog G display data 35, and analog B display data 36. The digital display data 11 includes digital R display data 52, digital G display data 53, and digital B display data 54.

In this embodiment, as shown in FIG.
The D conversion unit 10 includes an R black level adjusting means 40, a G black level adjusting means 41, a B black level adjusting means 42, and an R-A / D.
The conversion means 49, the GA / D conversion means 50, and the BA / D conversion means 51 are included.

The R black level adjusting means 40, the G black level adjusting means 41 and the B black level adjusting means 42 adjust the offset of the analog display data 6. The R black level adjusting means 40 adjusts the offset amount (that is, the black level) of the analog R display data 34 according to the R offset level 37. The adjustment is performed at the timing determined according to the black adjustment timing signal 4. The R black level adjustment means 40 outputs the adjusted data to the RA / D conversion means 49 as analog R data 43 for digital conversion. G black level adjusting means 41
Is for adjusting the offset amount (that is, the black level) of the analog G display data 35 according to the G offset level 38. The adjustment is performed at the timing determined according to the black adjustment timing signal 4. The G black level adjusting means 41 outputs the adjusted data to the G / A / D converting means 50 as analog R data 44 for digital conversion. The B black level adjusting means 42 adjusts the offset amount (that is, the black level) of the analog B display data 36 according to the B offset level 39. The adjustment is performed at the timing determined according to the black adjustment timing signal 4. B black level adjusting means 42
Outputs the adjusted data to the R / A / D conversion means 51 as analog B data 45 for digital conversion.

The RA / D converting means 49, the GA / D converting means 50, and the BA / D converting means 51 perform A / D conversion with a separately determined gain. The R-A / D conversion means 49 converts the analog R data 43 for digital conversion into
It is converted into digital R display data 52. This conversion is performed on the basis of the R gain level 46 and the reference low level 9. The G-A / D conversion means 50 is
The analog G data 44 for digital conversion is converted into digital G display data 53. This conversion is performed on the basis of the G gain level 47 and the reference low level 9. The B-A / D conversion means 51 converts the digital conversion analog B data 45 into digital B display data 54.
Is to be converted to. This conversion is for B gain level 4
8 and a reference low level 9 are used as a reference.
These more detailed configurations will be described later with reference to FIG.

The operation of the A / D converter 10 will be described by taking R data as an example.

First, the R black level adjusting section 40 adjusts the offset level. As shown in FIG. 3, the analog R display data 34 has a black level called a pedestal level in a blanking period 55 which is a non-display period. The R black level adjusting means 40 shifts the black level of the analog R display data 34 having this offset amount by the offset amount 57 in the blanking period 55. The offset amount 57 is determined according to the R offset level 37. The R black level adjustment unit 40 outputs the signal after the shift as analog R data 43 for digital conversion. In this way, the R black level adjusting means 40 adjusts the relationship between the reference low level 9 and the digital conversion analog R data 43. The timing signal for this adjustment is the black level adjustment timing signal 4 generated from the horizontal synchronizing signal 2 that generates a pulse in the blanking period 55. The period denoted by reference numeral "56" in FIG. 3 is the display period.

Then, R analog-to-digital conversion means 49
Converts the digital conversion analog R data 43 into digital R display data 52. In this conversion, the R gain level 46 is used as the higher reference voltage. On the other hand, the reference low level 9 is set to the lower reference voltage.

The offset level and gain level adjustment processing itself is performed by the A / D converter 10. However, the A / D conversion unit 10 uses the offset level 7
And only operating according to gain level 8. It is the automatic offset calculation adjustment unit 16 and the gain level adjustment unit 18 that “automatically” perform the adjustment process by appropriately changing the offset level 7 and the gain level 8. Offset automatic calculation adjustment unit 16
The gain level adjusting unit 18 will be described later in detail.

The internal structure of the R-A / D converter 49 is shown in FIG.
Will be explained.

In the present embodiment, the RA / D converter 49 has a resolution of 3 bits, and the RA / D converter 49 includes the first voltage dividing resistor 58 to the seventh voltage dividing resistor 64, and It is composed of a first comparator 73 to an eighth comparator 80 and an 8to3 encoder 89.

The first voltage dividing resistor 58 to the seventh voltage dividing resistor 64 are
By dividing the voltage between the R gain level 46 and the reference low level 9, the first comparison voltage 65 to the eighth comparison voltage 72 are generated. Here, in order to equally divide the voltage between the R gain level 46 and the reference low level 9, the resistance values of the voltage dividing resistors 58 to 64 are all set to be the same.

The first comparator 73 is for comparing the digital conversion analog R data 43 with the first comparison voltage 65. As a result of the comparison, if the input (here, the digital conversion analog R data 43) <the first comparison voltage 65, the first comparator 73 synchronizes “0” as the first comparator output 81 with the dot clock 5. Output. On the contrary, when the input (here, the digital conversion analog R data 43) ≧ the first comparison voltage 65,
The first comparator 73 outputs “1” as the first comparator output 81 in synchronization with the dot clock 5. The second comparator 74 to the eighth comparator 80 are also configured to output the second comparator output 82 to the eighth comparator output 88 by the same operation.

The encoder 89 converts the 8-bit first comparator output 81 to the eighth comparator output 88 into 3-bit digital R display data 52 and outputs it.

In this embodiment, the first comparator output 81 for the digital conversion analog R data 43 is used.
Table 1 shows a truth table of the eighth comparator output 88 and the digital R display display data 52.

[0043]

[Table 1]

The resolution of the A / D converter 10 is not limited to 3 bits. When it is desired to set the resolution to n bits, n comparators and (2n) to (n) encoders may be used.

The G / A / D converters 50 and B shown in FIG.
The internal configuration of the -A / D converter 51 is also the RA described here.
It is similar to the / D converter 49.

The gain adjusting operation by the RA / D converter 49 will be described with reference to FIG.

The first voltage dividing resistor 58 to the seventh voltage dividing resistor 64 are
By dividing the voltage between the R gain level 46 and the reference low level 9, the first comparison voltage 65 to the eighth comparison voltage 72 are generated. First comparator 73 to eighth comparator 80
Respectively compare the digital conversion analog R data 43 with the first comparison voltage 65 to the eighth comparison voltage 72. Then, the comparison result is output as the first comparator output 81 to the eighth comparator output 88. For example, consider a case where sixth comparison voltage ≦ input <fifth comparison voltage. In this case, since input <first comparison voltage, the first comparator output 81
Becomes "0". Input <second comparison voltage, so second
The comparator output 82 becomes "0". Since input <third comparison voltage, the third comparator output 83 becomes "0". Since the input is less than the fourth comparison voltage, the fourth comparator output 84 is "0". Since input <fifth comparison voltage, the fifth comparator output 85 is "0". Since input ≧ sixth comparison voltage, the sixth comparator output 86
Becomes "1". Since input ≧ seventh comparison voltage, the seventh
The comparator output 87 becomes "1". Since input ≧ eighth comparison voltage, the eighth comparator output 88 becomes “1”.

The encoder 89 encodes the 8-bit first comparator output 81 to the eighth comparator output 88 into 3 bits, and outputs this as digital R display data 52.

In this embodiment, since eight comparators are provided, nine levels of conditions can be set. If the input exceeds the higher reference voltage, it will overflow. The encoder encodes the input value into 3 bits because the remaining 8 levels of conditions are represented by binary numbers. When the overflow condition is not necessary, the number of comparators can be reduced by one. In this embodiment, the overflow bit is set to "1" at the time of overflow.

Here, the relationship between the gain level and the offset level and the A / D conversion result will be described with reference to FIGS.

In the following, 1. 1. A / D conversion when both offset level and gain level are optimally set, 2. 2. Effect of offset level on A / D conversion result, The influence of the gain level on the result of A / D conversion will be described. Here, for the sake of simplicity, only the comparator outputs 81 to 88 and the digital R display data 52 will be described as a result of A / D conversion.

1. A / D conversion when both offset level and gain level are optimally set FIG. 5 shows the result of A / D conversion when appropriate offset level and gain level are set (comparator outputs 81 to 88, An example of digital R display data 52) is shown. The sample point 90 of A / D conversion is the timing at which the comparators 73 to 80 compare voltages,
Here, the rising timing of the dot clock 5 is set.

FIG. 5B shows that the first comparator outputs 81 to 8th at each sample point 90.
It is the comparator output 88. FIG. 5C shows the output of the encoder 89 (that is, the value of the digital R display data 52) with respect to the first comparator output 81 to the eighth comparator output 88 of FIG. 5B. The highest brightness "1, 1, 1" to the lowest brightness "0, 0,
It is correctly converted to 0 ". In this case, the overflow bit is" 0 ".

Further, the minimum value 91 "0, 0, 0" is the minimum value data 14 output from the minimum value storage unit 12, and the maximum value 92 "1, 1, 1, 1" is the maximum value storage unit. It is the maximum value data 15 output from 13. In the automatic adjustment of offset and gain, this data becomes the maximum value and the minimum value within one display period.

2. Effect of Offset Level on A / D Conversion Result FIG. 6A shows a digital conversion operation when the offset amount is set higher than that in FIG. 5A. Analog R data 43 for digital conversion in FIG.
Indicates that the R offset level is set higher than that in the example of FIG. 5, and the black level of the analog display data exceeds the reference low level 9 of A / D conversion.

FIG. 6B shows the outputs of the first to eighth comparators at each of the sample points 90 in FIG. 6A. The operation of each comparator is shown in Figure 5.
This is as described in (b). In FIG. 6B, the output is different from that in FIG. 5B at some sample points 90 due to the change in the level of the analog R display data 43. For example, at the first sample point 90, all the comparator outputs are “0” in FIG. 5B, whereas the eighth comparator output is “1” in FIG. 6B. ing.

FIG. 6C shows the first to eighth parts of FIG. 6B.
The encoder output with respect to the comparator output, that is, the value of the digital display data is shown. The operation of the encoder 89 is as described with reference to FIG.

At the sampling points where the comparator outputs are different between FIG. 6B and FIG.
In (c), the digital data has a value different from that in FIG. 5 (c). In particular, the minimum value 91 is “0, 0,
What was 0 ”is now 0, 0, 1”, which means that the black display is slightly brighter because the offset amount is too large. It is necessary to adjust the amount.

3. Effect of Gain Level on A / D Conversion Result First, the case where the gain level is too high will be described with reference to FIG. 7.

In FIG. 7A, the gain level is shown in FIG.
4 shows a digital conversion operation when the value is set higher than that in FIG. The analog R data 43 for digital conversion is
This is similar to the example of FIG. However, the R gain level is set higher than that in the example of FIG. Further, accordingly, the first to eighth comparison voltages in which the R gain level and the reference low level are evenly divided are also different from the example of FIG.

FIG. 7B shows the outputs of the first to eighth comparators at the sample points 90 in FIG. 7A. In FIG. 7B, the operation of each comparator is as described in FIG. 5B.

At some sample points due to the change in the comparison voltage level, FIG.
Output is different from. For example, in the sixth sample point, only the first comparator output is “0” in FIG. 5B, whereas the first and second comparator outputs are “0” in FIG. 7B. Has become.

FIG. 7C shows the output of the encoder 89 with respect to the first comparator output 81 to the eighth comparator output 88 of FIG. 7B, that is, the value of the digital display data. The operation of the encoder 89 is as described with reference to FIG. When compared with FIG. 5, digital data also has different values at sample points where the values of the comparator outputs are different. Especially, the maximum value is 9
2 is "0, 1, 1, 1" in FIG. 5 (c), but is "0, 1, 1, 0" in FIG. 7 (c).
That is, it indicates that the white display is displayed slightly darker. In this case, it is necessary to adjust the gain level. This point serves as a criterion for determining whether the gain level is too high.

The case where the gain level is too low will be described with reference to FIG.

In FIG. 8A, the gain level is shown in FIG.
The digital conversion operation is shown in the case of being set to be lower than that of. The analog R data 43 for digital conversion is the same as in FIG. However, the R gain level is set lower than that in the example of FIG. Accordingly, the R gain level and the reference low level are evenly divided into the first
The eighth comparison voltage is also different from that in FIG.

FIG. 8 (b) shows the outputs of the first to eighth comparators at each sample point 90 in FIG. 8 (a). The operation of each comparator is as described in FIG. Due to the change in the comparison voltage level, the output in FIG. 8B differs from that in FIG. 5B at some sample points. For example,
The sixth sample point is that only the first comparator output is “0” in FIG.
In (b), all comparator outputs are "1".

FIG. 8C shows the output of the encoder 89 with respect to the first comparator output 81 to the eighth comparator output 88 of FIG. 8B, that is, the value of the digital display data. The operation of the encoder 89 is as described with reference to FIG. When compared with FIG. 5, the digital data also has different values at the sample points where the values of the comparator output are different. Especially maximum value 92
However, what is "0, 1, 1, 1" in FIG. 5C is now "1, 1, 1, 1". That is, it is shown that not only the white display but also a slightly dark gray display becomes the white display. In this case as well, the gain level needs to be adjusted. This point serves as a criterion for determining whether the gain level is too low.

Next, the automatic adjustment of the offset level will be described.

First, the structure of the automatic offset calculation adjustment section 16 will be described with reference to FIG. As shown in FIG. 9, the offset automatic calculation adjustment unit 16 includes an offset calculation unit 161.
And an offset generation unit 162.

The offset calculation unit 161 takes in the minimum value data 14 and outputs an offset calculation result output 163 giving an offset level. The offset calculation result output 163 is digital data and takes a predetermined initial value when the power is turned on. The offset calculation unit 161 calculates a more appropriate offset level based on the fetched minimum value data 14 and the offset calculation result output 163 output at that time, and newly calculates the calculation result as the offset calculation result output 163. Output as.

The number of bits of the offset calculation result output 163 can be set arbitrarily, and the higher the number, the better the accuracy of offset adjustment. The offset calculation unit 161 may be realized by hardware or may be realized by executing a predetermined program by a microcomputer.

The offset generator 162 outputs analog data of a level according to the value of the offset calculation result output 163 as the offset level 7. The offset generation unit 162 can be realized by a D / A converter. It can also be realized by a digital potentiometer that divides the reference voltage with a voltage division ratio according to the value of the input data.

The operation of the offset automatic calculation adjustment unit 16 is
This will be described with reference to FIGS. 10 and 11. It should be noted that the level denoted by reference numeral "237" in FIG. 11 is the level of the black display portion of the analog display data.

When the power is turned on, the offset calculator 161
Outputs the initial value of the offset calculation result output (see FIG. 1).
0, step 2500). This initial value is set to a large value so that the minimum value data 14 does not become "0,0,0" during the calculation. Then, the offset generation unit 1
From 62, an offset level 7 of a larger level according to this initial value is output (see FIG. 11).

At least one display period has elapsed since the output of the initial value of the offset calculation result output was started (steps 2500 and 2501 in FIG. 10), and when the offset adjustment start signal 17 became "1", the offset calculation section 161
Subtracts the minimum value data 14 from the initial value of the offset calculation result output (offset value) output at that time (step 2502), and outputs the calculation result in synchronization with the next vertical synchronization signal. It is output as 163. The offset generation unit 162 outputs the offset level 7 of the voltage level according to the calculation result. As a result, the offset level 7 is reduced by the width indicated by reference numeral "238" in FIG. 11 and adjusted to an appropriate level.

According to the calculation of FIG. 10 described above, when the A / D converter 10 and the offset generator 162 have the same conversion characteristic, the offset level 7 can be set to the optimum level in a short period of time.

As shown in FIG. 12, the conversion characteristics of the digital value and the analog value in the analog-digital conversion section 10 (a straight line with the reference numeral “239”) and the conversion of the digital value and the analog value in the offset generation section 162. If the characteristics (straight line with reference numeral “240”) do not match,
The offset calculation unit 161 is provided with the calculation shown in FIG.
By performing the calculation shown in (1), highly accurate offset adjustment is possible.

In the calculation shown in FIG. 13, when the offset adjustment start signal 17 becomes "1" (step 250)
5) The product of the coefficient previously set to a value smaller than 1 and the minimum value data 14 is subtracted from the offset calculation result output currently output, and the subtraction result is newly set as the offset calculation result output (step 2506). Then, the above steps 2505 and 2506 are repeated n times with one display period (step 2508).

In the calculation shown in FIG. 14, the offset adjustment start signal 17 becomes "1" (step 2
511), the result obtained by multiplying the minimum value data 14 by a coefficient previously set to a value smaller than 1 is subtracted from the offset calculation result output that is being output at that time, and the subtraction result is newly set as the offset calculation result output (step). 2512). Then, after waiting for one display period (step 2513), it is determined whether or not the newly input minimum value data 14 is "0, 0, 0" (0 value) (step 2514). The calculation ends. When the minimum value data 14 is not 0, the value of the offset calculation result output is decremented by a constant value (step 2516), and the process returns to step 2513.

It should be noted that the smaller the reduction amount of the offset calculation result output in step 2516, the higher the accuracy of the adjustment becomes. At least [(higher reference voltage of A / D converter 10-lower reference voltage) / (resolution-
1)] is required.

According to the calculations of FIGS. 13 and 14, as shown in FIG. 15, the offset level 7 does not fall significantly below the proper value, and gradually approaches the proper value for each reference one display period. Adjusted. Accordingly, even when the conversion characteristics of the analog-digital conversion unit 10 and the offset generation unit 162 do not match, highly accurate offset adjustment can be performed.

Next, the automatic calculation adjustment of the gain level will be described.

First, the configuration of the automatic gain calculation adjustment section 18 will be described with reference to FIG. As shown in the figure, the automatic gain adjustment section 18 includes a gain calculation section 181 and a gain generation section 182.

The gain calculation unit 181 uses the maximum value data 15
Is output and a gain calculation result output 183 that gives a gain level is output. Gain calculation result output 18
3 is digital data, which has a predetermined initial value when the power is turned on. The gain calculation unit 181 captures the maximum value data 15 and the gain calculation result output 1 at that time.
A more appropriate gain level is calculated based on 83 and the calculation result is newly output as a gain calculation result output 183.

The number of bits of the gain calculation result output 183 can be set arbitrarily, and the higher the number, the higher the accuracy of gain adjustment. The gain calculation unit 181 may be realized by hardware, or may be realized by executing a predetermined program by a microcomputer.

The gain generator 182 outputs analog data of a level according to the value of the gain calculation result output 183 as a gain level 8. The gain generator 182 can be realized by a D / A converter or a digital potentiometer.

The operation of the automatic gain calculation adjustment section 18 is shown in FIG.
This will be described with reference to FIGS. It should be noted that the reference numeral "47" in FIG. 30 is the maximum brightness display analog data that is the maximum value data.

When the power is turned on, the gain calculator 181
The initial value of the gain calculation result output is output (step 2900 in FIG. 17). This initial value is set to a large value so that the maximum value data 15 does not become "1, 1, 1". Then, the gain generation unit 182 outputs the gain level 8 having a larger voltage level according to this initial value (see FIG. 18).

At least one display period has elapsed since the output of the initial value of the gain calculation result output was started (step 290
1) At the time when the offset adjustment start signal 17 becomes "1", the gain calculator 181 starts calculation. In this calculation, first, the fetched maximum value data 15 is subtracted from the value "1, 1, 1" of the maximum value data 15 obtained when the gain level is appropriate. Then, the value obtained by subtracting the subtraction result from the initial value of the gain calculation result output (gain value) output at that time is output as the gain calculation result output 183 in synchronization with the next vertical synchronization signal. (Step 2902). The gain generation unit 182 outputs the gain level 8 of the voltage level according to the calculation result. As a result, the gain level 8 is reduced by the width designated by reference numeral "238" in FIG. 18 and adjusted to an appropriate level.

When the conversion characteristics of the analog-digital conversion unit 10 and the gain generation unit 182 do not match, the automatic gain adjustment unit 18 is caused to perform the calculation shown in FIG. 19 or the calculation shown in FIG. High gain adjustment is possible.

In the calculation shown in FIG. 19, first, the value "1" of the maximum value data obtained when the gain level is appropriate,
The maximum value data 15 taken in is subtracted from 1, 1 ″. Then, from the gain calculation result output (gain value) output at that time, the product of the subtraction result and a coefficient previously set to a value smaller than 1 And outputs the result as a new gain calculation result output 183 (step 290).
6). Then, the above steps 2905 and 2906
Is repeated n times with one display period (step 2905) (step 2908).

Further, in the calculation shown in FIG. 20, first, the fetched maximum value data 15 is subtracted from the value "1, 1, 1" of the maximum value data obtained when the gain level is appropriate. Then, from the gain calculation result output (gain value) output at that time, the product of the subtraction result and a coefficient previously set to a value smaller than 1 is subtracted, and the result is output as a new gain calculation result output 183. (Step 291
2). Then, wait for one display period (step 2
913), the newly acquired maximum value data 15 is “1,
It is determined whether or not it is 1, 1 "(all 1 bits) (step 2914), and if all bits are 1, the operation is ended.
When the maximum value data 15 is not all 1 bits, the value of the gain calculation result output is decreased by a constant value (step 291).
6) Then, the process returns to step 2913.

The smaller the decrease amount of the gain calculation result output in step 2916, the more accurate the adjustment becomes. At least, it must be smaller than [(higher reference voltage of A / D converter 10-lower reference voltage) / (resolution-1)].

According to the calculations in FIGS. 19 and 20, as shown in FIG. 21, the gain level 8 does not drop significantly below the proper value, and gradually approaches the proper value for each display period. Adjusted. Therefore, even when the conversion characteristics of the analog-digital conversion unit 10 and the offset generation unit 162 do not match, highly accurate offset adjustment is possible.

As described above, in the liquid crystal display device of this embodiment, the offset and gain levels are calculated and adjusted on the basis of the maximum value and the minimum value of the digital display data after the analog-digital conversion, so that the optimum value can be obtained. Offset adjustment and gain level adjustment can be performed automatically.
Further, since the maximum value and the minimum value of the digital display data within one display period are used for the calculation, the optimum offset adjustment and gain level adjustment can be performed for the video signal from the personal computer.

[0096]

As described above, according to the present invention, even when analog data having different black levels and amplitudes are input, it is converted into appropriate digital data for display and good display is performed. An analog interface liquid crystal display device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an analog interface liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an analog-digital conversion unit 10.

FIG. 3 is a diagram for explaining offset adjustment of analog display data.

FIG. 4 is a block diagram showing a configuration of an RA / D converter 49.

FIG. 5 shows an example of a case where an offset level and a gain level are appropriately set, (a) shows A / D conversion output, (b) shows comparator output, and (c) shows digital display data.

FIG. 6 is a diagram showing an example when the offset level is large.

FIG. 7 is a diagram showing an example when the gain level is high.

FIG. 8 is a diagram showing an example when the gain level is small.

9 is a block diagram showing a configuration of an offset automatic calculation adjustment unit 16. FIG.

FIG. 10 is a flowchart (1) showing a method of automatic offset adjustment.

FIG. 11 is a diagram (1) showing a timing of automatic offset adjustment.

FIG. 12 is a diagram showing an example of conversion characteristics of the analog-digital conversion unit 10 and the offset generation unit 162.

FIG. 13 is a flowchart (2) showing a method of automatic offset adjustment.

FIG. 14 is a flowchart (3) showing a method of automatic offset adjustment.

FIG. 15 is a diagram (2) showing the timing of automatic offset adjustment.

16 is a block diagram showing a configuration of an automatic gain calculation adjustment section 18. FIG.

FIG. 17 is a flowchart (1) showing a method of automatic gain adjustment.

FIG. 18 is a diagram (1) showing the timing of automatic gain adjustment.

FIG. 19 is a flowchart (2) showing the automatic gain adjustment method.

FIG. 20 is a flowchart (3) showing the automatic gain adjustment method.

FIG. 21 is a diagram (2) showing the timing of automatic gain adjustment.

[Explanation of symbols]

1 ... Vertical sync signal, 2 ... Horizontal sync signal, 3 ... Clock generation unit, 4 ... Black level adjustment timing signal, 5 ... Dot clock, 6 ... Analog display data, 7 ... Offset level, 8 ... Gain level, 9 ... Standard Low level, 10 ... Analog-digital conversion section (A / D conversion section), 11 ... Digital display data, 12 ... Minimum value storage section, 13 ... Minimum value storage section, 14 ... Minimum value data, 15 ... Maximum value data, 16 …
Offset automatic calculation adjustment unit, 17 ... Offset adjustment start signal, 18 ... Gain automatic calculation adjustment unit, 19 ... Gain adjustment start signal, 20 ... Liquid crystal controller, 21 ... Liquid crystal display data, 22 ... Latch clock, 23 ... Horizontal clock, 2
4 ... Leading line signal, 25 ... Gradation voltage generator, 26 ... Gradation voltage level, 27 ... X driving means, 28 ... Panel data, 29 ... Y driving means, 30 ... Non-selection voltage, 31 ... Selection voltage, 32 ... scanning signal line, 33 ... liquid crystal panel, 34 ... analog R display data, 35 ... analog G display data, 3
6 ... Analog B display data, 37 ... R offset level, 38 ... G offset level, 39 ... B offset level, 40 ... R black level adjusting means, 41 ... G black level adjusting means, 42 ... B black level adjusting means, 43 ... analog R data for digital conversion, 44 ... analog G data for digital conversion, 45 ... analog B data for digital conversion, 4
6 ... R gain level, 47 ... G gain level, 48 ... B
Gain level, 49 ... RA / D conversion means, 50 ... G-
A / D conversion means, 51 ... B-A / D conversion means, 52 ... Digital R display data, 53 ... Digital G display data, 5
4 ... Digital B display data, 55 ... Return line period, 56 ... Display period, 57 ... Offset amount, 58 ... First voltage dividing resistance, 5
9 ... 2nd voltage division resistance, 60 ... 3rd voltage division resistance, 61 ... 4th voltage division resistance, 62 ... 5th voltage division resistance, 63 ... 6th voltage division resistance, 6
4 ... 7th voltage division resistance, 65 ... 1st comparison voltage, 66 ... 2nd comparison voltage, 67 ... 3rd comparison voltage, 68 ... 4th comparison voltage, 6
9 ... 5th comparison voltage, 70 ... 6th comparison voltage, 71 ... 7th comparison voltage, 72 ... 8th comparison voltage, 73 ... 1st comparator, 74 ... 2nd comparator, 75 ... 3rd comparator, 76 ... 4th Comparator, 77 ... Fifth comparator, 78 ... Sixth comparator, 79 ... Seventh comparator, 80 ... Eighth comparator, 81 ... First comparator output, 82 ... Second comparator output, 83 ... Third comparator output, 84 ... 4 comparator output, 85 ... 5th
Comparator output, 86 ... Sixth comparator output, 87
... 7th comparator output, 88 ... 8th comparator output, 89 ... 8to3 encoder, 90 ... sample point, 91 ... minimum value, 92 ... maximum value, 161 ... offset calculation unit, 163 ... offset calculation result output, 162 ... offset generation Part, 237 ... Black display analog data, 23
8 ... Offset adjustment amount, 239 ... Offset generation DA
Characteristics, 240 ... Analog-to-digital conversion characteristics, 241 ... Analog data level, 242 ... Offset digital value,
243 ... Analog-to-digital conversion value, 181 ... Gain calculation section, 183 ... Gain calculation result output, 182 ... Gain generation section, 247 ... Maximum brightness display analog data, 248 ... Gain adjustment amount.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI G09G 3/20 642 G09G 3/20 642E (72) Inventor Tsutomu Furuhashi 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. System development In-house (72) Hiroshi Kurihara, 3300 Hayano, Mobara-shi, Chiba, Electronic Devices Division, Nitrate Manufacturing Co., Ltd. (72) Nobutaka Kato, Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Hitachi Systems Co., Ltd. 72) Inventor Masashi Mori, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Hitachi Image Information Systems Co., Ltd. (72) Inventor Yukio Hikita, 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Image Information System, Ltd. (56) References JP-A-8-9193 (JP, A) JP-A-3-231287 ( JP, A) JP 60-247378 (JP, A) JP 56-75775 (JP, A) JP 62-188477 (JP, A) JP 9-83836 (JP, A) JP Flat 2-168296 (JP, A) JP 59-33930 (JP, A) JP 2-146587 (JP, A) Actual development Flat 6-60884 (JP, U) (58) Fields investigated (Int .Cl. ⁷ , DB name) G09G 3/00-3/38 H04N 5/66-5/74 G02F 1/133 505-580

Claims (4)

(57) [Claims] 1. A matrix type liquid crystal panel having a data signal line and a scanning signal line, analog type display data having a plurality of levels, an offset level signal and a gain level signal are taken in, and the voltage of the display data is obtained. An analog-to-digital conversion unit that shifts the level by the voltage level indicated by the offset level signal, and converts the shifted display data into display data in a digital format with a gain determined by the voltage level of the gain level signal; and a data signal of the liquid crystal panel. X driving means for applying a gradation voltage corresponding to the value of the converted digital format display data to the lines, Y driving means for applying a selection voltage to the scanning signal lines of the liquid crystal panel, and one screen portion. The minimum value of the voltage of the converted digital-format display data is measured every one display period of scanning. A minimum value storage means to be stored, an initial value of a predetermined offset level, and the minimum value stored in the minimum value storage means, or the minimum value multiplied by a coefficient.
The offset level based on the deviation from the
An analog interface liquid crystal display device, comprising: an offset calculation adjusting means for generating the offset level signal indicating a set level . 2. The analog interface liquid crystal display device according to claim 1, wherein a maximum value storage for storing the maximum value of the voltage of the converted digital-format display data for each one display period during which one screen is scanned. Means and the current gain level,
Of the period value and the maximum value stored in the maximum value storage means
Deviation or a value obtained by multiplying the deviation by a coefficient is subtracted to obtain the gain level.
An analog interface liquid crystal display device, further comprising: a gain calculation adjusting unit that determines a bell and generates the gain level signal indicating the gain level. 3. The analog interface liquid crystal display device according to claim 1 , wherein the offset calculation adjustment means performs the operation for each display period.
An analog interface liquid crystal display device characterized by performing a calculation and repeating the calculation a plurality of times. 4. The analog interface display device according to claim 2 , wherein the gain calculation adjusting means calculates for each one display period.
An analog interface liquid crystal display device characterized by performing the calculation and repeating the calculation a plurality of times.