JP3448487B2 - Redundancy circuit of semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant circuit of a semiconductor memory device having a redundant program.

[0002]

2. Description of the Related Art In recent years, dynamic RAM (hereinafter referred to as DR
Say AM. In order to reduce the defect rate of bits during mass production, a method of preparing redundant bits in advance and repairing the defective bits is adopted. In this method, when a defective bit is generated, a redundant bit corresponding to the defective bit is programmed in advance, and when the defective bit is accessed, the defective bit is replaced with the corresponding redundant bit to replace the defective bit. To rescue.

Therefore, in order to realize such redundancy, a circuit for programming the redundant bit is required, and the redundant bit is generally programmed by cutting the fuse with a laser beam. Note that such a conventional technique is described in, for example, Japanese Patent Laid-Open No. 5-41096. Hereinafter, a redundant circuit of a conventional semiconductor memory device will be described with reference to the drawings.

FIG. 4 is a circuit diagram showing the structure of a general redundant circuit.

The power supply Vcc is connected to a node N2 via a P-channel type precharge transistor TR. The node N2 is connected to the power supply Vcc via the P-channel type latch transistor TL, and is connected to the gate of the latch transistor TL via the inverter In1.

The node N2 has fuses F1A, F1B, F2A,
F2B ... and N-channel type transistors T1A, T1B, T2
It is grounded through a plurality of series circuits composed of A, T2B, ... The gates of these transistors T1A, T1B, T2A, T2B ... Have column address signals A1x, / A1x, A2x, /
A2x ... (Note that / means inversion, and so on.)
Is entered. To the gate of the precharge transistor TR, an ATD (advertent detector) signal QATD which is detected when the address signal makes a transition and becomes "L" level is inputted.

Next, the operation of the redundant circuit in which the redundant program is not set will be described.

Now, the column address signals A1x, / A1x,
When A2x, / A2x ... Make a transition, the addressant detector signal QATD becomes "L" level, the precharge transistor TR is turned on, and the node N2 is precharged by the power supply Vcc.

The column address signals A1x, / A1
x, A2x, / A2x ... transits (a pair of A1x, / A1x,
Either "H" or "L" is input to A2x, / A2x .... ), The transistors T1A, T1B, T2A, T2B ... Are turned on (a pair of transistors T1A, T1B, T2A, T2B).
One of the ... turns on. ), And ground node N2.
As a result, the node N2 is fixed at "L" level.
Thus, when the node N2 is at "L" level, the gate of the latch transistor TL becomes "H" level, the latch transistor TL is turned off and the node N2 is not charged, and the node N2 is fixed at "L" level. Therefore, the redundant address signal is not applied to the node N2.

Next, the operation of the redundant circuit shown in FIG. 5 in which the redundant program is set will be described.

In FIG. 5, the fuses F1B, F2B ... Are cut off, and the rest of the configuration is similar to that of the redundant circuit shown in FIG.

Now, the column address signals A1x, / A1x,
When the addressant detector signal QATD becomes "L" level when A2x, / A2x ... Make a transition, the precharge transistor TR is turned on to precharge the node N2 by the power supply Vcc.

The column address signals A1x, / A1
x, A2x, / A2x ... transition (A1x, A2x ... to "H")
When the level is input), transistors T1A, T2A
Is turned on to ground the node N2.

The column address signals A1x, / A1x,
A2x, / A2x ... transitions ("H" to / A1x, / A2x ...)
When the level is input), transistors T1B, T2B
.. is turned on, the fuses F1B, F2B ... Are blown, so that the node N2 is not grounded and the node N2 maintains the "H" level.

Then, the latch transistor TL is turned on to charge the node N2. That is, the node N2 is set to "H" by the redundant program set by the fuse.
It becomes the level, and the redundant address signal .phi.RA is applied to the node N2. The redundant address signal .phi.RA applied to the node N2 prohibits access to the defective memory area and accesses the redundant memory area.

When the redundant address signal .phi.RA applied to the node N2 is released, any one of the transistors T1A, T2A ... Connected in series to one of the fuses F1A, F2A. By inputting the "H" level of the column address signal A1x (, A2x ...) To the transistor T1A (, T2A ...) And turning on the node N2, the potential of the node N2 is pulled out.

[0017]

However, the following problems have occurred when the redundant program is set as described above.

That is, for example, as shown in FIG. 6, between the ground potential GND1 of the transistor TA and the ground potential GND2 of the inverter In2 for generating the column address signal Ax, which are connected in series to the fuse FA which is not fuse-cut, are internally connected. When a potential difference due to power supply noise occurs (ground potential GND1 <ground potential GND2), the inverter In2
By inputting the “H” level to the (node n1), the P-channel transistor T that forms the inverter In2
Of the rP and the N-channel type transistor TrN, the N-channel type transistor TrN is turned on and the ground potential GN
The column address signal Ax becomes "L" due to D2, the transistor TA is turned off, and the node N2 is maintained at "H" level. However, the potential of the ground potential GND2 is equal to the ground potential GN.
Since it is larger than the potential of D1, the transistor TA is turned on, the through current Is flows, the node N2 is changed to the “L” level, and the redundancy determination state (use of the redundant line) is released. Is.

The inventor has found that the internal power supply noise is generated by input signals such as a chip select input signal (CE), a write enable input signal (WE) and an output enable input signal (OE) other than the address signal. It was found that it was due to.

Therefore, an object of the present invention is to provide a redundant circuit of a semiconductor memory device which enables reliable precharge and high-speed extraction of a node potential when redundancy is used.

[0021]

Therefore, according to the present invention of claim 1, a P-channel type precharge transistor is connected between the power supply Vcc and the node N2, and the node N2 is connected.
A fuse F1A (, F1B, F2A, F2B ...) and an N-channel type transistor T1A (, T1B, T2A, T2B) between 2 and ground.
,) And a column address A1x (, / A1x, A2x, / A2x ...) Is supplied to the gates of the N-channel type transistors T1A (, T1B, T2A, T2B ...) And the node. In a redundant circuit of a semiconductor memory device in which a redundant address signal .phi.RA is output from N2, a first precharge transistor TR1 to which a gate is supplied with an adductant detector signal QATB and a column address strobe to a gate. A second precharge transistor TR2 to which a pulse signal QATS generated from a signal (/ CAS) is input, and the first and second precharge transistors TR
1 and TR2 are connected in parallel to the node N2, and when there is no address transition, the node Q2 is held at "H" level by precharging by the signal QATS generated from / CAS. To do.

According to a second aspect of the present invention, in the redundant circuit of the present invention, the first precharge transistor TR1 to which the advertent detector signal QATB having a predetermined pulse width is input to the gate, and the advertent detector signal to the gate. A column address strobe signal (/ C having a pulse width shorter than that of QATB
AS) and a second precharge transistor TR2 to which a pulse signal QATS generated from the
And second precharge transistors TR1 and TR2 are connected in parallel to the node N2. When there is no address transition, precharge is performed by a pulse signal QATS generated from / CAS. The operation of the precharge transistor TR2 is performed by holding N2 at "H" and making the pulse width of the pulse signal QATS generated from the / CAS shorter than the pulse width of the adsorbent detector signal QATB. By releasing the potential faster than the above, the potential of the node N2 potential can be rapidly extracted.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of a redundant circuit of a semiconductor memory device of the present invention will be described below with reference to the drawings. 1 and 2 are diagrams showing a circuit configuration of a redundant circuit of the semiconductor memory device of the present invention, and FIG. 2 shows an example of redundant setting. The same components as those of the conventional configuration are designated by the same reference numerals and the description thereof will be omitted.

The feature of the first embodiment of the present invention is that the first precharge transistor for performing precharge by the fall of the addressant detector signal QATB according to the transition of the address (ADD) as shown in FIG. In addition to TR1, when the address (ADD) does not transit (select the same address), the pulse signal QATS generated from / CAS falls in response to the rising edge of the column address strobe signal (/ CAS) to precharge. That is, the second precharge transistor TR2 is provided.

As a result, when the same address is selected in the conventional redundant program setting, for example, as shown in FIG. 6, the ground potential GND1 and the column address of the transistor TA connected in series to the fuse FA which is not fuse cut and the column address. When a potential difference is generated between the ground potential GND2 of the inverter In2 which generates the signal Ax due to internal power supply noise, the transistor TA is turned on and the through current Is.
This suppresses a problem that the node N2, which originally should maintain the "H" level, changes to the "L" level.

FIG. 1 is a circuit diagram showing a redundant circuit of the semiconductor memory device of the present invention.

The power supply Vcc is connected to the node N2 through the P-channel type first precharge transistor TR1 and the second precharge transistor TR2, and the gate of the first precharge transistor TR1 has an address transition. In response to this, the advertent detector signal QATB having a predetermined pulse width is input, and the gate of the second precharge transistor TR2 is generated from / CAS in response to the rising edge of the column address strobe signal (/ CAS) which is the external synchronization clock. Pulse signal QA
TS is input. The node N2 is connected to the power supply Vcc via the P-channel latch transistor TL, and also connected to the gate of the latch transistor TL via the inverter In1.

The node N2 has fuses F1A, F1B, F2A,
F2B ... and N-channel type transistors T1A, T1B, T2
It is grounded through a series circuit composed of A, T2B, ... The column address signals A1x, / A1x, A2x, / A2x ... Are supplied to the gates of these transistors T1A, T1B, T2A, T2B.
Is entered.

In the operation of the redundant circuit of the semiconductor memory device of the present invention configured as described above, the address (ADD) transitions and the addressant detector signal QATB becomes "L" level as described above. The precharge transistor TR1 of is turned on to precharge the node N2 by the power supply Vcc, and the pulse signal QATS generated from / CAS becomes "L" level in response to the rise of the column address strobe signal (/ CAS). The second precharge transistor TR2 is turned on to turn on the power supply Vc.
The operation is the same as the operation of the redundant circuit of the conventional semiconductor memory device described above except that the node N2 is precharged by c, and the description thereof is omitted to avoid duplication.

A second embodiment of the redundant circuit of the semiconductor memory device of the present invention will be described below with reference to FIG.
3 is a diagram showing an example of the operation timing of the redundant circuit of the semiconductor memory device of the present invention.

The feature of the second embodiment of the present invention is that the redundancy circuit configuration of the semiconductor memory device of the above-mentioned first embodiment is adopted, as shown in FIG.
It is to suppress a new problem in the case where the timing when D) transitions and the address detector signal QATB falls and the timing when the column address strobe signal / CAS falls overlap.

That is, as shown in FIG. 3, when the advertent detector signal QATB and the pulse signal QATS overlap, precharge is performed by both the first precharge transistor TR1 and the second precharge transistor TR2. Therefore, the precharge capacity becomes higher than necessary, and the column address signal A
The transition of x and / Ax slows down the extraction of the potential of the node N2.

Therefore, in the second embodiment of the present invention, the redundancy circuit of the semiconductor memory device can be speeded up.

A feature of the second embodiment of the present invention is that the pulse signal QATS having a pulse width shorter than the pulse width of the above-mentioned advertent detector signal QATB is supplied to the second precharge transistor TR2 as shown by a dotted line in FIG. The configuration is to input to.

As a result, as shown in FIG. 3, at the beginning of precharge, both the first precharge transistor TR1 and the second precharge transistor TR2 perform precharge, but the second precharge is performed at a predetermined timing. Since the precharge by the transistor TR2 is released and the precharge is performed only by the first precharge transistor TR1, as shown by the dotted line in FIG. 3, as compared with the first embodiment (see the solid line in FIG. 3), the node N2 It is possible to extract the electric potential at high speed.

The pulse signal QA generated from the column address strobe signal (/ CAS) shorter than the pulse width of the address restaurant detector signal QATB.
The pulse width of TS is the column address strobe signal (/
(CAS) rise period of charge / discharge current noise at the time of internal reset, that is, redundancy determination state (use of redundant line)
However, in the second embodiment, the pulse width of the above-mentioned advertent detector signal QATB (the pulse signal QATS generated from / CAS of the first embodiment) is approximately determined in the second embodiment. It is set to about half.

[0037]

According to the present invention, in a redundant circuit in which a redundant program is set, address transition can be performed by selecting the same address in addition to the first precharge transistor that starts precharge in response to address transition. Column address strobe signal (/ CAS) to prevent reset of redundancy judgment status (use of redundant line) due to internal power supply noise (charge / discharge current noise at internal reset)
By providing the second precharge transistor which starts the precharge in response to the rising edge of, the reliable precharge can be performed and the malfunction of the redundant circuit can be suppressed.

Further, the pulse width of the pulse signal QATS generated from / CAS input to the second precharge transistor is changed to the advertent detector signal QAT.
By setting it shorter than the pulse width of B, the operation of the second precharge transistor is released faster than the operation time of the first precharge transistor, the capacity of the precharge transistor can be reduced, and the potential of the node can be increased. The semiconductor memory device can be pulled out and the speed of the semiconductor memory device can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a redundant circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a redundant circuit with a redundant address set.

FIG. 3 is a diagram showing an operation timing of a redundant circuit of the semiconductor memory device.

FIG. 4 is a circuit diagram of a redundant circuit of a conventional semiconductor memory device.

FIG. 5 is a circuit diagram of a redundant circuit with a redundant address set.

FIG. 6 is a diagram for explaining a problem of a redundant circuit of a conventional semiconductor memory device.

[Explanation of symbols]

TR1, TR2 ... First and second precharge transistors F1A, F1B, F2A, F2B ... Fuse T1A, T1B, T2A, T2B ... Redundant transistors In1, In2 ... Inverter Vcc ... Power supply N2 ... node

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-41096 (JP, A) JP-A-6-111597 (JP, A) JP-A-9-198892 (JP, A) JP-A-5- 12898 (JP, A) JP 63-222397 (JP, A) JP 11-306789 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 29/00

Claims (2)

(57) [Claims] 1. A P-channel type precharge transistor is connected between a power source and a node, and a plurality of series circuits each including a fuse and an N-channel type transistor are connected between the node and ground, and the N-channel type. In a redundant circuit of a semiconductor memory device in which a column address is supplied to a gate of a transistor and a redundant address signal is output from the node, an advertent detector signal (QATB) having a predetermined pulse width is input to the gate. And a second precharge transistor having a gate to which a pulse signal (QATS) generated from a column address strobe signal (/ CAS) is input, wherein the first and second precharge transistors are A semiconductor characterized by being connected in parallel to the node Redundant circuit of memory device. 2. A P-channel type precharge transistor is connected between a power supply and a node, and a plurality of series circuits each including a fuse and an N-channel type transistor are connected between the node and ground, and the N-channel type. In a redundant circuit of a semiconductor memory device in which a column address is supplied to a gate of a transistor and a redundant address signal is output from the node, an advertent detector signal (QATB) having a predetermined pulse width is input to the gate. The pre-charge transistor and the gate of the advertent detector signal (QA
A second precharge transistor to which a pulse signal (QATS) generated from a column address strobe signal (/ CAS) having a pulse width shorter than the pulse width of TB) is input. A redundancy circuit for a semiconductor memory device, comprising a precharge transistor connected in parallel to the node.