JP3446358B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is a complete CMOS type S.
The present invention relates to a semiconductor memory device called a RAM.

[0002]

2. Description of the Related Art FIG. 3 shows an equivalent circuit of a memory cell of a complete CMOS type SRAM. The flip-flop 11 of this memory cell is a pair of inverters 1 which are connected to each other.
2 and 13, and these inverters 12,
Reference numeral 13 is composed of driving NMOS transistors 14 and 15 and load PMOS transistors 16 and 17. Then, the flip-flop 11 and the transfer NM
A memory cell is composed of the OS transistors 21 and 22.

A ground line 23 is connected to the sources of the NMOS transistors 14 and 15, and a power supply line 24 is connected to the sources of the PMOS transistors 16 and 17. In addition, the word line 25 is the NMOS transistor 21,
It serves as a gate electrode of 22, and true complementary bit lines 26 and 27 are connected to one source and drain of each of the NMOS transistors 21 and 22.

FIG. 4 shows a first conventional example of a memory cell of a complete CMOS type SRAM. In this first conventional example,
A P well (not shown) and an N well (not shown) are formed in a Si substrate or the like which is a semiconductor substrate, and element active regions 30a to 30e are formed in each well. The gate electrodes of the inverters 12 and 13 are formed by the polycide layers 31a and 31b, which are the first conductive layers on the Si substrate, and the word line 25 is formed from the polycide layer 31c.
Are formed.

In the element active regions 30a to 30e on both sides of the polycide layers 31a to 31c, the NMOS transistor 1 is formed.
N-type diffusion layers 32a to 32g serving as source / drain of 4, 15, 21, 22 and P-type diffusion layers 32h to 32k serving as source / drain of PMOS transistors 16 and 17 are formed. ing. Polycide layer 3
1a is connected to the diffusion layers 32f, 32d and 32k via the buried contacts 33a to 33c, and the polycide layer 31b is connected to the diffusion layers 32b and 32i via the buried contacts 33d and 33e.

Al which is the second conductive layer on the Si substrate
The ground line 23 and the power supply line 24 are formed by the films 34a and 34b, and the diffusion layers 32e and 34e are formed by the Al films 34c and 34d.
Wirings extending from above 32g to above the polycide layer 31c are formed. The Al film 34a has contact holes 35a-35.
is connected to the diffusion layers 32a and 32c via
The film 34b is connected to the diffusion layers 32h and 32j via the contact holes 35d and 35e. In addition, the Al film 34c,
34d is connected to the diffusion layer 32e and the diffusion layer 32g through the contact holes 35f and 35g, respectively.

Al which is the third conductive layer on the Si substrate
Bit lines 26 and 27 are formed by the films 36a and 36b, and these Al films 36a and 36b are formed by the polycide layer 3.
A contact hole 37a on the word line 25 composed of 1c, etc.,
It is connected to the Al films 34c and 34d via 37b.

FIG. 5 shows a second conventional example of a memory cell of a complete CMOS type SRAM. In this second conventional example,
A P well (not shown) and an N well (not shown) are formed in a Si substrate or the like which is a semiconductor substrate, and element active regions 30f and 30g are formed in each well. The gate electrodes of the inverters 12 and 13 are formed by the polycide layers 31a and 31b, which are the first conductive layers on the Si substrate, and the pair of word lines for a single memory cell are formed by the polycide layers 31c and 31d. 25 are formed.

In the device active regions 30f and 30g on both sides of the polycide layers 31a to 31d, the NMOS transistor 1 is formed.
N-type diffusion layers 32a, 32b, 32d, 32e, 32g serving as source / drain of 4, 15, 21, 22
And P-type diffusion layers 32h, 32i and 32k serving as the sources and drains of the PMOS transistors 16 and 17, respectively.

The polycide layers 31a and 31 are formed by the polycrystalline Si films 41a and 41b which are the second conductive layer on the Si substrate.
The wiring that extends over b is formed, and the polycrystalline Si film 41c,
Wirings extending along the polycide layers 31c and 31d are formed at 41d. The polycrystalline Si film 41a is provided with diffusion layers 32b, 32 via contact holes 42a-42c, respectively.
i and the polycide layer 31b.

Further, the polycrystalline Si film 41b is connected to the diffusion layers 32d and 32k and the polycide layer 31a via contact holes 42d to 42f, respectively. Furthermore, polycrystalline S
i films 41c and 41d have contact holes 35f and 35g, respectively.
Is connected to the diffusion layer 32e and the diffusion layer 32g via.

Al which is the third conductive layer on the Si substrate
The ground line 23, the power supply line 24, and the bit lines 26 and 27 are formed by the films 34a, 34b, 34e, and 34f. A
I films 34a and 34b have contact holes 35a and 35d, respectively.
And the Al films 34e and 34f are connected to the polycrystalline Si films 41c and 41d via the contact holes 43a and 43b, respectively.

[0013]

However, first, referring to FIG.
In the first conventional example shown in FIG. 3, since the polycide layers 31a and 31b that are the gate electrodes of the inverters 12 and 13 extend in the direction orthogonal to the polycide layer 31c that is the word line 25, the shape of the memory cell is the word line. 25 in the extending direction. Therefore, the pitch of the bit lines 26 and 27 extending in the direction orthogonal to the word line 25 cannot be widened, and the Al films 36a and 36b of the bit lines 26 and 27 cannot be widened.
Therefore, electromigration and stress migration easily occur, and it is difficult to improve the reliability of the bit lines 26 and 27.

Further, as is clear from FIG. 4, the diffusion layer 3
Element active region 30 in which any of 2a to 32k is formed
The a to 30e also have complicated shapes, and therefore the transistors 14 to 17, 21, and 22 also have complicated shapes. Therefore, it is difficult to obtain a stable data holding operation due to a large variation in characteristics due to misalignment during manufacturing, and it is also difficult to secure the withstand voltage between the element active regions 30a to 30e, which is also disadvantageous to miniaturization. there were.

On the other hand, in the second conventional example shown in FIG. 5, in order to interconnect the inverters 12 and 13, the polycrystalline S
The i-films 41a and 41b are required, and the contact holes 42c and 42f for the polycrystalline Si films 41a and 41b are formed in the NMOS transistors 14, 15, 21, 22 and the PMO.
It is necessary on the isolation region from the S transistors 16 and 17. Therefore, the number of manufacturing steps is increased by the amount of the polycrystalline Si films 41a and 41b and the cost is high, and it is difficult to narrow the width of the isolation region, which is also disadvantageous in miniaturization.

[0016]

According to another aspect of the semiconductor memory device of the present invention, a memory cell is formed by using a flip-flop 11 including a pair of inverters 12 and 13, and the memory cell is formed on a semiconductor substrate. In a semiconductor memory device in which the inverters 12 and 13 are composed of the first conductivity type channel transistors 14 and 15 and the second conductivity type channel transistors 16 and 17, a pair of word lines 31c and 31d extending in parallel with each other is a single. An element used for the memory cell and separated from each other by an element isolation region for each pair of the first conductivity type channel transistors 14 and 15 and the second conductivity type channel transistors 16 and 17. Active regions 30a to 30d are provided, and the four element active regions 30a to 30d are provided.
Are sequentially arranged between the pair of word lines 31c, 31d in the extending direction of the word lines 31c, 31d, and each of the word lines 31c, 31d is arranged.
The pair of inverters extend in a direction orthogonal to d.
The gate electrodes 31a and 31b of 12 and 13 are
Extending in the extending direction of the lead wires 31c and 31d, the pair of wires
The inverters 12 and 13 are connected to each other .

According to another aspect of the semiconductor memory device of the present invention, the gate electrodes 31a and 31 of the pair of inverters 12 and 13 are provided.
It is characterized in that b extends parallel to the word lines 31c and 31d.

[0018]

According to the semiconductor memory device of the present invention, the four transistors 14 forming the pair of inverters 12 and 13 are provided.
Element active regions 30a to 30d are separated from each other in the element isolation region and are sequentially arranged between the pair of word lines 31c and 31d in the extending direction of the word lines 31c and 31d. Since the element active regions 30a to 30d are arranged in the direction orthogonal to the word lines 31c and 31d, the gate electrodes 31a and 31b of the inverters 12 and 13 are directly connected to the word line 31.
By extending the c and 31d in the extending direction, the pair of inverters 12 and 13 can be connected to each other, and a dedicated wiring for interconnection and a contact portion for this wiring are unnecessary.

Further, a pair of word lines 31c and 31d are used for a single memory cell, and separate element active regions 30a to 30d are provided for each of the four transistors 14 to 17. The word line 31
The element active regions 30a to 30d can be easily arranged with respect to c and 31d, and the other element active regions 30a to 3d can be arranged.
Since the degree of freedom of the positions of the element active regions 30a to 30d with respect to the position of 0d is large, the element active regions 30a to 30d
The shape of d and thus the shapes of the transistors 14 to 17 can be made simple.

According to another aspect of the semiconductor memory device of the present invention, the gate electrodes 31a and 31b of the pair of inverters 12 and 13 are provided.
Are parallel to the word lines 31c and 31d, the shape of the memory cell can be elongated in the extending direction of the word lines 31c and 31d.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. Also in this embodiment, the equivalent circuit of the memory cell is as shown in FIG.
The point that a P well (not shown) and an N well (not shown) are formed on the i substrate or the like is also similar to the above-mentioned first and second conventional examples.

However, in this embodiment, the element active regions 30a to 30d isolated from each other by the element isolation region are formed for each of the NMOS transistors 14 and 15 and the PMOS transistors 16 and 17. The element active regions 30a to 30d extend in parallel with each other and are substantially aligned in the direction orthogonal to the extending direction.

The polycide layers 31a to 31d, which are the first conductive layers on the Si substrate, are connected to the device active regions 30a to 30.
They extend substantially parallel to each other in a direction orthogonal to the extending direction of d. The gate electrodes of the inverters 12 and 13 are formed of the polycide layers 31a and 31b, and the polycide layers 31 on both sides of the polycide layers 31a and 31b are formed.
A pair of word lines 25 for a single memory cell is formed by c and 31d.

The polycide layers 31a to 31d are tungsten polycide layers or the like, and the polycide layers 31a and 31d.
The portion of NMOS transistors 14 and 15 and the polycide layers 31c and 31d of Nb are N ⁺ type, and the PMOS transistor 1 of the polycide layers 31a and 31b.
Parts 6 and 17 are P ⁺ type.

In the device active regions 30a to 30d on both sides of the polycide layers 31a to 31d, the NMOS transistor 1 is formed.
N-type diffusion layers 32a to 32e and 32g serving as source / drain of 4, 15, 21, and 22 and P serving as source / drain of PMOS transistors 16 and 17.
Type diffusion layers 32h to 32k are formed. The polycide layer 31a is connected to the diffusion layers 32d and 32k via the buried contacts 33b and 33c, and the polycide layer 31b is connected to the diffusion layers 32b and 32i via the buried contacts 33d and 33e.

Al which is the second conductive layer on the Si substrate
The power line 24 is formed of the film 34b, and the Al film 34
c, 34d, and 34g, wiring extending from the diffusion layer 32e along the polycide layer 31c and wiring located on the diffusion layer 32g and diffusion layers 32a and 32c to the polycide layer 31.
A wiring extending along d is formed.

The Al film 34g has contact holes 35a, 35.
b to the diffusion layers 32a and 32c via
The film 34b is connected to the diffusion layers 32h and 32j via the contact holes 35d and 35e. In addition, the Al film 34c,
34d is connected to the diffusion layer 32e and the diffusion layer 32g through the contact holes 35f and 35g, respectively.

Al which is the third conductive layer on the Si substrate
The films 36a to 36c include bit lines 26 and 27 and a ground line 23.
And are formed. The Al films 36a and 36b are connected to the Al films 34c and 34d through the contact holes 37a and 37b, and the Al film 36c is connected to the Al film 34g through the contact hole 37c.

Although FIG. 1 shows only a single memory cell, if the pattern of this single memory cell is represented by the symbol'F ', the pattern of the entire memory cell array is sequentially developed according to the rule shown in FIG. By doing so, the element isolation region and the contact hole can be easily formed.

In the above embodiment, in a single memory cell, the word line 25 is different from that of the first conventional example shown in FIG.
Is increased by one, and the number of element active regions is doubled as compared with the second conventional example shown in FIG. However, as is clear from the comparison between FIG. 1 and FIGS. 4 and 5, the configuration is so simple that the increment of the memory cell area is within 10%. Moreover, since the memory cells are widened in the extending direction of the word lines 25, the pitch of the bit lines 26, 27, etc. can be widened, and the reliability of the bit lines 26, 27, etc. can be improved.

In the above embodiment, the conductive layer is 1
Since the polycide layer of two layers and the Al film of two layers are used,
Highly compatible manufacturing process with semiconductor devices such as ASIC.
It is possible to easily realize a semiconductor device in which a RAM and an ASIC are mounted together.

In the above embodiment, the inverter 1
Polycide layers 31a and 31 which are gate electrodes of 2 and 13
The part of NMOS transistors 14 and 15 is
Set to ⁺ type, and replace the PMOS transistors 16 and 17 with P
^Although the polycide layers 31a and 31b are of the ⁺ type, the entire polycide layers 31a and 31b are of the N ⁺ type, and the N type diffusion layers 32d and 32b and the P type diffusion layers 32k and 32i and the polycide layers 31a and 31b.
And the polycide layers 31a and 31b may be connected via a polycrystalline Si film or the like as an upper layer.

[0033]

In the semiconductor memory device according to the first aspect of the present invention, since a dedicated wiring for connecting a pair of inverters to each other and a contact portion for this wiring are unnecessary, the manufacturing process is simple and the cost is low. It is also advantageous for miniaturization. In addition, since the shape of the element active region and thus the shape of the transistor can be made simple, it is possible to obtain stable data retention operation with little change in characteristics due to misalignment during manufacturing. It is easy to ensure the withstand voltage between them, which is also advantageous for miniaturization.

According to another aspect of the semiconductor memory device of the present invention, since the shape of the memory cell can be elongated in the extending direction of the word line, the pitch of the bit lines extending in the direction orthogonal to the word line is wide. Therefore, the reliability of the bit line and the like can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a single memory cell according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a method of developing a pattern of a memory cell array.

FIG. 3 is a complete CMOS SRA to which the present invention can be applied.
It is an equivalent circuit diagram of the memory cell of M.

FIG. 4 is a plan view of a single memory cell in a first conventional example of the present invention.

FIG. 5 is a plan view of a single memory cell in a second conventional example of the present invention.

[Explanation of symbols]

11 flip-flops 12 inverter 13 Inverter 14 NMOS transistor 15 NMOS transistor 16 PMOS transistor 17 PMOS transistor 30a element active region 30b element active region 30c element active region 30d element active region 31a Polycide layer 31b Polycide layer 31c polycide layer 31d polycide layer

Claims (2)

(57) [Claims] 1. A memory cell is formed by using a flip-flop formed by a pair of inverters, and the inverter is formed by a first conductivity type channel transistor and a second conductivity type channel transistor formed on a semiconductor substrate. In a configured semiconductor memory device, a pair of word lines extending parallel to each other are used for a single memory cell, and a pair of the first conductivity type channel transistor and the second conductivity type channel transistor are provided. Element active regions that are isolated from each other by an element isolation region, and the four element active regions are arranged between the pair of word lines in the extending direction of these word lines . are arranged side by side sequentially extends and the direction in which each orthogonal to the word lines, each of said pair of inverters The word gate electrode of
The pair of inverters are connected to each other by extending in the extending direction of the wire.
A semiconductor memory device characterized by being connected . 2. The semiconductor memory device according to claim 1, wherein a gate electrode of each of the pair of inverters extends parallel to the word line.