JP3445705B2 - Image signal format, image signal format conversion method, and apparatus therefor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal format and conversion technique for image signals, and more particularly to a signal format and conversion technique for television signals.

[0002]

2. Description of the Related Art In recent years, due to the demand for high image quality, the scanning method is shifting from the interlaced method to the progressive scanning method. As a typical progressive scanning type digital interface, a luminance signal of a 525 progressive scanning (hereinafter referred to as 525p) analog signal is sampled at a frequency of 27 MHz,
Color difference signals are sampled at 13.5 MHz 4: 2:
The luminance signal of the 2p system and the 525 progressive scanning analog signal is sampled at a frequency of 27 MHz, and the color difference signal is 6.7.
A 4: 2: 0p method in which sampling is performed at 5 MHz is known.

The above-mentioned 4: 2: 2p method and 4: 2: 0p method
The method has 480 effective scanning lines and 7 effective horizontal images.
It has 20 pixels, and its aspect ratio is 16: 9.
On the other hand, with the recent rise of computers, the number of cases where images are also processed by computers has increased. By the way, since the image data has a huge amount of data, it is usually compression-encoded when the image is digitized and transmitted or recorded on a recording medium such as a CD-ROM or a hard disk.

In the compression encoding system, DCT is used to perform compression by utilizing the property that the spatial frequency of an image is concentrated in a low frequency.
A coding system based on is used relatively often. This is JPEG (Joint Photographic Experts Gro
up) and MPEG (Moving Picture Experts Group). Figure 4
(A) to (f) are hierarchical diagrams of MPEG-compliant code formats. The MPEG code has several hierarchical structures as shown in FIG. The highest layer is the video sequence shown in FIG. 4A, which is composed of a plurality of GOPs (Group Of Pictures).

As shown in FIG. 4B, the GOP is composed of a plurality of pictures. Then, one picture shows one image. There are three types of pictures: an I-picture, which is an intra-frame code, a P-picture, which is an inter-frame code only in the forward direction, and a B-picture, which is an inter-frame code between the front and back. The picture is composed of a plurality of slices divided into arbitrary areas as shown in FIG. A slice is composed of a plurality of macroblocks arranged in order from left to right or from top to bottom.

As shown in FIG. 4 (e), the macroblock is a luminance component (Y1, Y2, Y3, Y4) obtained by further dividing a block of 16 × 16 dots into blocks of 8 × 8 dots.
And six blocks of color difference components (Cb, Cr) of a block of 8 × 8 dots in a region matching the luminance component. Therefore, it is premised that the picture is divided into blocks of 16 × 16 dots.

[0007]

By the way, as described above, in the 4: 2: 2p system and the 4: 2: 0p system, the number of effective scanning lines is 480, the number of effective horizontal images is 720 pixels, and the aspect ratio thereof is Is 16: 9. Therefore, the shape of each pixel is not square (square), and the image signals of the 4: 2: 2p system and the 4: 2: 0p system cannot be easily image processed by a computer. This is because when a computer processes an image, for example, when an image is rotated on the screen, the rotated image will have a different shape from the original image unless the shape of each pixel is square.

Therefore, an object of the present invention is to provide an image signal which can be easily image-processed by a computer and can be easily data-compressed, particularly a signal format of a television signal, and a conventional technique for converting an image signal into the image signal. To provide.

[0009]

[0010]

SUMMARY OF THE INVENTION The object of the present invention is to
Image with 16: 9 image ratio and 720 horizontal effective pixels
A signal format of an image signal, wherein the image signal
6 times the sampling frequency of luminance data
Generating a clock signal having
Zero data is inserted in the luminance data based on the
-Pass-filtering the clock signal
Dividing step by 5 and dividing by the dividing step
Zero data is inserted based on the generated clock signal.
And the step of decimating the luminance data is performed.

Aspect ratio 16: 9, number of horizontal effective pixels
Is 720, the number of effective horizontal pixels can be changed to 864 by simply converting the sampling rate of the luminance data to 6/5 times. Incidentally, normally,
The number of effective horizontal pixels matches the number of horizontal samplings of luminance data, but does not match the number of horizontal samplings of color difference data. Therefore, in the present invention, the minimum number of horizontal samplings of luminance data is 864, and the number of horizontal samplings of color difference data is generally set to 864 / integer. The most common value is 864/2.

An object of the present invention is to have an aspect ratio of 16:
9. A device for converting the format of an image signal having 720 horizontal effective pixels, the device comprising:
Has a frequency that is 6 times the sampling frequency of luminance data
Means for generating a clock signal, and a means for generating the clock signal
Then insert zero data into the luminance data and
A means for multiplying the clock signal and a portion for dividing the clock signal by 5.
Frequency dividing means and a clock signal divided by the frequency dividing means.
Then, the luminance data with zero data inserted is thinned out.
It is accomplished by the format converter of the image signal; and a that means.

Another object of the present invention is a device for converting the format of an image signal of 4: 2: 2p or 4: 2: 0p system, which is an image of 4: 2: 2p or 4: 2: 0p system. Means for generating a first clock signal having a frequency that is six times the sampling frequency of the luminance data in the signal;
Zero data is inserted into the luminance data based on the first clock signal, a means for low-pass filtering, a first frequency dividing means for dividing the first clock signal by 5, and the first frequency dividing Means for thinning out the luminance data in which zero data is inserted based on the clock signal divided by the means, and a frequency which is 6 times the sampling frequency of the color difference data in the 4: 2: 2p method or the 4: 2: 0p method. Means for generating a second clock signal having, and inserting zero data into the color difference data based on the second clock signal,
Zero data is inserted based on the means for applying a low pass filter, the second frequency dividing means for dividing the second clock signal by 5, and the clock signal frequency-divided by the second frequency dividing means. And a means for thinning out color difference data.

The present invention uses the 4: 2: 2p method or the 4: 2: method.
A clock signal for changing the number of pixels can be obtained with a simple configuration in which a clock that is 6 times the sampling frequency of luminance data and color difference data in the 0p system is generated, and this clock is divided by 5. To do.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the signal format of the present invention will be described. The signal format of the present invention is shown in FIG.
As shown in, on a screen with an aspect ratio of 16: 9,
The number of effective scanning lines is 480 and the number of effective horizontal pixels is 864.

The number of effective scanning lines in the conventional progressive scanning system having an aspect ratio of 16: 9 is 480. In order to obtain a square pixel for each pixel without changing the number of effective scanning lines, the number of pixels may satisfy the following formula. Number of pixels = 16/9 × 480 = 853.3 Therefore, if the number of horizontal effective pixels is set to about 853, each pixel becomes a square pixel, and image processing by a computer can be easily performed.

By the way, when recording and transmitting this image data, the amount of image data becomes enormous in the uncompressed state, and data compression is indispensable. However, J mentioned above
When using PEG or MPEG, the discrete cosine transform (D
Since one block of (CT) has 8 pixels × 8 pixels, and the color difference information is generally a sample point of half the luminance, it is convenient that the number of pixels is a multiple of 16.

Therefore, in order to obtain pixels close to a square, the number of horizontal effective pixels is close to about 853 and is set to 864 pixels which is a multiple of 16. As a result, image processing on a computer can be facilitated, and image compression techniques such as JPEG and MPEG can be used. Next, an apparatus for converting a 4: 2: 2p system signal into the signal format of the present invention will be described.

The 4: 2: 2p system is a digital interface in which a luminance signal of a 525p analog signal has a sampling frequency of 27 MHz and a color difference signal has a frequency of 13.5 MHz.
8: 4: 4 format video data sampled in
Interlaced data extracted for each line is used as a set of interlaced data, and a line having a complementary relationship with the extracted line is divided as another interlaced data and then doubled on the time axis. Each 13.5MHz
The sampling 525 interlaced digital component signal is interfaced with two bit streams having the same data structure. Therefore, 4: 2: 2p
The sampling frequency of the luminance data Y of the system is 27 MHz
The sampling frequency of the color difference data C _B and C _R is 13.5 MHz.

Therefore, the sampling rate of the luminance data Y and the color difference data C _B and C _R is changed to 6/5 times, and the number of effective horizontal pixels is converted to 864. Below, 4:
An apparatus for converting a 2: 2p type signal into the signal format of the present invention will be described with reference to FIG. Figure 2
FIG. 3 is a block diagram of the present conversion device.

Reference numeral 21 is a separation circuit. This separation circuit 21
Separates the 4: 2: 2p format data into luminance data Y, color difference data C _B and color difference data C _R. Reference numeral 22 denotes a first PLL circuit, which has a frequency of 162 MHz synchronized with the sampling frequency of the luminance data Y, 27 MHz.
Generate a clock signal for z. Reference numeral 23 ₁ denotes a second PLL circuit, which generates a clock signal of 81 MHz which is a frequency six times in synchronization with 13.5 MHz which is the sampling frequency of the color difference data C _B.

Numeral 23 ₂ is a third PLL circuit, which generates a clock signal of 81 MHz which is a frequency six times synchronized with 13.5 MHz which is the sampling frequency of the color difference data C _R. Reference numeral 24 is a first interpolation / filter circuit. This interpolation / filter circuit 24 is provided by the 16th circuit from the PLL circuit 22.
Five 0 data are inserted between the luminance data Y of each pixel based on the clock signal of 2 MHz. Then, the harmonic component generated by the insertion is removed. Furthermore, interpolation /
The filter circuit 24 gives a 6 times gain because the level is lowered by inserting 0.

25 ₁ is a second interpolation / filter circuit. The interpolation / filter circuit 25 ₁ is provided in the PLL circuit 22.
5 pieces of 0 data are inserted between the color difference data C _B of each pixel based on the clock signal of 81 MHz from. Then, the harmonic component generated by the insertion is removed.
Further, since the level of the interpolation / filter circuit 25 ₁ is lowered by inserting 0, the gain of 6 times is given.

25 ₂ is a third interpolation / filter circuit. The interpolation / filter circuit 25 ₂ is used in the PLL circuit 22.
5 pieces of 0 data are inserted between the color difference data C _R of each pixel based on the clock signal of 81 MHz from. Then, the harmonic component generated by the insertion is removed.
Furthermore, the level of the interpolation / filter circuit 25 ₂ is lowered by inserting 0, so that a gain of 6 times is applied.

Reference numeral 26 is a first frequency dividing circuit. The frequency dividing circuit 26 receives the 162 MHz clock signal from the PLL circuit 22 and outputs the 162 MHz clock signal to 5
Frequency division is performed to generate a 32.4 MHz clock signal. Two
7 ₁ is a second frequency dividing circuit. This frequency dividing circuit 27 has P
16. The 81 MHz clock signal from the LL circuit 23 ₁ is input, and the 81 MHz clock signal is frequency-divided by 5. 16.
Generate a 2 MHz clock signal.

27 ₂ is a _second frequency dividing circuit. The frequency dividing circuit 27 inputs the 81 MHz clock signal from the PLL circuit 23 ₂ and outputs the 81 MHz clock signal to 5
Frequency division is performed to generate a 16.2 MHz clock signal. Two
Reference numeral 8 is a first thinning circuit. This thinning circuit 28
The interpolated luminance data Y is thinned out based on the 32.4 MHz clock signal from the frequency dividing circuit 26. Then, the data having 864 horizontal effective pixels is output.

29 ₁ is a second thinning circuit. This decimation circuit 29 ₁ uses 16.2 MHz from the frequency dividing circuit 27.
Color difference data C _B interpolated based on the clock signal of
Thin out. Then, the data having 864/2 horizontal effective pixels is output. 29 ₂ is a third thinning circuit. This decimation circuit 29 ₂ is equivalent to 1 from the frequency dividing circuit 27.
The interpolated color difference data C _R is decimated based on the 6.2 MHz clock signal. Then, the data having 864/2 horizontal effective pixels is output.

Reference numeral 30 denotes a digital compression encoder, which has luminance data Y of 864 horizontal effective pixels, color difference data C _B of 864/2 horizontal effective pixels and color difference data of 864/2 horizontal effective pixels. Input _CR and digitally compress it. Next, an apparatus for converting a 4: 2: 0p type signal into the signal format of the present invention will be described.

The 4: 2: 0p system uses the above-mentioned 8: 4: 4.
This is a data system in which only the color difference signal of the video data of the system is passed through a vertical low-pass filter and then thinned out in an interlaced manner in the vertical direction. Therefore, the luminance signal is 27 MH
It has z-sampling progressive scan data, and the color difference signal has 6.75 MHz sampling data. Therefore,
The PLL circuit 23 ₁ and the PLL circuit 23 ₂ of the conversion device in the 4: 2: 0p system described above are synchronized with the sampling frequency of the color difference data of 6.75 MHz, which is 40.5M.
A clock signal of Hz may be generated.

The operation will be described below with reference to FIG. The 4: 2: 0p type data is input to the separation circuit 21, and the luminance data Y, the color difference data C _B, and the color difference data C _R are input.
Is separated into Then, the luminance data Y is the PLL circuit 2
Based on the 162 MHz clock signal generated in 2, the interpolation / filter circuit 24 interpolates and removes the harmonic component. That is, the luminance data Y has been converted into data having six times the number of pixels.

Further, the color difference data C _B is the PLL circuit 23 ₁
On the basis of the 40.5 MHz clock signal generated in step ₁ , the interpolation / filter circuit 25 ₁ interpolates, and harmonic components are removed. That is, the color difference data C _B is
This means that the number of pixels has been converted to six times. Similarly, the color difference data C _R is interpolated by the interpolation / filter circuit 25 ₂ based on the 40.5 MHz clock signal generated by the PLL circuit 23 ₂ , and the harmonic components are removed. That is, the color difference data C _R has been converted into data having six times the number of pixels.

On the other hand, 162 generated by the PLL circuit 22
The frequency of the MHz clock signal is divided by 5 by the frequency dividing circuit 26. Then, a clock signal of 32.4 MHz is generated. Further, the clock signal of 40.5 MHz generated by the PLL circuit 23 ₁ and the PLL circuit 23 ₂ is divided by the frequency dividing circuit 2
The frequency is divided by 5 by 7 ₁ and the frequency dividing circuit 27 ₂ . And
A clock signal of 8.1 MHz is generated.

The interpolated luminance data Y is used in the thinning circuit 2
8 decimates at 32.4 MHz samples. That is, 5 pixels are thinned out every 6 pixels, and 864 samples of luminance data are output. The interpolated color difference data C _B is thinned out by the thinning circuit 29 ₁ at a sampling rate of 8.1 MHz. That is, 5 pixels are thinned out for every 6 pixels. Similarly, the interpolated color difference data C _R is the decimation circuit 29 ₂ is thinned by 8.1MHz sample. That is, 5 pixels are thinned out for every 6 pixels.
Then, as the color difference data, data of 864/2 samples is output.

The digital compression encoder 30 digitally compresses the luminance data of 864 samples and the color difference data of 864/2 samples. 2 and 3
In the example of FIG. 2, a PLL circuit is provided for each of Y, C _B, and C _{R in} order to make the explanation easy to understand. However, in practice, only one PLL circuit 22 is necessary. In the example of FIG. In the example of 3, 1 /
It is possible to obtain clocks of 81 MHz and 40.5 MHz by dividing the frequency by 4.

[0035]

According to the signal format of the image signal of the present invention, since each pixel is square when the aspect ratio is 16: 9, image processing by a computer can be facilitated.
Further, since the number of vertical and horizontal pixels is a multiple of 16, it is also suitable for data compression such as JPEG and MPEG.

Furthermore, when converting a signal of the 4: 2: 2p system or the 4: 2: 0p system into the signal format of the present invention, the conversion should be performed with a simple structure without using a complicated rate converter. Can be done.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a signal format of an image signal of the present invention.

FIG. 2 is a block diagram of a conversion device of the present invention.

FIG. 3 is a block diagram of a conversion device of the present invention.

FIG. 4 is a diagram for explaining a data compression technique.

[Explanation of symbols]

21 Separation circuit 22, 23 PLL circuit 24, 25 ₁ , 25 ₂ Interpolation / filter circuit 26, 27 Dividing circuit 28, 29 ₁ , 29 ₂ Thinning circuit 30 Encoder

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI G09G 5/00 G09G 5/00 555A H04N 7/24 H04N 7/13 Z 11/06 11/06 11/24 (56) References JP-A-7-87449 (JP, A) JP-A-6-38238 (JP, A) JP-A-6-205387 (JP, A) JP-A-4-79696 (JP, A) JP-A-8-125963 (JP, A) JP-A-7-140954 (JP, A)

Claims (3)

(57) [Claims] 1. A horizontal effective pixel having an aspect ratio of 16: 9.
Convert the format of the image signal whose number is 720
A method, sampling frequency of the luminance data in the image signal
Of generating a clock signal with a frequency of 6 times
And zero data for the luminance data based on the clock signal.
A step of inserting and low-pass filtering, a step of dividing the clock signal by 5 and a clock signal divided by the step of dividing
To thin out the luminance data with zero data inserted.
And a conversion method. 2. A horizontal effective pixel having an aspect ratio of 16: 9.
Convert the format of the image signal whose number is 720
A device, wherein the sampling frequency of luminance data in the image signal
Means for generating a clock signal having a frequency of 6 times, and zero data for luminance data based on the clock signal.
Based on the means for inserting and low-pass filtering, the frequency dividing means for dividing the clock signal by 5 , and the clock signal divided by the frequency dividing means,
(B) The means for thinning out the luminance data with the inserted data.
A conversion device having. 3. A device for converting a format of an image signal of 4: 2: 2p or 4: 2: 0p system, wherein luminance data sampling in an image signal of 4: 2: 2p or 4: 2: 0p system is performed. Means for generating a first clock signal having a frequency of six times, means for inserting zero data into luminance data based on the first clock signal, and applying a low-pass filter, and the first clock signal A frequency dividing means for dividing the luminance data into which zero data is inserted based on the clock signal divided by the first frequency dividing means, and 4: 2: 2p Means for generating a second clock signal having a frequency that is 6 times the sampling frequency of the color difference data in the method or the 4: 2: 0p method, and the color difference data having zero frequency based on the second clock signal. Based on the clock signal divided by the second frequency dividing unit, a second frequency dividing unit that divides the second clock signal by 5 And a means for thinning out color difference data in which zero data is inserted.