JP3439036B2 - Quadrature and amplitude error compensation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system for modulating and transmitting digital signals. In particular, it relates to a device for demodulating a digital signal.

[0002]

2. Description of the Related Art In digital communication using a phase modulation / demodulation system, a conventional demodulator for extracting information from a modulated wave amplifies a received modulated wave with an amplifier and performs orthogonal quasi-synchronous detection with an orthogonal quasi-synchronous detector. The output of the quadrature quasi-synchronous detector is detected by the detector, and the discriminator uses the discriminant plane on the IQ plane where the in-phase component is the I axis and the quadrature component is the Q axis to identify the in-phase component that is the output of the detector. Information is obtained from the orthogonal components.

[0003]

However, the in-phase component and the quadrature component, which are the outputs of the quadrature quasi-synchronous detector, should ideally be quadrature and have a constant amplitude. Therefore, the amplitude may not be constant or may not be orthogonal. That is, the output of the quadrature quasi-synchronous detector,
Quadrature / amplitude error occurs. Therefore, if the in-phase component and the quadrature component, which are the outputs of the quadrature quasi-synchronous detector, are directly used as the input of the detector, there is a drawback that the bit error rate (BER) increases. A detailed process of causing such a defect will be described below.

FIG. 7 is a diagram showing a locus drawn by the in-phase component and the quadrature component, which are outputs of the quadrature quasi-synchronous detector, and shows what locus is drawn on the IQ plane due to the imperfections of the apparatus. It is a figure explaining.

[0005] perpendicular to the quasi-coherent detector, to generate a phase sum signal and the phase difference signal by multiplying the reference signal to the phase-modulated wave signal _{Acos (ω c t + Φ k} ), the phase of low-pass filter This is a device that removes the sum signal and obtains the phase difference signal. Here, AS in the formula of the modulated wave signal represents the amplitude of the modulated signal, ω _c represents the angular frequency of the carrier, and Φ _k represents the phase component having different values in the value of the baseband signal. Also,
The reference signal is a sine function p _i co of the angular frequency ω = ω _c + Δω that is different from the angular frequency ω _{c of the} carrier by an error Δω.
s (.omega.t) and cosine functions -p _q is that sin of (.omega.t), the use of each of the reference signal, the in-phase component of the modulated wave _{I = Ap i cos (Φ k} -Δωt) and a quadrature component Q = -p
_q sin (Φ _k −Δωt) is obtained. Note that the sine function p _i cos (ωt) and the cosine function p _q sin (ω
p _i and p _{q in} t) represent the amplitudes of the respective functions.

When the error Δω is zero, the in-phase component and the quadrature component are Ap _i cos (Φ _k ) and Ap _{q, respectively.}
sin (Φ _k ). Therefore, the loci of the in-phase component and the quadrature component on the IQ plane are stationary in one time slot, although the position of the point changes with the change of Φ _k . However, since Δω actually has a certain value, the loci of the in-phase component and the quadrature component become loci that rotate with the passage of time. Here, assuming that the amplitudes p _i and p _{q of the} reference signal for deriving the in-phase component and the quadrature component have the same value, and the gains of the in-phase component and the quadrature component are the same, the in-phase component on the IQ plane and The locus of the orthogonal component is a perfect circle as shown in FIG.

However, in reality, due to the imperfections of the device,
The above assumption does not hold, and the loci of the in-phase component and the quadrature component on the IQ plane are ellipses whose axes are the I axis and the Q axis, as shown in FIG. 7B.

Up to this point, as a precondition, a sine function p _i c is used as a reference signal for deriving an in-phase component and a quadrature component.
It has been assumed that os (ωt) and the cosine function −p _q sin (ωt) are used. That is, this is a case where the phases of the two reference signals for deriving the in-phase component and the quadrature component are exactly deviated by π / 2, and therefore, the in-phase component and the quadrature component are exactly quadrature. However, when the in-phase component and the quadrature component are not orthogonal to each other due to the imperfections of the device, the axis becomes an ellipse whose axis deviates from both the I axis and the Q axis, as shown in FIG. 7C. According to the equation, the reference signals are p _i cos (ωt) and −p _q sin (ωt + Φ). When the in-phase component and the quadrature component are obtained from these, I = A p _i cos (Φ _k −Δωt) and Q, respectively. = Ap _q s
in (Φ _k −Δωt −Φ). These equations express the quadrature / amplitude error of the output of the quadrature quasi-synchronous detector.

Summarizing the above description, the in-phase component I and the quadrature component Q are orthogonal to each other, and the amplitude (square root of I ² + Q ² )
7 is constant, the loci of the in-phase component and the quadrature component on the IQ plane are perfect circles as shown in FIG. 7 (a). The axis is an ellipse whose axes are the I axis and the Q axis, and when the axes are not orthogonal to each other, the axis is an ellipse displaced from both the I axis and the Q axis as shown in FIG. 7C.

The reason why the loci of the in-phase component and the quadrature component, which are the outputs of the quadrature quasi-synchronous detector, are not perfect circles is that the phase shifter constituting the quadrature quasi-synchronous detector accurately transfers π / 2.
It is caused by incompleteness of the device, such as when the phase cannot be shifted only or when the gains of the in-phase component and the quadrature component are different.

Next, it will be explained how the in-phase component and the quadrature component, which are the outputs of the quadrature quasi-synchronous detector, are input to the detector and processed, and as a result, the BER is increased. The purpose of the processing of the detector is to remove the influence of the rotation of the loci of the in-phase component and the quadrature component caused by the frequency shift Δω of the reference signal of the quadrature quasi-synchronous detector to obtain a new in-phase component and quadrature component. It is in. However, since white Gaussian noise is added to the signal and noise is distributed around the loci of the in-phase component and the quadrature component on the IQ plane, the loci of the in-phase component and the quadrature component which are the outputs of the quadrature quasi-synchronous detector. When is not a perfect circle, the result of performing the processing of the detector and extracting the digital signal by the discriminating device shows that the loci of the in-phase component and the quadrature component are perfect circles.
BER increases.

As described above, the in-phase component and the quadrature component which are the outputs of the quadrature quasi-synchronous detector should ideally be quadrature and have a constant amplitude, but due to the imperfections of the device. Quadrature / amplitude error occurs. For this reason, the amplitude may be different between the in-phase component and the quadrature component, or may not be quadrature, and if the in-phase component and the quadrature component are directly input to the detector, there is a drawback that the BER is increased.

Further, due to the imperfections of the device, the in-phase component and the quadrature component are quadrature, but the amplitude is not constant, or even if they are not quadrature, the difference from the complete device is known in advance. If it is, a device for adjusting the in-phase component and the quadrature component by a constant is provided after the quadrature quasi-synchronous detector,
A technique is also known in which the in-phase component and the quadrature component are orthogonal and the amplitude is constant. Although it is possible to improve the BER by using this conventional technique, it is difficult to adjust the BER, which causes a disadvantage of increasing labor costs. Further, such a conventional technique does not provide any effective means when the fluctuations of the in-phase component and the quadrature component change with the lapse of time due to the slow time fluctuation caused by the temperature fluctuation.

An object of the present invention is to solve these problems and to provide a quadrature and amplitude error compensating circuit for making the in-phase component and the quadrature component output from the quadrature quasi-synchronous detector quadrature and keeping the amplitude constant. And

[0015]

SUMMARY OF THE INVENTION A quadrature and amplitude error compensating circuit of the present invention is a quadrature and amplitude error compensating for quadrature and amplitude errors of in-phase and quadrature component signals output from a quadrature quasi-synchronous detector. In the compensation circuit, a signal obtained by multiplying the input signal of one of the in-phase component and the quadrature component from the quadrature quasi-synchronous detector by the first coefficient and a signal obtained by multiplying the input signal of the other component by the second coefficient are provided. First means for adding and outputting an output signal for one component, second means for multiplying an input signal for the other component by a third coefficient, and an output signal for the component, and a quadrature quasi-synchronous detector. The first to third coefficients are updated so that the output signal of the first means and the output signal of the second means are orthogonal and the sum of squares thereof is constant for each predetermined number of inputs from Equipped with a third means to Characterized in that was.

The third means is a fourth means for obtaining an error term e obtained by subtracting the sum of squares of the output of the first means and the output of the second means from the square of a constant σ representing the desired amplitude level. , A first update difference obtained by multiplying a multiplication value of the input signal and the output signal of one component and the error term e by a constant parameter μ for controlling the magnitude of the correction, and updating the first update difference Fifth means for adding to the previous first coefficient to obtain a new first coefficient, and second means for multiplying the input signal of one component, the output signal of the other component, the error term e and the parameter μ Of the second component, and the second update difference is added to the second coefficient before updating to obtain a new second coefficient, the input signal of the other component, and the output of one component. A third update difference obtained by multiplying the signal, the error term e and the parameter μ is obtained, and the third update difference is obtained. It is possible to include a sixth unit for a third by adding the coefficient new second coefficient before updating different.

The principle of the present invention will be described below. First, the orthogonality and amplitude error generation model by the discrete time expression is developed as follows.

[0018]

[Equation 1] However, x _{i, k} and x _{q, k} represent the in-phase component and the quadrature component, respectively, and the subscript k represents the time. The matrix term on the right-hand side of Equation 1 is the portion that obviously causes the orthogonality and amplitude errors. Therefore, the orthogonality and the amplitude error can be compensated by multiplying the vector of Equation 1 by the inverse matrix of this matrix term. This inverse matrix can be easily obtained as follows.

[0019]

[Equation 2] That is, quadrature and amplitude will be compensated for by accurately estimating the three elements of the matrix in Eq. Therefore, the following processing corresponding to equation 2 is performed on the quadrature-detected signal.

[0020]

[Equation 3] However, y _{i, k} and y _{q, k} represent a signal-processed in-phase component and quadrature component. In order to estimate these three matrix elements, paying attention to the fact that the output amplitude is constant regardless of the transmission code bit if quadrature amplitude compensation is perfect, and a CMA (Constant Modulus Algorithm) that uses constant amplitude as a cost function is used. Apply. This algorithm is based on the literature: JR Treichler and MGLarimore, "New process
ing techniques based on the constant adaptive algo
rithm ", IEEE Trans.Acoust., Speech & processing, A
Details on SSP-33, pp.420-431, 1985. The cost function to which CMA is applied is shown in Equation 4.

[0021]

[Equation 4] In this equation, σ ² is the desired amplitude level, and the matrix H and the vector X are the right-varying matrix and vector of Equation 3, respectively. CM
The parameter estimation formula used in A is obtained as an extension of the steepest descent method and is given by the following formula.

[0022]

[Equation 5] However,

[0023]

[Equation 6] Is. μ is a constant called a step size parameter and is a parameter for controlling the magnitude of correction in each iteration. [•] ^T represents the transpose of a matrix or vector. Table 1 shows an update formula in which Formula 6 is specifically calculated. Since the orthogonality and amplitude compensation model obtained by the equation 3 is perfect, the orthogonality and amplitude error compensation can be realized by repeatedly executing the parameter estimation formulas of the equations 4 and 5.

In the present invention, the in-phase component and the quadrature component as the output of the quadrature quasi-synchronous detector are subjected to the signal processing which is sequentially adapted with the lapse of time, so that the output of the quadrature quasi-synchronous detector is quadrature and Amplitude error is compensated, the in-phase component and the quadrature component are made orthogonal, and the amplitude is made constant.
This is different from the conventional technique in that the in-phase component and the quadrature component of the output of the quadrature quasi-synchronous detector are not immediately input to the detector, but are input to a signal processing device for signal processing. Further, even when compared with the conventional technique in which a device for adjusting the in-phase component and the quadrature component by a constant is provided, the coefficient used when performing signal processing on the in-phase component and the quadrature component is not a constant, but sequentially with the passage of time. They are different in that they change.

According to the present invention, quadrature and amplitude errors occur in the in-phase component and the quadrature component as the output of the quadrature quasi-synchronous detector,
Even if the amplitudes are quadrature but not constant, or even if they are not quadrature, the output of the quadrature quasi-synchronous detector is processed by the quadrature and amplitude error compensating circuit, which is a kind of signal processing device, to obtain the in-phase component. Since it is possible to make the quadrature component and the amplitude constant, it is possible to obtain the effect of lowering the BER.

According to the present invention, the coefficient used for signal processing of the in-phase component and the quadrature component as the output of the quadrature quasi-synchronous detector is sequentially changed with the passage of time, so that the slow time due to the temperature fluctuation is caused. Even if the fluctuations of the in-phase component and the quadrature component change over time due to fluctuations, signal processing can be performed by adapting to the conditions that change from moment to moment, so there is temperature fluctuation. Also has the effect of lowering the BER.

[0027]

1 is a block diagram of a digital signal demodulating device showing an embodiment of the present invention. This demodulation device comprises an amplifier 1, a quadrature quasi-synchronous detector 2, a quadrature and amplitude error compensation circuit 3, a detector 4 and an identification device 5. The phase-modulated modulated wave that has reached the demodulator in the form of a radio wave is received by the antenna, amplified by the amplifier 1, and input to the quadrature quasi-synchronous detector 2. The quadrature quasi-coherent detector 2 quadrature quasi-coherently detects the amplified received wave and outputs signals of an in-phase component and a quadrature component. Hereinafter, these signals are simply referred to as “in-phase component” and “quadrature component”. The output of the quadrature quasi-synchronous detector 2 is the quadrature and amplitude error compensation circuit 4
The signal is input to the detector 4 via and is detected. The identification device 5 identifies information from the in-phase component and the quadrature component output from the detector 4 with the IQ plane having the in-phase component as the I axis and the quadrature component as the Q axis as the identification surface. As a result, digital baseband information can be obtained from the modulated wave that reaches the demodulator in the form of radio waves.

The in-phase component and the quadrature component output from the quadrature quasi-synchronous detector 2 are perfectly synchronized on the IQ plane because the frequency of the reference signal is not exactly the same as the frequency of the carrier wave. Instead, it becomes a rotating trajectory. In addition, due to the imperfections of the quadrature quasi-synchronous detector 2, the in-phase component and the quadrature component are usually quadrature but not constant in amplitude or not quadrature. That is,
Quadrature and amplitude errors occur.

Therefore, in the present embodiment, the in-phase component and the quadrature component of the modulated wave, which is the output of the quadrature quasi-synchronous detector 2, are a quadrature that is a kind of signal processing device installed in the subsequent stage of the quadrature quasi-synchronous detector 2. And input to the amplitude error compensation circuit,
The in-phase component and the quadrature component that have undergone signal processing are obtained as outputs. The signal-processed in-phase component and quadrature component are orthogonal to each other due to the function of the quadrature and amplitude error compensating circuit 3,
And the amplitude is constant. By inputting the signal-processed in-phase component and quadrature component to the detector 4, an in-phase component and a quadrature component that are completely synchronized and stationary on the IQ plane can be obtained.

2 to 6 are diagrams showing a detailed circuit configuration of the quadrature and amplitude error compensating circuit 3, which are shown separately for each function. FIG. 2 shows the coefficients h ₁ , h ₂ , and h for the in-phase component x _I and the quadrature component x _q input from the quadrature quasi-coherent detector ₂ .
FIG. 3 shows a configuration for processing using h ₃ , FIG. 3 shows a configuration for obtaining the error term e, and FIGS.
A configuration for obtaining ₁ , h ₂ , and h ₃ is shown.

Referring to FIG. 2, this quadrature and amplitude error compensating circuit 3 has the same input in-phase as the multiplier 11 for multiplying the input quadrature component x _q from the quadrature quasi-synchronous detector 2 by the first coefficient h _1. The multiplier 12 that multiplies the component x _i by the second coefficient h ₂ , the adder 13 that adds the output of the multiplier 11 and the output of the multiplier 12 to form the output quadrature component y _q , and the input in-phase component x _i Is multiplied by a _third coefficient h ₃ to obtain an output in-phase component y _i . That is, signal processing of y _i = h ₃ x _i and y _q = h ₁ x _q + h ₂ x _i is performed. Here, the coefficients h ₁ , h ₂ , and h ₃ are not constants, but are coefficients that change sequentially over time so that the in-phase component y _i and the quadrature component _q are orthogonal and the sum of squares thereof is constant. is there. Therefore, it is necessary to sequentially update the coefficients h ₁ , h ₂ and h ₃ for each predetermined number of inputs. Note that this sequential update is
It may be performed every time one symbol is input, or may be performed every plural symbols. Therefore, the update cycle is less than or equal to the symbol rate.

The coefficients h ₁ , h ₂ and h ₃ can be calculated from the input / output components and the output amplitude error. As the amplitude error, an error term e is defined by subtracting the sum of squares of the in-phase component y _i and the quadrature component y _q from the square of the constant σ representing the desired amplitude level. To obtain the error term e, as shown in FIG. 3, the square of the constant σ is obtained by the multiplier 15, the squares of the in-phase component y _i and the quadrature component y _q are obtained by the multipliers 16 and 17, respectively. Multiplier 1 at the outputs of 16 and 17
8 and 19 are multiplied by -1, and multipliers 15, 18, 19
Are added by the adder 20. The constant σ can be selected arbitrarily, but when the circuit is a digital circuit and the signal is quantized, if the value of the constant σ is made too small, it will be buried in the quantization error, and conversely it will be made too large. Therefore, it is desirable to set an appropriate value. Even if the circuit is analog, if the value of the constant σ is too small, it will be greatly affected by the DC drift, and if it is made too large, the power consumption will be too large. Must be set.

Next, the updating of the coefficient h ₁ will be described with reference to FIG. Here, the coefficient h ₁ before update is h _{1, k-1} ,
The updated coefficient h ₁ is represented as h _{1, k} . To obtain the coefficients h _{1, k} , the input quadrature component x _q , the output quadrature component y _q , the error term e, and a constant parameter μ that controls the magnitude of the correction are multiplied by the multiplier 21 to obtain The obtained update difference Δh ₁ is added to the coefficient h _{1 1, k-1} before update by the adder 22. The coefficient h _{1, k} thus _obtained is the multiplier 11 shown in FIG.
Is supplied to. The parameter μ is a constant called a step size parameter and controls the magnitude of correction in each iteration.

The coefficient h ₂ is updated by updating the coefficient h ₂ before the update by h
_{2, k−1} , and the updated coefficient h ₂ is represented by h _{2, k,} and as shown in FIG. 5, the input quadrature component x _q , the output in-phase component y _i , the error term e, and the parameter μ are multiplied by the multiplier 23. And the obtained update difference Δh ₂ is multiplied by
Add to _{2, k-1} . The coefficient h _{2, k} obtained by this is supplied to the multiplier 12 shown in FIG.

The coefficient h ₃ is updated by updating the coefficient h ₃ before the update by h
_{3, k−1} , and the updated coefficient h ₃ is represented by h _{3, k,} and as shown in FIG. 6, the input in-phase component x _i , the output in-phase component y _i , the error term e, and the parameter μ are multiplied by 25. And the update difference Δh ₃ obtained is multiplied by
Add to _{3, k-1} . The coefficient h _{3, k} thus obtained is supplied to the multiplier 14 shown in FIG.

Table 1 shows updating formulas of the coefficients h ₁ , h ₂ and h ₃ . Signal processing is performed by the configuration shown in FIG. 2 using the coefficients h ₁ , h ₂ , and h ₃ that change sequentially. As a result, quadrature and amplitude errors occur in the in-phase component and quadrature component on the IQ plane and are not quadrature or quadrature but amplitude is not constant,
It is possible to modify them so that they are orthogonal and the amplitude is constant. Further, even if the fluctuations of the in-phase component and the quadrature component change with the passage of time due to changes in the temperature characteristics, the coefficients h ₁ , h ₂ , and h ₃ change sequentially, so that the fluctuations are adaptively followed. Signal processing becomes possible.

[0037]

[Table 1]

[0038]

When there is an error in the orthogonality and the amplitude of the in-phase component and the quadrature component as the output of the quadrature quasi-synchronous detector, the amplitude fluctuates according to the phase of the signal. Therefore, in the present invention, a quadrature and amplitude error compensating circuit using a CMA algorithm for making the amplitude constant is provided at the output of the quadrature quasi-coherent detection. This makes it possible to make the in-phase component and the quadrature component orthogonal to each other and to keep the amplitude constant. Removing the quadrature and amplitude errors results in BE
The effect of lowering R can be obtained.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a digital signal demodulation device showing an embodiment of the present invention.

FIG. 2 is a diagram showing a part of the configuration of a quadrature and amplitude error compensation circuit, which is a configuration for processing in-phase component x _I and quadrature component x _q using coefficients h ₁ , h ₂ , and h ₃ ; FIG.

FIG. 3 is a diagram showing a part of the configuration of a quadrature and amplitude error compensation circuit, and a circuit diagram showing a configuration for obtaining an error term e.

FIG. 4 is a diagram showing a part of a configuration of a quadrature and amplitude error compensation circuit, and a circuit diagram showing a configuration for obtaining a coefficient h ₁ .

FIG. 5 is a diagram showing a part of the configuration of a quadrature and amplitude error compensation circuit, and a circuit diagram showing a configuration for obtaining a coefficient h ₂ .

FIG. 6 is a diagram showing a part of a configuration of a quadrature and amplitude error compensation circuit, and a circuit diagram showing a configuration for obtaining a coefficient h ₃ .

FIG. 7 is a diagram showing a locus drawn by an in-phase component and a quadrature component which are outputs of a quadrature quasi-coherent detector.

[Explanation of symbols]

1 amplifier 2 Quadrature quasi-synchronous detector 3 Quadrature and amplitude error compensation circuit 4 detector 5 Identification device 11, 12, 14-19, 21, 23, 25 Multiplier 13, 20, 22, 24, 26 adder

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-188928 (JP, A) JP-A-7-95137 (JP, A) JP-A-3-157034 (JP, A) JP-A-9- 135279 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/22

Claims (3)

(57) [Claims] 1. A quadrature and amplitude error compensating circuit for compensating for quadrature and amplitude errors of signals of an in-phase component and a quadrature component output from a quadrature quasi-synchronous detector. A signal obtained by multiplying an input signal of one component of the orthogonal components by a first coefficient and a signal obtained by multiplying an input signal of the other component by a second coefficient to obtain an output signal for the one component. Means, second means for multiplying the input signal of the other component by a third coefficient to obtain an output signal for that component, and for each predetermined number of inputs from the quadrature quasi-synchronous detector And a third means for updating the first to third coefficients so that the output signal of the first means and the output signal of the second means are orthogonal and the sum of squares thereof is constant. Orthogonal and And amplitude error compensation circuit. 2. The third means obtains an error term obtained by subtracting the sum of squares of the output of the first means and the output of the second means from the square of a constant σ representing a desired amplitude level. And a first update difference obtained by multiplying a multiplication value of the input signal and the output signal of the one component and the error term by a constant parameter for controlling the magnitude of the correction. Fifth means for adding the update difference to the pre-update first coefficient to obtain a new first coefficient, the input signal of the one component, the output signal of the other component, the error term, and the parameter Sixth means for obtaining a second update difference by multiplying by, and adding the second update difference to the second coefficient before update to obtain a new second coefficient, and inputting the other component The signal, the output signal of the one component, the error term, and the parameter are multiplied. 6. A sixth means for obtaining a calculated third update difference and adding the third update difference to the pre-update third coefficient to obtain a new second coefficient. Amplitude error compensation circuit. 3. A quadrature quasi-synchronous detector that quadrature quasi-coherently detects a phase-modulated modulated wave and outputs signals of an in-phase component and a quadrature component, and a detector that detects an output from the quadrature quasi-synchronous detector. A demodulator provided with a discriminating device for discriminating information from an in-phase component signal and a quadrature component signal output from the detector using an IQ plane having an in-phase component as an I-axis and a quadrature component as a Q-axis as an identification plane, A quadrature quasi-synchronous detector between the detector and the detector.
Alternatively, the demodulation device is provided with the quadrature and amplitude error compensation circuit described in 2.