JP3435941B2 - Data transfer system and computer system and functional circuit board for hot-swap - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hot-swappable functional circuit board, a data transfer system and a computer system using the same.

[0002]

2. Description of the Related Art Electronic information processing apparatuses such as computers are required to have improved processing performance and reliability. In particular, in a bus connecting a large number of functional circuits in an electronic information processing apparatus, the functional circuit connected to this bus is removed without stopping or pausing the bus operation, that is, without interrupting the data transfer of the bus. Alternatively, hot-swap technology is required to connect new functional circuits for maintenance.

As prior art relating to this hot-line insertion / removal, Japanese Patent Laid-Open Nos. 2-125314 and 4-8840 are known.
No. 9 publication is known. In the former conventional technique, a bus interface circuit is provided between a bus wiring and a functional circuit, and the operation of this bus interface circuit is controlled to be turned on / off to realize insertion / removal without suspending the bus operation. The latter conventional technique realizes hot plugging / unplugging by providing a switching element such as a MOS field effect transistor between the bus wiring and the functional circuit and turning on / off the switching element.

[0004]

In the former prior art, an additional signal delay time is required in this bus interface circuit by newly providing the bus interface circuit. That is, when the bus interface circuit is composed of bipolar or MOS transistors, the delay time becomes about 2 to 10 ns. As a result, the improvement of the bus operating frequency is limited, and it is difficult to increase the speed of the bus. As described above, the former conventional technique has not taken into consideration the point of making it possible to cope with the speedup of the bus.

In the latter prior art, the delay in the switching element is small and it is suitable for speeding up. However, due to the capacitance of the functional circuit and the line connecting the functional circuit and the switching element, noise occurs in the bus signal at the moment of switching, and this noise causes other functional circuits on the bus to malfunction. There were challenges. As described above, the noise is generated on the bus because, when the potential of the bus and the potential of the line of the functional circuit to be inserted are different, charging / discharging occurs due to this potential difference at the moment when the switching element becomes conductive.

In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a data transfer system in which a functional circuit board can be hot-swapped without stopping or suspending an operating device and bus transfer in the device. Another object of the present invention is to provide a computer system and a hot-swap functional circuit board used therein. Another object of the present invention is to cope with the speeding up of the bus, and a data transfer system and a computer system in which the functional circuit board can be hot-swapped so that other functional circuits on the bus do not malfunction, and a hot-swap functional circuit. To provide a substrate.

[0007]

In order to achieve the above object, the present invention is a data transfer system having a bus for transferring data, comprising a functional circuit, and further an input / output signal path of the functional circuit. A functional circuit board having a resistor and a switching element connected in parallel with each other is formed so that it can be inserted into and removed from the bus by a connector provided at an input / output end of the resistor and the switching element connected in parallel. Data transfer system.

Further, the present invention is a data transfer system having a bus wiring for transferring data, wherein a functional circuit is provided, and a precharging resistor and a switching element are connected in parallel on an input / output signal path of the functional circuit. The data transfer system is characterized in that a functional circuit board, which is provided in the vicinity of the connector and is connected to the connector, is formed so as to be insertable into and removable from the bus wiring by the connector.

The present invention is also a data transfer system having a bus for transferring data, comprising a functional circuit, and further comprising a precharging resistor and a switching element connected in parallel to an input / output signal path of the functional circuit. A functional circuit board comprising switching control means for synchronizing and controlling the conduction of the switching element by using a delay clock obtained by delaying a bus clock used for data transfer of the bus by the bus clock period or less, A data transfer system is characterized in that it is formed so as to be insertable into and removable from the bus by a connector provided at the input and output ends of the resistor and the switching element connected in parallel.

Further, the present invention is a data transfer system comprising a bus wiring for transferring data, wherein a functional circuit is provided, and a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit. Is connected to the connector in the vicinity of the connector, and the conduction of the switching element is controlled by synchronizing with a delay clock obtained by delaying a bus clock used for data transfer in the bus wiring by the bus clock period or less. In the data transfer system, the functional circuit board having the switching control means is formed to be insertable into and removable from the bus wiring by the connector.

Further, the present invention is a data transfer system having a bus for transferring data, comprising a functional circuit, further comprising a precharging resistor and a switching element connected in parallel to an input / output signal path of the functional circuit. A functional circuit board provided with switching control means for controlling the conduction of the switching element based on a board insertion completion signal, and the functional circuit board is provided with a connector provided at an input / output terminal of the resistor connected in parallel and the switching element. It is a data transfer system characterized by being formed so that it can be inserted into and removed from.

Further, the present invention is a data transfer system comprising a bus wiring for transferring data, comprising a functional circuit, and a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit. Is connected to the connector in the vicinity of the connector, and a functional circuit board having switching control means for controlling conduction of the switching element based on a board insertion completion signal is inserted into and removed from the bus wiring by the connector. It is a data transfer system characterized by being formed possible.

Further, the present invention is a data transfer system having a bus wiring for transferring data, comprising a functional circuit, and a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit. Is provided in the vicinity of the connector by connecting to the connector, and the conduction of the switching element is synchronized by using a delay clock obtained by delaying a bus clock used for data transfer in the bus wiring by the bus clock period or less, The data transfer system is characterized in that a functional circuit board having a switching control means for controlling based on an insertion completion signal is formed so as to be insertable into and removable from the bus wiring by the connector.

The present invention is also a computer system in which a bus for transferring data is connected to a computer,
A functional circuit board provided with a functional circuit and a precharge resistor and a switching element connected in parallel to the input / output signal path of the functional circuit is provided at the input / output terminals of the parallel-connected resistor and the switching element. In the computer system, the connector is formed so as to be insertable into and removable from the bus.

The present invention is also a computer system in which a bus for transferring data is connected to a computer,
A functional circuit is further provided, and a precharging resistor and a switching element connected in parallel to an input / output signal path of the functional circuit are provided, and conduction of the switching element is connected to a bus clock used for data transfer of the bus. A functional circuit board provided with a switching control means for synchronizing and controlling using a delay clock delayed by a period or less, with respect to the bus by a connector provided at an input / output terminal of the resistor and the switching element connected in parallel. It is a computer system characterized by being formed so that it can be inserted and removed.

The present invention is also characterized in that a functional circuit is provided, and a precharging resistor and a switching element connected in parallel on the input / output signal path of the functional circuit are connected to the connector in the vicinity of the connector. It is a functional circuit board for hot-swap.

Further, according to the present invention, a functional circuit is provided, and a precharging resistor and a switching element connected in parallel on the input / output signal path of the functional circuit are connected to the connector in the vicinity of the connector to transfer data on the bus. A switching control unit that has an input unit for inputting a bus clock to be used, and that synchronizes and controls the bus clock input by the input unit with a delay clock delayed by the bus clock period or less; It is a featured hot-swap functional circuit board.

Further, according to the present invention, a functional circuit is provided, and a pre-charging resistor and a switching element connected in parallel on the input / output signal path of the functional circuit are connected to the connector in the vicinity of the connector, and are used for data transfer on the bus. It has an input means for inputting a bus clock to be used and a board insertion completion signal, and synchronizes the bus clock input by the input means with a delay clock delayed by the bus clock period or less, and the input means It is a functional circuit board for hot-plugging / unplugging, comprising switching control means for controlling based on an inputted board insertion completion signal.

Further, the present invention is characterized in that, in the data transfer system, the computer system, or the hot-swap functional circuit board, the switching element of the functional circuit board is formed of a MOS field effect transistor. Further, the present invention is characterized in that, in the data transfer system, the computer system, or the hot-swap functional circuit board, the resistance of the functional circuit board is formed to have a resistance value of 200Ω or more. Further, the present invention is characterized in that, in the data transfer system, the computer system, or the hot-swap functional circuit board, the resistance of the functional circuit board is formed to have a resistance value of 1300Ω or less.

That is, according to the present invention, a switching element having a resistor connected in parallel is provided on the input / output signal path on the functional circuit board connected to the bus, and the resistor and the switching element are provided in the vicinity of the connector of the functional circuit board. When the functional circuit board is mounted and further inserted, the switching element is controlled to conduct after the insertion is completed and the power supply to the functional circuit board is stable, and the functional circuit board including the functional circuit is in operation. Can be inserted or removed without stopping or pausing the bus in the device.

Further, the present invention is characterized in that the influence of noise generated by switching is prevented by controlling the switching element synchronously with the delayed bus clock, especially at the time of insertion.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be specifically described with reference to FIG. A CPU 1 is directly or indirectly connected to an electronic information processing apparatus such as a computer, or a bus wiring 1 for transferring data in the electronic information processing apparatus such as a computer. Is wired to. Reference numeral 3 is a functional circuit board that can be inserted and removed. Although not shown here, a plurality of functional circuits are connected to the bus wiring 1. A CPU may be connected to any of these functional circuits. 4 is a connector, and the functional circuit board 3 is
It is connected to the back panel 5 via this connector 4.

Reference numeral 10 denotes a functional circuit mounted on the functional circuit board 3. The functional circuit 10 includes a bus wiring 1, a connector 4, a switching element 11, and a precharging resistor 1.
2 and the wiring (leader wire) 13 are connected.
Although the switching element 11 is described here as a MOS field effect transistor, it may be a relay that can operate at high speed or a switch that is composed of a bipolar transistor. The switching element 11 and the precharging resistor 12 are connected in parallel. In addition, the functional circuit 10
Has an electrostatic capacity, and especially the C-MOS LSI has a large capacity. In the case of C-MOS, it is usually about 10 to 15 pF. In FIG. 1, the switching element 1
1 and resistor 12 for precharge, connector 4 and wiring 13
Although one set is inserted between and, in reality, at least all the signal lines output from the functional circuit board 3 are inserted.

Reference numeral 14 is a switching control means for controlling ON / OFF of the switching element 11. Power may be supplied to the functional circuit board 3 through a power supply / ground pin assigned to another pin of the connector 4 at the time of insertion, or may be supplied through a connecting means such as a connector provided separately. When the functional circuit board 3 is hot-plugged, the system resets the functional circuit 10 after the connector 4 is completely connected and after the power supply to the functional circuit board 3 is stabilized,
The switching control means 14 controls the switching element 11 from a non-conducting state to a conducting state. This connector 4
The connection completion may be detected by the user turning on a switch provided separately, or automatically by detecting the contact of the shortest pin shorter than the other pins provided on the connector 4. It is also possible to detect the insertion completion.

When performing hot line removal, IEEE 896.2 (Futureb
As described in “us +, Physical Layer Specifications & Profile”, when the functional circuit board 3 is notified by the system side that the hot line is removed, the functional circuit board 3 does the following.

(1) Complete all work currently in progress.

(2) Prevent the own board from participating in further bus transactions.

(3) Release all outputs of the bus (in a high resistance state).

According to the present invention, when the functional circuit board 3 is notified by the system side that the hot line is removed, after the bus access of the functional circuit 10 and the output of the control signal are stopped as described above, and the switching is performed. When the control unit 14 is notified by the system side that the hot line is removed, the control unit 14 controls the switching element 11 from the conductive state to the non-conductive state before the functional circuit board 3 is removed.

As described above, since the switching element 11 is made non-conductive before the hot line is removed, even if the functional circuit 10 fails and the bus signal cannot be released, the bus wiring 1 or The additional effect is that it can be removed without affecting other functional circuit boards.

It should be noted that the switching element 11 is the functional circuit 10 from the time when the conduction signal is received from the switching control means 14 after the functional circuit board 3 is inserted to the time when the non-conduction signal is received before the functional circuit board 3 is removed. Conduction is maintained throughout operation, and in this state the switching element 1
The delay at 1 is negligible. Therefore, it does not limit the speeding up of the bus.

The operation of the first embodiment of the present invention and the noise reduction effect at the time of insertion will be described with reference to FIGS. 4 to 7 in comparison with the configuration shown in FIG. FIG. 2 shows an equivalent circuit of a hot-swap circuit using bus switches in a typical backplane bus system. In addition, the numerical values described in each part in the figure are the conditions of the simulation described later.

In the circuit configuration example shown in FIG. 2, 1-1,
Reference numeral 1-2 is a transmission line forming a bus on the back panel 5. 3-1, 3-2, 3-3 are functional circuit boards that are inserted into and removed from the back panel 5, and functional circuit boards 3-1 and 3-
3 is mounted and data is transferred through the buses 1-1 and 1-2. Connector 4 of the functional circuit board 3-2
Is inserted and the voltage supplied to the functional circuit board 3-2 is stabilized, and then the switching element 11 is made conductive. 13-1, 13-2 and 13-3 are buses 1-1 and 1
-2 is a wiring (leader line) from the functional circuit 10-1,
10-2 and 10-3 (not explicitly shown) are connected to the input / output buffers 20-1, 20-2 and 20-3.

Here, the functional circuit 10 of the functional circuit board 3-1.
Outputs "H" data (= 5V) from the bus 1-1,
Other functional circuit boards 3-2, 3-connected to 1-2
3 is in a high-impedance state in which no output is made. Furthermore, it is assumed that the switching element 11 of the functional circuit board 3-2 is in the conductive state. That is, in terms of an equivalent circuit, only the capacitance is connected to the bus.
Therefore, the input / output buffers 20-2 and 20-3 of the functional circuits 10-2 and 10-3 are represented by the electrostatic capacity of the input / output circuit.

In the functional circuit board 3-2, if the switching element 11 is not provided, the capacitance is 10 to 20 pF if the semiconductor is composed of C-MOS.
And 10 pF in this example. The length of the wiring (lead-out line) 13-2 depends on the size of the functional circuit 10 to be connected. One side is 40-50 in recent multi-pin LSI
Since there are not a few mm packages, 50-100
It may be mm. The wiring capacity is 1.
Since it is about 0 pF, it becomes 5 to 10 pF per LSI. Therefore, the total of the line capacitance and the functional circuit capacitance is 15 to 20 pF, and the bus capacitance is 150 to 200 pF.
It becomes so large that it cannot be ignored, and noise may be generated when there is a potential difference between the bus signals.

On the other hand, the effect of noise on the bus signal when the connector is inserted while the switching element is non-conductive is small. This is because the capacity of the inserted signal line is the sum of the capacity of the wiring from the connector 4 to the switching element 11 and the input capacity of the switching element, and this line is wired in the shortest (about 5 to 10 mm). The total capacitance is as small as 5 to 6 pF, and the noise generated by charging and discharging this capacitance is about 1/40 to the signal amplitude.
This is because it becomes as small as 1/20.

Reference numeral 31 is a control power supply for controlling the switching element 11. Here, when the control power supply 31 outputs "H", the switching element 11 becomes conductive. this is,
For example, it is most suitable for an N-channel MOS field effect transistor, and a P-channel MOS conducts when "L" is output. Output buffer 20-1 and capacities 20-2 and 20
-3 terminal voltages are V (1), V (2), V
Notated in (3).

FIG. 3 is a waveform diagram simulating a case where the functional circuit board 3-2 is hot-plugged into the bus using the above equivalent circuit. In FIG. 3, V (2), V
The voltage waveform of (3) is shown. This is the result of turning on the switching element 2 ns after the start of the simulation.
In (3), it can be seen that the voltage drops from 5V to 2.2V. That is, it means that noise is generated in 2.8 V (= 5-2.2 V) in other functional circuits on the bus when the switching element is made conductive after the board 3-2 is inserted. This is the level at which malfunction occurs, and this noise causes the device to malfunction.

Next, the operation of the first embodiment of the present invention and the noise reduction effect at the time of insertion will be described with reference to FIGS. The parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and duplicate description is omitted. The following description is also the same. As in FIG. 2, FIG. 4 shows two functional circuit boards 3-1 on the back panel 5,
3-3 is installed, and one functional circuit board 3-
2 is a circuit model for analyzing the effect of the parallel connection of the switching element 11 and the precharging resistor 12 of the first embodiment, which is an embodiment in which 2 is inserted.

Here, the output signal of the switching control means 14 shown in FIG. 1 is equivalently replaced by the control power supply 31. Further, the equivalent circuit of the connector 4 when inserting the functional circuit board 3-2 was replaced with the switch 15, and the contact state of the connector 4 was replaced with the conduction of the switch 15 to perform circuit analysis. This is the functional circuit board 3
This is because when -2 is inserted, the time until the back panel 5 and the pin of the connector 4 facing the functional circuit board 3 come into contact with each other to be electrically connected is instantaneous. Thirty
Is a control power supply for the switch 15.

FIG. 5 shows the waveform of each part when a simulation is performed with the configuration of FIG. FIG. 5A shows the timing of the signal for controlling the switch 15, that is, the output signal of the control power supply 30. The control power supply 30 controls the switch 15 so that the switch 15 becomes conductive 5 ns after the start of the simulation.

FIG. 5B shows the timing of the control signal of the switching element 11. Here, the control power source 31
Indicates that the switching element 11 is controlled so as to be conductive in 80 ns after the start of the simulation. Here, the time when the switching element 11 becomes conductive is set to the switch 15
Is separated from the time when the switch 1 is turned on by waiting until the bus waveform becomes stable after the switch 15 is turned on.
This is because interference between the control power supply 5 and the control power supply 31 is reduced.

Further, FIG. 5C shows a functional circuit board 3-3.
20 that models the functional circuit 10-3 mounted on the
3 shows a voltage waveform V (3) of −3. Furthermore, due to the influence of noise generated by the switch 15 being conductive,
The point where V (3) is the lowest is defined as V (3) min. FIG. 5D shows the functional circuit board 3 to be inserted.
2 shows a voltage waveform V (2) of the capacitor 20-2 modeling the functional circuit 10-2 of -2. Furthermore, the time τ from when the connector 4 comes into contact, that is, when the switch 15 becomes conductive to when it becomes 1-1 / e (63.2%) of the signal amplitude (5V in this case), that is, the definition of the time constant is shown. There is. here,
e is the base of the natural logarithm.

FIG. 6 shows voltage waveforms at various points when a simulation is performed with the precharge resistor 12 of 500Ω in the configuration of FIG. V (3) mi
n is 4.09 V, and the time constant τ of V (2) is 7.8.
It turns out that it is ns. FIG. 7 shows V (3) when the precharging resistor 12 is changed from 50Ω to 4KΩ.
The changes in min and τ are shown. Precharge resistor 1
It was found that the delay time τ increased almost linearly as the resistance value of 2 increased, but V (3) min gradually asymptotically approached to about 4.2V with a resistance larger than 500Ω.
That is, when the resistance value is 200Ω or less, the time constant is short, but the generated noise is large. Precharge resistor 12 is 200Ω
In this case, the generated noise is 1.42V (= 5−3.58V), and in the case of the TTL and C-MOS semiconductors, it is smaller than the input margin, so it can be seen that there is no problem. Therefore, the precharge resistor 12 is preferably 200Ω or more.

Further, the precharge resistor 12 is 500Ω
In the above case, the generated noise is 0.91V (= 5-4.09).
Since it is less than V), noise such as power supply ripples of about 0.5 V can be sufficiently tolerated, and it is desirable for high reliability.

On the other hand, in order to support the high speed bus, it is necessary to suppress the delay time τ to a value corresponding to the bus cycle Tclk or less. This is because the delay time τ becomes longer as the precharge resistor 12 becomes larger, and the stub voltage of the inserted function expansion board cannot follow the bus signal. From FIG. 7, the resistance value Rd of the precharge resistor 12 and the delay time τ
Since the relationship between and is linear, the relationship between the delay time τ and the resistance Rd and the electrostatic capacity C, which can be approximated to the series connection of Rd and the electrostatic capacity C, is expressed by the following equation.

V2 (t) = Eo (1-Exp (−t / τ)) (1) Here, the time function of V (2) is represented by V2 (t). Further, Eo is the output voltage of the output buffer 20-1 in FIG. Further, the time constant τ is τ = Rd · C, and
From this, it can be seen that the capacitance C is about 17.2 pF.

The wiring 13 of the inserted function expansion board 3-2
Since the voltage of −2 is delayed by the resistor 12, a large delay may cause a glitch on the bus. This is because when there is a delay that exceeds the bus cycle, the switching element 11 is turned on immediately after the bus cycle is switched, and the driver 20-1 immediately after the bus cycle is switched from data H to L or L. This is because the glitch noise is generated on the bus 1 because the voltage difference between the bus 1 and the wiring 13-2 remains large when the voltage changes to H. In order to reduce the bus glitch noise, the voltage of the wiring 13-2 needs to follow the bus signal voltage.

For that purpose, the potential V (2) of the wiring 13-2 needs to be at a bus potential, that is, a potential similar to the output voltage Eo of the output buffer 20-1 within the bus cycle Tclk. When the ratio of the potential V2 (Tclk) to Eo in the bus cycle Tclk is X, the following relationship holds. V2 (Tclk) = X * Eo (2) When Formula (2) is substituted into Formula (1) and rearranged, it becomes Rd = Tclk / (C * Log (1 / (1-X))) (3). By the relational expression given by the equation (3), the value of the precharging resistor 12 and the charging rate X of the wiring voltage with respect to the output voltage Eo of the output buffer are related within the time of the bus cycle Tclk.

For example, in the case of a 33 MHz high-speed bus, the bus cycle is 30 ns, and the capacitance C is the same as in FIG.
If the charging rate X is 7.2 pF and the charging rate X is designed to be 70% or more, the resistance 12 becomes 1.4 KΩ or less, and the charging rate X is 80% or less.
% Designing resistance 12 becomes 1.1KΩ or less,
If the charging rate is designed to be 90% or more, the resistance 12 becomes 750Ω or less, and if the charging rate is 95%, the resistance 12 becomes 582Ω or less.

Further, in the case of a 60 MHz bus, when the charging rate X is designed to be 70%, 80%, 90%, 95% or more,
The resistors 12 are 724Ω, 540Ω, 378Ω, and 2 respectively.
It becomes less than 91Ω. In practice, commercially available resistance values such as the E12 series are used, and values close to these are used.

In this way, the precharge resistor 1
2 is 200Ω or more, preferably 500Ω or more, and is obtained from the formula (3), that is, the operating frequency of the bus, the electrostatic capacity C of the functional circuit board to be hot-plugged, and the charging rate X.
By selecting the upper limit value of the resistance value of the resistor 12 obtained from the above, it is possible to optimally determine the noise generated during hot insertion and the delay related to the resistor 12.

Here, the length of the wiring 13-2 up to the bus connection and the input capacitance of the function expansion circuit 10 depend on the bus system and L
Since it depends on the SI package and the bus interface,
It may be larger or smaller than the value used here. However, even in this case, the optimum resistance R is calculated by the equation (3).
It is possible to obtain d12.

After the insertion of the connector is completed and the difference between the voltage of the bus 1 and the voltage of the wiring 13-2 becomes small, even if the switching element is turned on as shown in FIG. As shown, the change in V (3) is small and other functional circuit boards do not malfunction. Note that 80 ns in FIG. 5B is the time used as a simulation condition here, and may be any time after the voltage difference is sufficiently small. The above is a result of noise generated when the functional circuit board is inserted.However, when the functional circuit board is removed, there is no potential difference between the bus line and the line to be removed, so noise does not occur on the bus signal. , It does not cause malfunction.

By thus connecting the switching element 11 and the precharging resistor 12 in parallel, noise is generated on the bus even if the functional circuit board 3 is inserted into the connector 4 with the switching element 11 turned off. There is nothing to do. Moreover, even if the switching element 11 is turned on after the insertion, the potential difference between the bus and the line of the functional circuit is sufficiently reduced by the action of the precharging resistor 12, so that noise on the bus can be minimized. That is, the functional circuit board can be inserted without stopping or pausing the device and the bus in the device.

Since the switching element 11 is conducting when the functional circuit 10 is in an operable state, the delay generated by the switching element 11 and the precharging resistor 12 does not limit the speeding up of the bus. There is also the effect. That is, in the present embodiment, it is possible to achieve both high-speed bus and hot-swap.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram of the switching control means 14. Reference numeral 40 denotes a board insertion completion signal, which is generated by the user turning on a separately provided switch as in the first embodiment or by detecting the contact of an extremely short pin provided on the connector 4. The functional circuit board 3 is provided with input means (input terminal) for inputting the board insertion completion signal 40.

Generally, a synchronous bus has a clock line in addition to a data line, an address line, a control line, and data is transferred according to this clock. That is, data transmission or data reception is performed at the timing synchronized with the clock. For this reason, the system always has a clock distributor that generates and distributes clocks. Reference numeral 41 is a bus clock signal from this clock distributor, which is not shown in FIG. This clock distributor may be provided on the functional circuit board 3 or may be supplied from the back panel 5 via the connector 4. The functional circuit board 3 is provided with input means (input terminal) for inputting the bus clock 41.

Reference numeral 50 is a signal delay means for delaying the bus clock 41 by Δt seconds. Reference numeral 51 is a synchronizing means for synchronizing the board insertion completion signal 40 with a bus clock 41, and generates a control signal for the switching element 11 of 42. The synchronizing means 51 can be easily configured by a D flip-flop. Further, since the switching element control signal 42 controls the switching elements 11 provided on the plurality of signal lines, the switching element control signal 42 may be output via the buffer provided at the subsequent stage of the synchronization means 51.

FIG. 9 shows each timing when the functional circuit board is inserted. This figure shows (1) Functional circuit board 3
Is completed, (2) the power supply voltage of the functional circuit 10 is stabilized, and (3) the switching element 11 after the functional circuit 10 is reset by a reset signal provided for each functional circuit board and the reset is completed. 3 shows the timing of the control signal of. 9A shows a bus clock 41, FIG. 9B shows signals on the bus 1 in the back panel 5, and FIG. 9C shows a control signal 42 of the switching control means switching element 11. There is. The switching control means signal 42 (c) is generated by the synchronization means 51 and the delay means 50 with a delay of Δt seconds from the switching of the bus signal 1 (b).

The value of Δt will be described below. When the switching element 11 is turned on, the switching control signal 42
Is delayed but synchronized with the clock, the voltage V2 of the wiring 13 is the voltage of the bus 1, that is, the functional circuit 10.
The output voltage Eo of the driver is always charged (discharged) up to the voltage expressed by the equation (1). Therefore, when the switching element 11 is turned on, the voltage ratio between the bus 1 and the wiring 13 is as follows.

X = V2 (Δt + Tpzh) / Eo (4) Here, Tpzh is the time from when the switching element 11 inputs the switching control signal 42 until the bus 1 and the wiring 13 are brought into conduction, and this switching element 11 is C− M
Typical value when configured with OS is 1.5 to 6.5 ns
It is a degree.

When the time when the switching element 11 is turned on is immediately after the switching of the bus cycle, the voltage difference or voltage ratio between the bus 1 and the bus wiring 13 becomes maximum when the data on the bus 1 changes from L to H or from H to L. Therefore, a large bass glitch is generated. Therefore, Δt needs to be before the bus switching at the time when the switching element 11 becomes conductive, and to minimize the voltage difference or the voltage ratio.

Therefore, Δt is equal to Δt and the switching element 1
The value obtained by adding the switching time (Tpzh) of 1 and the system clock skew is controlled to be shorter than the bus cycle Tclk. Here, the clock skew means the phase time difference of the clocks supplied to all the functional circuits connected to the bus 1, and is generally about 10% of the bus cycle at maximum. Specifically, when the bus cycle is 30 ns, Δt is 30 ns to Tpzh.
(1.5 to 6.5 ns) and the system clock skew (3 ns), which is about 10% of the bus cycle, is subtracted 2
It is within 5.5 to 20.5 ns. Further, when the switching control signal 42 is long or the delay of the synchronizing means 51 is long, the propagation delay time of this signal is subtracted. If the wiring of this switching control signal 42 is about 12 cm, it will be about 1 n.
s.

When the bus cycle is 15 ns, Δ
t is within 12 to 7 ns, which is obtained by subtracting Tpzh (1.5 to 6.5 ns) from 15 ns and the system clock skew (1.5 ns) which is about 10% of the bus cycle.
Similarly, when the switching control signal 42 is long, or when the delay of the synchronizing means 51 is long, it is necessary to subtract the propagation delay time of this signal. By controlling in this way, the switching element 11 can be brought into conduction after charging or discharging the wiring 13 in synchronization with the clock without exceeding the bus cycle Tclk, so that the bus glitch noise applied to the bus 1 can be minimized without fail. effective.

Next, the precharge resistor Rd12 will be described. Bus 1 immediately before switching element 11 is turned on
The voltage ratio of the wiring 13 takes a value represented by the equation (4) when an average value is taken although there is a variation in the clock skew.
This voltage ratio X indicates the charging rate at the time Δt + Tpzh, and the resistance Rd12 changes depending on this charging rate X and the capacitance C of the wiring 13, which is arranged by substituting the equation (4) into the equation (1). It is obtained by doing.

Rd = (ΔT + Tpzh) / (C · Log (1 / (1-X))) (5) For precharging when the switching element 11 is synchronized with the clock by the relational expression given by the expression (5). The value of the resistor 12 is associated with the charging rate X of the wiring voltage with respect to the output voltage Eo of the output buffer.

The switching element 11 is (Δt + Tpz
Even if the power is turned on in h), the charging rate X causes the bus 1
Since the voltage difference between the wiring 13 and the wiring 13 is different, the bus glitch related to conduction is different. That is, if the switching element 11 is turned on when the charge is not sufficient, the waveform becomes as shown in FIG. The relationship between the resistance Rd12 and bass glitch noise is shown below. The noise margin Vnm of the input circuit of the functional circuit is defined by the following equation.

VnmH = Voh. min-Vih. min (6) VnmL = Vil. max-Vol. max (7) Here, Voh. min is the minimum output voltage of H data, Vo
l. max is the maximum output voltage of L data. Similarly V
il. max is the maximum input threshold voltage of L data,
Vih. min is the minimum input threshold voltage for H data. VnmH = for a typical TTL interface
0.7V (= 2.7-2.0V), VnmL = 0.3V
(= 0.8-0.5V). Typical 3.3V C
-For MOS interface VnmH = 1.35V
(= 3.0-1.65V), VnmL = 0.67V (=
1-0.33V).

Bus glitch noise Vnoise generated when the switching element 11 is conductive is caused by the bus 1 and the wiring 13.
In proportion to the voltage difference of Vh = 5V from FIG. 7, the resistance Rd = 0
Since the generated noise when Ω is 4 V, the voltage difference between the bus 1 and the wiring 13 when the charging rate is X is Eo * (1-X), and therefore the following relationship holds.

5: 4 = Eo * (1-X): Vnoise (8) In the case of TTL, Eo, that is, the output voltage VoH of the bus interface circuit is 3.5V, and Vnoise is to be kept below the noise margin, that is, Vnoise < Since Vnml = 0.3 (9), X is 89.5% or more according to the equation (8).

For example, in the case of a 33 MHz high-speed bus, the bus cycle is 30 ns, and the capacitance C is the same as in FIG.
In the case of 7.2 pF, if the charging rate is designed to be 90% or more, the resistance 12 becomes 750Ω or less, and if the charging rate is 95%, the resistance 12 becomes 582Ω or less. Further, in the case of a 60 MHz bus, when the charging rate X is designed to be 90% or 95% or more, the resistance 12 becomes 378Ω or 291Ω or less, respectively. In practice, commercially available resistance values such as the E12 series are used, and values close to these are used.

In this way, when the MOS type transistor switching element is used, the resistor 1 for precharge is used.
2 is 200Ω or more, preferably 500Ω or more, and 750Ω or less if the bus cycle is 30 ns, preferably 58.
2Ω or less, 200 if the bus cycle is 15ns
It is preferably Ω or more and 378 Ω or less, and optimally 291 Ω or less.

When the capacitance C of the wiring 13 of the functional circuit board 3 to be hot-swapped has a value other than 17.2 pF,
Alternatively, when the bus operating frequency and the input noise margin are different from those in the above configuration, the resistance 1 is calculated using the equations (4) to (8).
It is possible to select the upper limit value of the resistance value of 2, and thereby it is possible to optimally determine the noise generated during hot insertion and the delay related to the resistor 12.

Further, in FIG. 1, the switching element 11
Even if the resistor 12 and the switching controller 14 are provided on the back panel 5 side, the same effect can be obtained. In addition, as another effect, in a system having an existing back panel bus that does not have a hot-swap function, the functional circuit board is not changed, and the hot-swap circuit, that is, the resistor 12, the switching element 11, and the switching circuit is provided on the back panel 5. A system that can be hot-swapped by simply adding the control means 14 can be easily constructed.

By synchronizing the conduction timing of the switching element 11 with the bus clock 41 by the switching control means 14, the bus 1 on the back panel 5 at the time of insertion is synchronized.
Since it is possible to surely reduce the potential difference of the wiring (lead-out line) 13 on the functional circuit board 3 to be inserted, it is possible to completely minimize the noise generated on the bus, and an electronic information processing apparatus such as a computer. The reliability of can be improved more and more. As a result, there is an effect that the functional circuit can be inserted without stopping or suspending the electronic information processing apparatus such as a computer and the bus in the apparatus.

Further, since the switching element 11 is conducting when the functional circuit 10 is in an operable state, the delay generated by the switching element 11 and the precharging resistor 12 does not limit the bus speedup. . That is, it is possible to achieve both high bus speed and hot-swap while maintaining high reliability.

Next, an embodiment applied to a fault tolerant computer will be described with reference to FIG.
That is, 101 to 104 are CPUs. 111, 11
A bus bridge 2 connects the CPUs 101 to 104, the main memories 121 and 122, and the system buses 201 and 202 to each other. Further, 141 and 142 are I / O buses 2.
RAID disks 11 and 212 are cross-connected, and 151 and 152 are communication function modules connected to the buses 211 and 212. Reference numerals 131 and 132 are bus bridges. These are duplicates of a two-system system consisting of the same parts, and this is intended to improve the fault tolerance by providing redundancy.

In a system having such a configuration, hot plugging and unplugging can be performed by adding the parallel-connected resistors, switching elements and their control circuits of the present invention to the functional modules connected to the buses 201, 202, 211 and 212. Can be realized. As a result, the defective module can be removed and a new function can be added even when the system is energized and operating. This can be applied to mission-critical systems where system down is not allowed, such as accounting systems, automatic ticketing / reservation systems, and exchanges. In addition to the system configuration shown in FIG. 10, the main memory and CP are connected to the system bus.
Even if U is directly connected, the same function can be provided.

[0080]

According to the present invention, noise generation due to contact of a connector and conduction of a switching element can be suppressed, so that an electronic information processing apparatus such as a computer and a bus in the apparatus can be stopped or suspended. Without
It becomes possible to insert the functional circuit board into the bus.

Further, according to the present invention, when the functional circuit is in the operable state, the switching element is in conduction, so that there is an effect that the bus speed is not limited.

Further, according to the present invention, it is possible to prevent the generation of noise when the functional circuit board is removed, so that the hot wire can be removed.

That is, according to the present invention, in an electronic information processing apparatus such as a computer, it is possible to achieve both high bus speed and hot-swap, and to improve processing performance and reliability.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an outline of a first embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a hot-swap circuit in a conventional example.

FIG. 3 is a diagram showing voltage waveforms at respective points in the configuration of FIG.

FIG. 4 is a diagram showing an equivalent circuit of a circuit according to the first exemplary embodiment of the present invention.

5 is a diagram showing timing in the circuit configuration shown in FIG.

6 is a diagram showing voltage waveforms in the circuit configuration according to the first example shown in FIG. 4;

FIG. 7 is a diagram showing a correlation between bus noise and delay time when the precharging resistor according to the first embodiment of the present invention is changed.

FIG. 8 is a diagram showing a schematic configuration of a switching control means that is a second embodiment according to the present invention.

9 is a diagram showing timings in the switching control means shown in FIG.

FIG. 10 is a configuration diagram showing an embodiment in which the present invention is applied to a fault tolerant computer.

Front Page Continuation (72) Inventor Ryoichi Kurihara 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture Office Office Systems Division, Hitachi, Ltd. (72) Masao Inoue 810 Shimoimaizumi, Ebina City, Kanagawa Hitachi Office Systems Business, Inc. (56) Reference JP-A-6-125261 (JP, A) JP-A-5-34242 (JP, A) JP-A-6-112807 (JP, A) JP-A-6-161606 (JP, A) ) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 3/00

Claims (8)

(57) [Claims] 1. A data transfer system including a bus for transferring data, comprising: a functional circuit; a set of a resistor and a switching element connected in parallel on an input / output signal path of the functional circuit; And a switching control means for synchronizing and controlling conduction by using a delay clock obtained by delaying a bus clock used for data transfer of the bus by a delay of the bus clock period or less, and a functional circuit board comprising: A data transfer system, wherein a circuit board is formed so that it can be inserted into and removed from the bus by a connector terminal connected to one end of a set of a resistor and a switching element connected in parallel. 2. A data transfer system including a bus for transferring data, comprising: a functional circuit; a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit; And a switching control means for synchronizing and controlling the conduction by using a delay clock obtained by delaying a bus clock used for data transfer in the bus by the bus clock period or less, and a functional circuit board comprising: A data transfer system, wherein a circuit board is formed so that it can be inserted into and removed from the bus by a connector connected to the precharging resistor and the switching element connected in parallel. 3. A data transfer system including a bus for transferring data, comprising a functional circuit and a set of a precharging resistor and a switching element which are provided on an input / output signal path of the functional circuit and are connected in parallel. And a switching control means for controlling conduction of the switching element based on a board insertion completion signal, the functional circuit board comprising the parallel connected resistor and switching element. A data transfer system, wherein the connector terminal is connected to one end of the bus so that it can be inserted into and removed from the bus. 4. A data transfer system comprising a bus for transferring data, comprising: a functional circuit; a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit; Switching control means for synchronizing conduction using a delay clock obtained by delaying a bus clock used for data transfer in the bus by the bus clock cycle or less, and controlling based on a board insertion completion signal. A data transfer system having a substrate, wherein the functional circuit substrate is formed so that it can be inserted into and removed from the bus by a connector connected to the precharging resistor and the switching element connected in parallel. 5. A computer system in which a bus for transferring data is connected to a computer, the functional circuit, and a set of a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit, And a switching control means for synchronizing and controlling the conduction of the switching element by using a delay clock obtained by delaying a bus clock used for data transfer of the bus by the bus clock period or less. The computer system is characterized in that the functional circuit board is formed so as to be insertable into and removable from the bus by a connector terminal connected to one end of a pair of a resistor and a switching element connected in parallel. 6. A substrate in a data transfer system including a bus for transferring data, comprising a functional circuit, a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit, and the switching. Switching control means for synchronizing and controlling the conduction of elements by using a delay clock obtained by delaying a bus clock used for data transfer in the bus by the bus clock period or less, the precharge connected in parallel A hot-swap functional circuit board, wherein the hot-swap functional circuit board is formed so that it can be inserted into and removed from the bus by a connector connected to a resistance for use and a switching element. 7. A substrate in a data transfer system comprising a bus for transferring data, comprising a functional circuit, a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit, and the switching. A switching control means for synchronizing the conduction of the elements by using a delay clock obtained by delaying a bus clock used for data transfer in the bus by the bus clock period or less, and controlling it based on a board insertion completion signal; A hot-swap functional circuit board, which is formed so that it can be inserted into and removed from the bus by a connector connected to the precharging resistor and a switching element connected in parallel. 8. A backplane bus substrate for a data transfer system having a bus for transferring data, comprising a functional circuit, a precharging resistor and a switching element connected in parallel on an input / output signal path of the functional circuit. And a switching control means for synchronizing and controlling the conduction of the switching element by using a delay clock obtained by delaying a bus clock used for data transfer in the bus by the bus clock period or less. A backplane bus for a data transfer system, characterized in that the functional circuit board can be inserted into and removed from the bus by a connector connected to the precharge resistor and the switching element connected in parallel. substrate.