JP3431446B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a DRAM, and more particularly to a circuit for generating a step-down potential used as an internal power supply of the semiconductor integrated circuit.

[0002]

2. Description of the Related Art With the miniaturization of elements and wirings constituting a semiconductor integrated circuit, their withstand voltage characteristics have become a problem in recent years. As one of the methods for compensating the reliability of the withstand voltage characteristic, a method of reducing the electric field applied to each element and reducing the current generated in the wiring by using a potential lower than the external power supply voltage as the internal power supply. Is used. A circuit that generates such an internal step-down potential (hereinafter referred to as a step-down circuit) can be roughly classified into two types of circuits that have been used so far.

One circuit uses a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) as an element for driving a step-down potential. The step-down potential is constantly monitored, and when the step-down potential fluctuates from a set potential, this Feedback is applied to the gate potential of the PMOS transistor according to the amount of fluctuation to control the step-down potential. The other circuit uses an N-channel MOS transistor (hereinafter referred to as an NMOS transistor), supplies a constant boosted potential to the gate of an NMOS transistor having a very large gate width, and uses this in the subthreshold region. As a result, a stable step-down potential is supplied even with a large load current.

FIG. 5 shows a step-down circuit using a PMOS transistor as an element for driving a step-down potential (VINT in the figure). The step-down circuit includes a PMOS transistor P1, an operational amplifier circuit OP1, and two high resistance elements R1. , R2.

More specifically, the PMOS transistor P1
Has a source connected to the external power supply potential VEXT, a drain connected to the internal power supply potential VINT, and a gate connected to the node VG1. The operational amplifier circuit OP1 has a positive input terminal connected to the node VFB1, a negative input terminal connected to the node VREF1, and an output terminal connected to the node VG1.
It controls the gate potential of the transistor P1. The high resistance element R1 is connected between the internal power supply potential VINT and the node VFB1, the high resistance element R2 is connected between the node VFB1 and the ground potential VSS, and the internal power supply potential VINT is connected.
Accordingly, the intermediate potential reflecting the ratio of the resistance values of the two high resistance elements R1 and R2 described above is supplied to the node VFB1.

Further, it is assumed that the output terminal of some reference potential generating circuit is connected to the node VREF1 and is always kept at a stable reference potential when the external power supply is on.

In the above structure, when the internal power supply potential VINT has almost no load current, the output node VG1 of the operational amplifier circuit OP1 is connected to the operational amplifier circuit O1.
The potentials of the node VREF1 and the node VFB1 connected to the two input terminals of P1 are stabilized at a potential such that they are equal. According to the potential of the output node VG1, the current supplied from the external power supply potential VEXT to the internal power supply potential VINT via the PMOS transistor P1 is determined, which determines the potential of the internal power supply potential VINT. Here, when the load current of the internal power supply potential VINT increases and the external power supply potential VINT transiently slightly decreases, the resistance element R1,
The potential of the node VFB1 also drops slightly according to the resistance ratio of R2. The operational amplifier circuit OP1 is connected to this node VF.
When a decrease in the potential of B1 is detected, this fluctuation is amplified and
Feedback is applied so that the potential of the node VG1 decreases.

As a result, the current supplied to the internal power supply potential VINT via the PMOS transistor P1 increases,
The potential of the internal power supply potential VINT gradually recovers. By constantly monitoring the potential through such a feedback path, the internal power supply potential VINT is set to a predetermined potential.

FIG. 6 shows a typical step-down characteristic of the configuration shown in FIG. 5. The internal power supply is provided in the range of V1 <VEXT <V2 so that the integrated circuit performs a constant operation in the operation guaranteed voltage region. The characteristic is set so that the potential VINT becomes approximately Va. Here, the reference potential V of the voltage characteristic as shown in the figure
Using REF1, the internal power supply potential VINT is set to be about twice that. Further, here, Va = 2.
5V, V1 = 2.5V, V2 = 3.75V, and the voltage at the boundary between the voltage region A and the voltage region B is 3V.

Here, in the voltage region B in which the potential difference between the external power supply potential VEXT and the internal power supply potential VINT is large, the potential difference between the source and the drain of the PMOS transistor P1 in FIG. 5 is large (here, 0.5 V or more, for example, the external power supply potential). When VEXT is 3.3V, the internal power supply potential is 2.5
V), since the drop of the node VG1 due to the feedback via the node VFB1 also becomes large, the external power supply potential V
A sufficient supply current from EXT to internal power supply potential VINT can be secured. Therefore, even if the load current of the internal power supply potential VINT becomes large, the internal power supply potential VINT can be maintained at the desired potential as shown by the solid line in FIG.

On the other hand, in the voltage region A in which the potential difference between the external power supply potential VEXT and the internal power supply potential VINT is small, that is, when the potential difference between the source and the drain of the PMOS transistor P1 is small (here, less than 0.5 V), the characteristic is PMOS. The current in transistor P1 is either cut off or negligible. If the load current of the internal power supply potential VINT is small in the standby state of the integrated circuit, the charge can still be sufficiently supplemented and the internal power supply potential VINT can be maintained at a substantially desired potential. When the load current of VINT becomes 100 times or more that in the standby state, the decrease of the node VG1 due to the feedback via the node VFB1 is small, so that the sufficient current cannot be supplied to the internal power supply potential VINT. As a result, the internal power supply potential VINT becomes a potential lower than the set value in order for the PMOS transistor P1 to supply a sufficient current. This decrease becomes remarkable when the external power supply potential VEXT is around 2.8V. As a result, the internal power supply potential VINT has the characteristics shown by the broken line in FIG. 6 when the load current is large.

FIG. 7 shows an element for driving a step-down potential,
A step-down circuit using an NMOS transistor,
Two NMOS transistors N1 and N2 and a booster circuit P
P1, an operational amplifier circuit OP2, and two high resistance elements R
3, R4 and a large-capacity capacitor C1.

Here, the NMOS transistor N1 has a very large gate width (W = 10 4 μm), the source is the internal power supply potential VINT, and the drain is the external power supply potential VEX.
T is connected, and the gate is connected to the node VG2. The booster circuit PP1 has an input terminal connected to the node Q and an output terminal connected to the node VG2, and supplies a boosted potential to the node VG2 or a node VG2 depending on the state of the node Q.
Does nothing to The operational amplifier circuit OP2 has a node VREF2 at its positive input terminal and a node VFB at its negative input terminal.
2 is connected, and the node Q is connected to the output terminal to control the booster circuit PP1.

The NMOS transistor N2 has a gate and a drain connected to the node VG2 and a source connected to the node C. The high resistance element R3 is connected between the N-channel MOS transistor N2 and the node VFB2, the high resistance element R4 is connected between the node VFB2 and the ground potential VSS, and the two high resistance elements are connected according to the potential of the node VG2. The intermediate potential that reflects the ratio of the resistance values of the resistance elements R3 and R4 is V
Supply to FB2. The large-capacity capacitor C1 is a node V
It is connected between G2 and the ground potential VSS, and is connected to the node VG2.
Has a function of keeping the potential of the above constant with respect to the ground potential VSS. Further, it is assumed that the node VREF2 is always kept at a stable reference potential in the state where the output terminal of any reference potential generating circuit is connected and the external power supply is activated.

In the above structure, VG2 is currently set to a potential lower than the set value. At this time, the potential of the node VFB2 is lower than the potential of the node VREF2, and the operational amplifier circuit OP2 amplifies this potential difference and outputs the "1" level to the node Q. In response to this, the booster circuit PP1
Operates to boost the voltage of the node VG2. Node VG2
When the potential of the node VFB2 gradually rises, the potential of the node VFB2 accordingly rises while reflecting the resistance ratio of the high resistance elements R3 and R4, and when the potential of the node VREF2 is exceeded, the operational amplifier circuit OP2 becomes This potential difference is amplified and a "0" level is output to the node Q. In response to this, the booster circuit PP1 is stopped, and the boosting of the node VG2 ends.

In this way, the node VG2 is boosted to the set value and kept constant by the capacitor C1. At this time, the resistance of the resistor element R is set so that the potential of the node VG2 becomes sufficiently higher than the external power supply potential VEXT as shown below.
The resistance ratio of R3 and R4 is set, and this boosted node V
NMOS transistor N1 whose gate is connected to G2
Always becomes conductive, and charges are always supplied to the external power supply potential VINT except when VEXT = VINT.
Moreover, because the gate width is extremely large,
Even when the potential difference between the source and the drain of the OS transistor N1 is small, the absolute amount of charges supplied is sufficient.

FIG. 8 shows a typical step-down characteristic when the circuit described in FIG. 7 is used. For the same reason as in the case of FIG. 6, the reference potential VREF having the voltage characteristic as shown in FIG.
2 is used to set the boosted potential VG2, whereby the potential of the internal power supply potential VINT for each load current is determined. The characteristic indicated by the broken line in FIG. 8 is when the integrated circuit is in the active state and the load current of the internal power supply potential VINT is large. In this case, since the electric charge supplied from the NMOS transistor N1 to the internal power supply potential VINT is sufficiently consumed in the circuit, the potential of the internal power supply potential VINT is V1 <VE.
In the voltage region of XT <V2, VINT = Va, and the desired voltage characteristic is stabilized. Here, V1 = 2.5V, V2 =
3.75V, Va = 2.5V, Vb = 3.75-4.0
V.

On the other hand, when the load current of the internal power supply potential VINT is small while the integrated circuit is in the standby state, the current supplied from the NMOS transistor N1 becomes excessive, so that the internal power supply potential VINT is raised and the external power supply potential VEXT.
The potential difference between and decreases. As a result, the supply current of the NMOS transistor N1 decreases, and the internal power supply potential VINT is raised until it becomes in a state of being balanced with the load current as shown by the solid line in FIG.

[0019]

In the step-down circuit using the PMOS transistor as the element for driving the internal power supply potential VINT, the integrated circuit is particularly suitable in the region where the power supply voltage is low and the potential difference between the external power supply and the step-down power supply is small. When the load current of the internal power supply potential VINT is large in the active state, PM
Internal power supply potential VIN due to insufficient capacity of OS transistor
The decrease in T potential becomes remarkable. As a result, there is a problem in that the operation threshold value of each circuit is deviated and a malfunction occurs in the circuit, or the operation speed of each circuit decreases.

Further, in the step-down circuit using the NMOS transistor as the element for driving the internal power supply potential VINT, the current supply capability becomes excessive in a region where the external power supply voltage is high and the potential difference between the external power supply and the step-down power supply is large. There are drawbacks. Especially when the load current of the internal power supply step-down power supply is small when the integrated circuit is in the standby state, the potential difference between the external power supply potential VEXT and the internal power supply potential VINT becomes small, and the supply current decreases until the load current is balanced. , The internal power supply potential VINT is greatly raised. As a result, there is a problem that the operation threshold of each circuit shifts, the circuit malfunctions, and the current consumption in the standby state increases.

The semiconductor integrated circuit of the present invention has been made by paying attention to such a problem. The purpose of the semiconductor integrated circuit is to use two types of step-down circuits according to the voltage range, thereby providing a wide voltage range. It is an object of the present invention to provide a semiconductor integrated circuit capable of supplying a stable internal step-down potential regardless of the magnitude of current consumption during both standby and activation of the integrated circuit.

[0022]

To achieve the above object, a semiconductor integrated circuit according to the first invention comprises a first power supply step-down circuit using a P-channel MOS transistor as a step-down potential driving element, and a step-down step. N as a potential driving element
The second power supply step-down circuit using the channel MOS transistor and the voltage level of the external power supply are higher than a predetermined level.
In this case, only the first power supply voltage down circuit is operated,
When the voltage level of the external power supply is lower than the specified level
Is a combination of the first power supply voltage down circuit and the second power supply voltage down circuit.
And switching means for switching to operate .

In the semiconductor integrated circuit according to the second invention, the switching means includes a first reference potential generating circuit, a second reference potential generating circuit, a third reference potential generating circuit,
A first operational amplifier having a second input for receiving the output of the first input and the second reference potential generating circuit for receiving an output of said first reference potential generating circuit, the first operating < An amplifier output terminal is connected to one input terminal, and the other input terminal of this NAND circuit is connected to its output terminal.
Connected to receive the boosted potential of the output of the NAND circuit
It receives the first input terminal and the output of the third reference potential generating circuit.
A second operational amplifier having a second input terminal, the output potential of the first reference potential generation circuit being lower than the output potential of the second reference potential generation circuit , and
The boosted potential of the output of the NAND circuit generates the third reference potential.
When the potential is lower than the potential of the circuit, the NAND circuit is "L".
When the second power supply step-down circuit is activated in response to the output of the level and the output potential of the first reference potential generating circuit is higher than the output potential of the second reference potential generating circuit. Then, the NAND circuit outputs "H" level,
Receiving les, the second power supply step-down circuit is deactivated
It

A semiconductor integrated circuit according to a third invention is the semiconductor integrated circuit according to the second invention, wherein the first reference potential generating circuit comprises a PMOS transistor, and the source of the PMOS transistor is the external device. The drain is connected to the power supply potential, the drain is connected to the ground potential through the first resistor, and the gate is the second resistor whose one end is connected to the internal power supply potential and the third resistor whose one end is connected to the ground potential. Is connected to the connection point that connects the resistor and the resistor in series.

The semiconductor integrated circuit according to a fourth aspect of the invention is the semiconductor integrated circuit according to the third aspect of the invention, wherein the ratio of the resistance value of the second resistor to the resistance value of the third resistor is The difference between the second external power supply voltage and the potential of the gate is adjusted to be the threshold voltage of the PMOS transistor.

A semiconductor integrated circuit according to a fifth aspect of the present invention is the semiconductor integrated circuit according to the second aspect, wherein the second reference potential generating circuit is composed of a bandgap reference circuit.

[0027]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit according to an embodiment of the present invention. The semiconductor integrated circuit of the present embodiment has a PMOS transistor P11 and two NMOSs.
Transistors N21 and N22 and three operational amplifiers OP
11, OP21, OP22 and NAND circuit NAND21
A booster circuit PP21, a large capacity capacitor C21,
It is composed of four high resistance elements R11, R12, R21 and R22.

More specifically, the PMOS transistor P1
1, the source is connected to the external power supply potential VEXT, the drain is connected to the internal power supply potential VINT, and the gate is connected to the node VG1.
1 is connected. The operational amplifier circuit OP11 has a node VFB11 at its positive input terminal and a node VREF1 at its negative input terminal.
1 is connected, and the node VG11 is connected to the output terminal to control the gate potential of the PMOS transistor P11. The high resistance element R11 is connected between the internal potential VINT and the node VFB11, and the high resistance element R12 is connected between the node VFB11 and the ground potential VSS.
Two high resistance elements R1 according to the internal power supply potential VINT,
An intermediate potential that reflects the ratio of the resistance values of R2 is supplied to VFB11. Then, these three elements P11, R11, R
12 and one operational amplifier circuit OP11 enable PMOS
One step-down circuit using the transistor P11 as a drive element is configured.

The NMOS transistor N21 has a source connected to the internal power supply potential VINT, a drain connected to the external power supply potential VEXT, and a gate connected to the node VG21. The booster circuit PP21 has a node Q at the input end,
The node VG21 is connected to the output terminal, and depending on the state of the node Q, the boosted potential is supplied to the node VG21, or nothing is done to the node VG21. The operational amplifier OP21 has a positive input terminal connected to the node VREF22, a negative input terminal connected to the node VFB23, and an output terminal connected to the node A.

The operational amplifier circuit OP22 has a positive input terminal connected to the node VREF21, a negative input terminal connected to the node VFB21, and an output terminal connected to the node B. In the NAND circuit NAND21, the node A is connected to one input end, the node B is connected to the other input end, and the node Q is connected to the output end, so that the node B is connected to the input end of the booster circuit PP21 and the output is By connecting the node Q to the end, the booster circuit PP21 is controlled. The NMOS transistor N22 is
Node VG21 for gate and drain, node C for source
Are connected. The high resistance element R21 is an N channel M
The high resistance element R22 is connected between the OS transistor N22 and the node VFB21, the high resistance element R22 is connected between the node VFB21 and the ground potential VSS, and the resistance values of the two high resistance elements R21 and R22 are changed according to the potential of the VG21. An intermediate potential reflecting the ratio is supplied to VFB21. The large-capacity capacitor C21 is connected between the node VG2 and the ground potential VSS, and the potential of the node VG21 is set to the ground potential VSS.
To keep constant against.

The above-mentioned five elements N21, N22, R2
1, R22, C21 and two circuits OP22 are NMOS
One step-down circuit using the transistor N21 as a drive element is configured.

It is assumed that the nodes VREF11 and VREF21 are connected to the output terminals of some reference potential generating circuits and are kept at different reference potentials when the external power supply is on. . A bandgap reference circuit is connected to the node VREF22 as a reference potential generation circuit capable of generating a stable voltage level having no temperature dependence or voltage dependence, and is connected to the node VR.
A reference potential generation circuit having the following configuration is connected to the EF 23. These three reference potential generating circuit, a NAND circuit NAND21 and an operational amplifier O P21 described above Oh
The pair amplifier OP22 constitutes a switching means.

FIG. 2 is a diagram showing the configuration of a reference potential generating circuit connected to VREF 23, which is a PMOS transistor P100 and three resistors R100, R101, R102.
Composed of and. This PMOS transistor P100
Is connected to the external power supply potential VEXT, and the drain is connected to the ground potential VSS via the resistor R102. One end of the resistor R100 is connected to the internal power supply potential VINT, and one end of the resistor R101 is connected to the ground potential VSS. The other ends of the resistors R100 and R101 are connected in series, and the gate of the PMOS transistor P100 is connected to this connection point. Here, the internal power supply potential VIN
In order to reduce the through current from T or the external power supply potential VEXT to the ground potential VSS, the resistors R100, R101,
R102 having a high resistance value is used.

Further, the resistance values A and R101 of the resistor R100
And the resistance value B of the resistance value A is ΔV = external power supply potential VEXT−gate voltage Vgate of the PMOS transistor P100 = threshold voltage Vth of the PMOS transistor P100 when the external power supply potential VEXT = 3.0V. The ratio of the resistance value B is adjusted. By this, PM
Since the OS transistor P100 turns OFF / ON at VEXT = 3V, the characteristic of VREF23 rises sharply around 3.0V and rises depending on the external power supply potential VEXT, as shown in FIG. Resistance ratio A: B
Becomes equal to the ratio of ΔVa: ΔVb in FIG.
The reason why such a characteristic curve is used as the characteristic of VREF23 is that it intersects with the characteristic of VREF22, which will be described later, when the external power supply potential VEXT is approximately 3 V so that the magnitude relationship between the two characteristics is switched before and after this. Is.

Next, the operation of the semiconductor integrated circuit of this embodiment having the above-mentioned configuration will be described in two cases with reference to FIG. In FIG. 4, Va = 2.5V, V1 =
2.5V, V2 = 3.75V, and the voltage at the boundary between the voltage region A and the voltage region B is 3V. (A) Low Power Supply Voltage Region (Voltage Region A in FIG. 4) First, on the step-down circuit side using the PMOS transistor P11 as a driving element, the output node VG11 of the operational amplifier circuit OP11 is a node VRE connected to two input terminals.
It stabilizes at a potential such that the potentials of F11 and node VFB11 are equal. PM according to the potential of this node VG11
External power supply potential VEXT via the OS transistor P11
Determines the current supplied to the internal power supply potential VINT.
However, the external power supply potential VEXT and the internal power supply potential VI are
In the voltage region A where the potential difference of NT is small, the potential difference between the source and the drain of the PMOS transistor P11 is small, and the potential of the node VG11 is close to the external power supply potential VEXT. Therefore, the current of the PMOS transistor P11 is cut off due to its characteristics. Yes or little.

On the other hand, on the step-down circuit side using the NMOS transistor N21 as a driving element, in the voltage region A, the operational amplifier circuit OP21 has the positive input terminal potential VREF22.
Is higher than the potential VREF23 at the negative input terminal, a "1" level is output to the node A. Here, node VG21
When There is lower than the set value voltage, the potential of the node VFB21 has become lower than the potential of the node VREF21, the operational amplifier circuit OP2 2 Node B to amplify the potential difference
The "1" level is output to. NAND circuit NAND21
Receives the fact that both the node A and the node B are at "1" level, outputs "0" level to the node Q. In response to this, the booster circuit PP21 operates to boost the node VG21. Then, when the potential of the node VG21 gradually rises, the potential of the node VFB21 accordingly rises while reflecting the resistance ratio of the high resistance elements R21 and R22, and eventually exceeds the potential of VREF21. OP2 2 amplifies the potential difference, the node B "0" and outputs the level. In response to this, the NAND circuit NAND21 outputs the "1" level to the node Q, the booster circuit PP21 receives this and stops, and the boosting of the node VG21 ends. In this way, the node VG21 is boosted to the set value and kept constant by the capacitor C21.

At this time, the resistance ratio of the resistance elements R21 and R22 is set so that the potential of the node VG21 becomes sufficiently higher than the external power supply potential VEXT as shown in FIG. 4, and the boosted node VG21 has a gate. The NMOS transistor N21 connected to is always conductive and always supplies the electric charge to the internal power supply potential VINT except when VEXT = VINT.

As described above, in the region where the power supply voltage is low (voltage region A in FIG. 4), PM is used as the drive element of the step-down potential.
The first power supply voltage down circuit using the OS transistor P11 and the second power supply voltage down circuit using the NMOS transistor N21 as the driving element of the step-down potential are operated.
The transistor N21 is the PMOS transistor P11.
Since the current supply capacity is overwhelmingly higher than that, the NMOS transistor becomes dominant with respect to the supply current regardless of the magnitude of the load current, and a stable step-down potential is supplied. (B) High Power Supply Voltage Region (Voltage Region B in FIG. 4) In this voltage region B, the operational amplifier circuit OP21 has a positive input terminal potential VREF22 and a negative input terminal potential VRE.
Since it is lower than F23, the "0" level is output to the node A, and the NAND circuit NAND21 receives this and receives the node B.
Regardless of the state, the "1" level is always output to the node Q, and the booster circuit PP21 receives this and stops the boosting operation. As a result, the node VG21 is only connected to the ground potential VSS via the NMOS transistor N22 and the high resistance elements R21 and R22, so that the potential becomes the ground potential VSS and the node VG21 is connected to the gate N.
The MOS transistor N2 is completely cut off.

On the other hand, on the step-down circuit side using the PMOS transistor P11 as a driving element, the state is the same as in the voltage region A, but in the region where the potential difference between the external power supply potential VEXT and the internal power supply potential VINT is large like the voltage region B. PMOS
Since the potential difference between the source and drain of the transistor P11 is large, and the potential of the node VG11 is greatly reduced by the feedback via the node VFB11, the current of the PMOS transistor P11 is characteristically the internal power supply potential VI.
It is supplied according to the fluctuation of NT and supplies a stable step-down potential.

As described above, in the region where the power supply voltage is high (voltage region B in FIG. 4), PM is used as the driving element for the step-down potential.
Only the power supply step-down circuit that uses the OS transistor P11 is operated, and the power supply step-down circuit that uses the NMOS transistor N21 as a step-down potential drive element is completely stopped.

To summarize the above, in the present embodiment, only the power supply step-down circuit using the PMOS transistor P11 is operated according to the external power supply voltage, that is, when the power supply voltage is high. On the other hand, when the power supply voltage is low, the power supply step-down circuit using the NMOS transistor N21 and the power supply step-down circuit using the PMOS transistor P11 are switched so as to operate together. Therefore, in a wide voltage range, regardless of the magnitude of the load current. A stable step-down potential can be supplied.

When the external power supply voltage is 3.3V,
A threshold value is provided, and only the power supply step-down circuit using the PMOS transistor P11 is operated with an external power supply voltage higher than this threshold value, and if the power supply voltage is lower than the threshold value, the NMOS transistor N21 is used. Only the power supply voltage down circuit may operate.

Furthermore, when 2.5 V is used as the external power supply voltage, the operation of the power supply voltage down circuit using the PMOS transistor P11 is completely stopped, and the power supply voltage is high. It is also possible to operate only the power supply voltage down circuit using the NMOS transistor N21 even in the low region.

[0045]

As described above, according to the present invention, it is possible to supply a stable internal step-down potential in a wide voltage range regardless of the magnitude of the load current during standby and during activation of the integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a reference potential generation circuit connected to VREF23.

3 is a diagram showing a characteristic curve of VREF 23 obtained by the configuration of FIG.

FIG. 4 is a diagram for explaining the operation of the semiconductor integrated circuit of this embodiment.

FIG. 5 is a diagram showing a configuration of a step-down circuit when a PMOS transistor is used as an element that drives a step-down potential.

6 is a diagram showing a typical step-down characteristic of the configuration shown in FIG.

FIG. 7 is a diagram showing a configuration of a step-down circuit when an NMOS transistor is used as an element that drives a step-down potential.

8 is a diagram showing a typical step-down characteristic of the configuration shown in FIG.

[Explanation of symbols]

P11 ... PMOS transistor, N21, N22 ... NMOS transistors, OP11, OP21, OP22 ... Operational amplifier, NAND21 ... NAND circuit, PP21 ... Booster circuit, C21 ... Large-capacity capacitor, R11, R12, R21, R22 ... High resistance elements.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-78471 (JP, A) JP-A-4-212786 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/4074 G11C 11/417

Claims (5)

(57) [Claims] 1. A P-channel M as a driving element for a step-down potential.
A first power supply voltage down circuit using an OS transistor, a second power supply voltage down circuit using an N-channel MOS transistor as a driving element of a voltage step down potential, and an external power supply voltage level higher than a predetermined level.
Activates only the first power supply voltage down circuit,
If the voltage level of the source is lower than the predetermined level, then
Operates both the first power supply voltage down circuit and the second power supply voltage down circuit
A semiconductor integrated circuit, comprising: a switching unit that switches so that 2. The switching means includes a first reference potential generating circuit, a second reference potential generating circuit, and a third reference potential generating circuit.
And raw circuit, a first operational amplifier having a second input for receiving the output of the first input and the second reference potential generating circuit for receiving an output of said first reference potential generating circuit, the
To the NAND circuit in which the output terminal of the first operational amplifier is connected to one input terminal, and to the other input terminal of this NAND circuit,
The output terminal of the NAND circuit is connected to the booster voltage of the output of the NAND circuit.
A first input terminal for receiving the voltage and the third reference potential generating circuit
Second input having a second input for receiving the output of
; And a flop, the output potential of the first reference potential generating circuit is lower than the output potential of the second reference potential generating circuit, and the nan
The boosted potential of the output of the switching circuit is the third reference potential generating circuit.
If the potential is lower than the potential of the
The second power supply step-down circuit is activated in response to the output, and the output potential of the first reference potential generation circuit is higher than the output potential of the second reference potential generation circuit. In the above
Command circuit outputs "H" level, in response to this, the semiconductor integrated circuit according to claim 1, wherein the second voltage step-down circuit is deactivated. 3. The first reference potential generating circuit is a PMOS
A source of the PMOS transistor is connected to the external power supply potential, a drain of the PMOS transistor is connected to the ground potential via a first resistor, and a gate of the PMOS transistor is connected to the internal power supply potential at a second end; 3. The semiconductor integrated circuit according to claim 2, wherein the resistor and a third resistor whose one end is connected to the ground potential are connected in series to each other. 4. The ratio of the resistance value of the second resistor and the resistance value of the third resistor is such that the difference between the second external power supply voltage and the potential of the gate is 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is adjusted to have a threshold voltage. 5. The semiconductor integrated circuit according to claim 2, wherein the second reference potential generating circuit comprises a bandgap reference circuit.