JP3428934B2 - Vehicle speed signal input circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vehicle speed signal input circuit, and more particularly to a vehicle speed signal input circuit for inputting a vehicle speed signal to a device such as an on-vehicle navigation device or a car audio device which is controlled by using the vehicle speed signal.

[0002]

2. Description of the Related Art In-vehicle navigation devices, car audio devices, electronic control units (ECU devices), etc., use a vehicle speed signal output from a vehicle speed signal circuit, which is indicative of the speed of the vehicle, to travel distance and speed. After obtaining information, etc., the current position is detected, and the volume control and traveling control are performed according to the traveling speed. Then, the vehicle-mounted navigation device sends the vehicle speed signal to the GPS.
A GPS receiver that receives radio waves from a satellite and a gyro sensor are used in combination to detect the current location with high accuracy and guide the vehicle. As described above, the vehicle speed signal is used in various devices, and the vehicle speed signal is roughly classified into a digital vehicle speed signal 10 and an analog vehicle speed signal 11. The vehicle speed detection sensor that generates the digital vehicle speed signal 10 includes a contact sensor and an optical sensor. The contact sensor electrically turns on / off the reed switch each time the shaft of the vehicle rotates. The type sensor is to make a hole in a disk attached to a shaft of a car, pass light through the hole each time the shaft rotates, and receive the light to electrically detect ON / OFF. The signal that drives the output of this vehicle speed detection sensor is the digital vehicle speed signal 10
As a drive circuit, there is an open collector circuit type vehicle speed sensor drive circuit shown in FIG. On the other hand, the vehicle speed detection sensor that generates the analog vehicle speed signal 11 includes a magnetic sensor and a power generation sensor, and the magnetic sensor detects a magnetic field generated by a groove formed in a rotor that rotates in accordance with the rotation of the vehicle. The generation is detected as a sine wave signal, and the power generation type sensor detects a sine wave signal by rotating a generator by rotation of a shaft of a vehicle. This sine wave signal is the analog vehicle speed signal 11 (the vehicle speed can be detected depending on the state of this sine wave signal).

As an example of the digital vehicle speed signal 10, (A) T1 vehicle speed signal input terminal waveform shown in FIG. 4 is a waveform of a signal obtained by driving the output of the vehicle speed detection sensor by the vehicle speed sensor drive circuit shown in FIG. A pulse waveform that sometimes becomes 15 V and becomes 0 V when off is shown, and the frequency of this pulse shows the vehicle speed. In this vehicle speed sensor drive circuit, since the resistor R16 is pulled up to the vehicle battery voltage (VBAT), fluctuations in the battery voltage occur in the pulse of the vehicle speed signal as shown in FIG. 4 (A) T1 vehicle speed signal input terminal waveform (a). It overlaps as shown in. Further, as an example of the analog vehicle speed signal 11, the (D) T1 vehicle speed signal input terminal waveform shown in FIG. 6 changes in voltage amplitude and frequency depending on the speed of the vehicle, and a high frequency part indicates a high speed part and a high voltage part indicates a high speed part. It indicates that there is.

FIG. 13 is a block diagram showing an example of a vehicle speed signal input circuit compatible with both the digital vehicle speed signal and the analog vehicle speed signal 11, which is disclosed in Japanese Patent Application Laid-Open No. 9-126806. When a DC (direct current) component is given as an offset to the input vehicle speed signal, the DC cut circuit 23 cuts off the offset. The limiter circuit 24 limits the voltage amplitude of the input vehicle speed signal. The amplifier circuit 25 is a part that amplifies the input signal to a binarizable level. The voltage dividing circuit 26 is applied only to the digital vehicle speed signal 10, and attenuates the voltage amplitude of the input signal when the input determination unit 22 determines that the digital vehicle speed signal 10 is input. The high frequency removing circuit 29 removes chattering of the digital signal, and is connected when the input determining unit 22 determines that the digital vehicle speed signal 10 is input. The changeover switch 27 selects an output that does not pass through the voltage dividing circuit 26 when the input determination unit 22 determines that the analog vehicle speed signal 11 is input, and the input determination unit 22 selects the digital vehicle speed signal 1
When it is determined that 0 is input, the output is switched through the voltage dividing circuit 26. The change-over switch 28 connects the high-frequency removing circuit 29 in parallel when the input determining unit 22 determines that the digital vehicle speed signal 10 is input. Two
The binarization circuit 30 is a circuit that binarizes the analog vehicle speed signal 11 or the digital vehicle speed signal 10 output from the amplifier circuit 25 and makes the level constant.

The operation of the vehicle speed signal input circuit circuit that can handle both the digital vehicle speed signal 10 and the analog vehicle speed signal 11 shown in FIG. 13 will be described. When the (A) T1 vehicle speed signal input terminal waveform of FIG. 4 which is the digital vehicle speed signal 10 is input to the vehicle signal input terminal (SP), the input determination unit 22 determines that the vehicle speed signal is the digital vehicle speed signal 10. The CPU switches the output through the voltage dividing circuit 26 with the changeover switch 27, and connects the high frequency removing circuit 29 in parallel with the changeover switch 28. As a result, the digital vehicle speed signal 10 is D
The C-cut circuit 23 cuts the offset, and the limiter circuit 24 limits the voltage amplitude in order to keep the input maximum rating of the amplifier circuit 25. After that, the signal is amplified by the amplifier circuit 25, but is divided by the voltage divider circuit 26, and
The noise of (a) is attenuated to a level that cannot be detected by the next binarization. At this time, the attenuation amount is a level at which the digital vehicle speed signal 10 can be detected. Finally 2
The digitizing circuit 30 converts the digital signal into a digital signal that can be determined by the CPU. Next, when the (D) T1 vehicle speed signal input terminal waveform of FIG. 6 that is the analog vehicle speed signal 11 is input to the vehicle signal input terminal (SP), the input determination unit 22 determines that the vehicle speed signal is the analog vehicle speed signal 11. To be done. The voltage amplitude and frequency of the analog vehicle speed signal 11 change depending on the speed of the vehicle, and the voltage amplitude and frequency decrease at low speed. Therefore, the changeover switch 27 selects an output that does not pass through the voltage dividing circuit 26 and is detected even at low speed. It can be so. Further, in the case of the analog vehicle speed signal 11, the noise is smaller than that of the digital vehicle speed signal 10.
Separate 9 As a result, the analog vehicle speed signal 11 is D
Since the offset is cut by the C-cut circuit 23 and the voltage amplitude increases in the limiter circuit 24 when the speed is high, the voltage amplitude is limited in order to keep it within the maximum input rating of the amplifier circuit 25. Since the voltage amplitude of the amplifier circuit 25 is small at low speed, the analog vehicle speed signal 11 is amplified to a level at which the analog vehicle speed signal 11 can be detected even at low speed. Finally, in the binarization circuit 30, like the digital vehicle speed signal 10, it is converted into a digital signal that can be determined by the CPU.

In the digital vehicle speed signal 10 driven by the vehicle speed sensor drive circuit shown in FIG. 3, the resistance R16 of the drive circuit causes the battery voltage (VBAT) of the vehicle.
4A, the fluctuation of the battery voltage is superimposed as shown in FIG. 4A of the T1 vehicle speed signal input terminal waveform. In this vehicle speed sensor drive circuit, when the vehicle is stopped, noise due to the battery voltage fluctuation is superimposed on the waveform near the battery voltage of the vehicle as shown in FIG. 5 (B) T1 vehicle speed signal input terminal waveform (a). Or the transistor Q1 shown in (b) of FIG.
The noise is small in the waveform near V. In this case, the input determination unit 22 cannot determine the digital vehicle speed signal 10 and the analog vehicle speed signal 11 only from the vehicle speed signal input from the vehicle speed signal input. Therefore, in the vehicle-mounted navigation device using this circuit, it is difficult to determine with the vehicle speed signal input circuit of FIG. 13 using the absolute position and the traveling speed obtained by calculating the radio wave from the GPS satellite with the GPS receiver. It is determined whether the vehicle is running or stopped.

[0007]

SUMMARY OF THE INVENTION The above-described conventional vehicle speed signal input circuit is provided with a determination by an input determination unit when a vehicle speed signal input circuit that can operate both a digital vehicle speed signal and an analog vehicle speed signal is realized. Since it is necessary to switch the vehicle speed signal processing circuit, an input determination unit for determining whether the input signal is a digital vehicle speed signal or an analog vehicle speed signal is required. There is a problem that the two-system processing circuit is required. Further, when the input is a digital vehicle speed signal, depending on the vehicle speed sensor drive circuit used, when the vehicle is stopped, noise due to battery voltage fluctuation is superimposed on the waveform near the battery voltage of the vehicle. Since it is in the state of being on or the noise is small in the waveform near 0V, there is a problem that it is not possible to judge whether it is the digital vehicle speed signal or the analog vehicle speed signal only by the inputted vehicle speed signal.

The object of the present invention is to eliminate such a drawback of the prior art, so that an input judging unit for judging whether the input signal is a digital vehicle speed signal or an analog vehicle speed signal is not required, and a digital vehicle speed signal for switching is used. There is no need for two processing circuits, one for and one for the analog vehicle speed signal. Another object of the present invention is to provide a vehicle speed signal input circuit that can process an input vehicle speed signal even when the vehicle is stopped, regardless of the vehicle speed sensor drive circuit used.

[0009]

SUMMARY OF THE INVENTION A first vehicle speed signal input circuit of the present invention includes a limit circuit for receiving a vehicle speed signal and limiting a positive amplitude and a negative amplitude of the vehicle speed signal, respectively, and a DC of the limited vehicle speed signal. A DC cut circuit for removing a component, a bias circuit for biasing the vehicle speed signal from which the DC component is removed to a predetermined level, and a clamp circuit for clamping the biased vehicle speed signal within a predetermined amplitude range. , And are configured.

The first vehicle speed signal input circuit of the present invention comprises a comparator for converting the vehicle speed signal clamped by the clamp circuit into two level signals.

A second vehicle speed signal input circuit according to the present invention includes a limit circuit for receiving a vehicle speed signal and limiting the positive and negative amplitudes of the signal, and a DC cut for removing the DC component of the limited vehicle speed signal. A circuit, a bias circuit that biases the vehicle speed signal from which the DC component has been removed to a predetermined level, a clamp circuit that clamps the biased vehicle speed signal within a predetermined amplitude range, and the clamped And a low-pass filter that removes frequency components above a predetermined frequency from the vehicle speed signal.

The second vehicle speed signal input circuit of the present invention comprises a comparator for converting the vehicle speed signal from which the frequency components higher than a predetermined frequency have been removed into two level signals.

The vehicle speed signals received by the limit circuits of the first vehicle speed signal input circuit and the second vehicle speed signal input circuit of the present invention are digital vehicle speed signals or analog vehicle speed signals.

Further, the limit circuits of the first vehicle speed signal input circuit and the second vehicle speed signal input circuit of the present invention limit the positive amplitude of the digital vehicle speed signal to remove noise. With respect to the analog vehicle speed signal, the negative amplitude is cut off by leaving a predetermined voltage, and the positive amplitude is limited.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a vehicle speed signal input circuit of the present invention.

In the present embodiment shown in FIG. 1, a limit circuit 3 for receiving a vehicle speed signal which is a digital vehicle speed signal 10 or an analog vehicle speed signal 11 and limiting the positive and negative amplitudes of the signal, respectively, and the limited vehicle speed signal. DC cut circuit 4 for removing the DC (direct current) component of B, and bias circuit 5 for biasing the vehicle speed signal from which the DC component is removed to a predetermined level.
(Thus, the vehicle speed signal waveform has an amplitude around the bias point and is biased to a level necessary for determination by the comparator 8), and the clamp circuit 6 that clamps the biased vehicle speed signal within a predetermined amplitude range. (By this, the voltage is clamped within the safe operating voltage range of the circuit while maintaining the voltage amplitude sufficient for the judgment by the comparator 8 and the like.)
And a low-pass filter 7 (which removes a noise component of a frequency sufficiently higher than the vehicle speed signal) for removing frequency components of a clamped vehicle speed signal that are higher than a predetermined frequency, and a frequency that is higher than the predetermined frequency. It is composed of a comparator 8 for converting the vehicle speed signal from which the components have been removed into a signal of two levels for input to the port or interrupt terminal of the CPU 9.

The limit circuit 3 uses a digital vehicle speed signal 10
The positive amplitude is restricted by removing the noise by removing the noise and the analog vehicle speed signal 11 is restricted by cutting the negative amplitude by leaving a predetermined voltage.

The clamp circuit 6 clamps the vehicle speed signal biased by the bias circuit 5 to a predetermined level with two different voltages so that the amplitude of the vehicle speed signal falls between these two voltages. The voltage amplitude sufficient for judgment by the comparator 8 etc. can be maintained).

Note that FIG. 1 also shows a CPU 9 for detecting a vehicle speed by inputting signals of two levels from the comparator 8 to a port or an interrupt terminal. Then, the CPU 9 uses a vehicle speed signal (two-level signal) indicating the speed of the vehicle output from the vehicle speed signal circuit mounted on the vehicle,
A CPU 9 such as an in-vehicle navigation device, a car audio device, an electronic control unit (ECU device), etc. for performing current position detection, volume control according to traveling speed, and traveling control, respectively is shown.

Next, the operation of the vehicle speed signal input circuit of the present embodiment will be described in detail with reference to FIGS. 2 to 9.

FIG. 2 is a diagram showing an example of a concrete vehicle speed signal input circuit.

FIG. 3 is a diagram showing an example of a vehicle speed sensor drive circuit for driving the output of the digital vehicle speed sensor.

FIG. 4 is a diagram showing an example of a digital vehicle speed signal driven by the circuit shown in FIG. This signal is input to the vehicle speed signal input terminal 2 (T1) of the vehicle speed signal input circuit 1.

FIG. 5 is a diagram showing an example of a digital vehicle speed signal when the vehicle driven by the circuit shown in FIG. 3 is stopped. This signal is input to the vehicle speed signal input terminal 2 (T1) of the vehicle speed signal input circuit 1.

FIG. 6 is a diagram showing an example of the analog vehicle speed signal. This signal is input to the vehicle speed signal input terminal 2 (T1) of the vehicle speed signal input circuit 1.

FIG. 7 is a diagram showing an example of a process of processing a digital vehicle speed signal by the vehicle speed signal input circuit.

FIG. 8 is a diagram showing an example of a process of processing the digital vehicle speed signal when the vehicle is stopped by the vehicle speed signal input circuit.

FIG. 9 is a diagram showing an example of a process of processing an analog vehicle speed signal by the vehicle speed signal input circuit.

In FIG. 1, a vehicle speed signal input terminal 2 (S
Input from P). The vehicle speed signals are roughly classified into a digital vehicle speed signal 10 and an analog vehicle speed signal 11, and the vehicle speed sensor drive circuit in the digital vehicle speed signal 10 is shown in FIG.
There is an open collector circuit type shown in. In the drive circuit shown in FIG. 3, the resistor R16 is connected to the vehicle battery voltage (VB
Since it is pulled up to AT), the fluctuation of the battery voltage is superimposed on the pulse of the vehicle speed signal as shown in (a) of the T1 vehicle speed signal input terminal waveform in FIG. 4 (A). In this vehicle speed sensor drive circuit, when the vehicle is stopped,
(B) As shown in (a) of the T1 vehicle speed signal input terminal waveform, noise due to battery voltage fluctuation is superimposed on the waveform near the battery voltage of the vehicle, or the transistor Q1 shown in FIG. It is turned on, and the noise is small in the waveform near 0V. The analog vehicle speed signal 11 is shown in FIG.
(D) As shown in the T1 vehicle speed signal input terminal waveform, when the rotation of the shaft is low, both the voltage amplitude and the frequency are low, and when the rotation is high, both the voltage amplitude and the frequency are high.

Description will be made with reference to FIG. 2 which is an example of a concrete circuit of the vehicle speed signal input circuit corresponding to the block diagram shown in FIG. First, for example, a digital vehicle speed signal 10 shown in FIG. 4 driven by the vehicle speed sensor drive circuit shown in FIG.
The case where is input will be described. The waveform of the T1 vehicle speed signal input terminal waveform shown in FIG. 4 (A) input from the vehicle speed signal input terminal 2 shown in FIG. 2 is shown in (E) T1 vehicle speed signal input terminal waveform of FIG. This waveform corresponds to the limit circuit 3 shown in FIG.
(For example, the resistor R1, the diode D1, and the diode D2
(R) and diode D1 (F)
Like the T2DC limit waveform, + 8V (actually, if the forward voltage drop of the diode is 0.6V, + 8V
Is + 8.6V), and the noise component is cut. After that, the DC component is removed by the DC cut circuit 4 (for example, the coupling capacitor C1), and + is generated by the bias circuit 5 (for example, composed of the resistor R2 and the resistor R3).
Biased to a bias point of 4.15V, which is centered between 5V and + 3.3V. At this time, due to the value of the resistor R1 and the parallel value of the resistors R2 and R3, voltage attenuation occurs at A / (R1 + A) (= Equation 1) times (here, A = (R2 · R3) / (R2 + R3)). . In addition, the capacitor C1 and the resistors R2 and R
Cutoff frequency 1 / 2π ・ A ・ C1 (Hz) by 3
Since the high-pass filter of (= Equation 2) is formed, Equation 1
And Equation 2 need to be considered. That is, the cut-off frequency is set to, for example, 0.1 H so that the amplitude of the vehicle speed signal at a low speed does not reach an undetectable level in Expression 1 and the frequency at a low speed is detected in Expression 2.
It is necessary to consider such as z or less. After that, (G) T
The diode D3 of the clamp circuit 6 (for example, composed of the diode D3 and the diode D4) like the three-clamp waveform.
Is clamped to + 5V by the diode D4 of the clamp circuit 6 and is clamped to + 3.3V (actually,
If the forward voltage drop of the diode is 0.6V, +5
V becomes + 5.6V and + 3.3V becomes 2.7V).
The clamped waveforms are, for example, operational amplifiers IC1 and IC2,
The active low-pass filter 7 composed of the resistors R4, R5 and R6 and the capacitors C2 and C3 removes noise components having a frequency sufficiently higher than the vehicle speed signal (for example, 2 KHz or more). Then, in order to prevent the (G) T3 clamp waveform from malfunctioning due to noise, the resistors R7, R8,
R9 and R10 are converted to (H) T4 comparator output waveform by using comparator 8IC3 which has input hysteresis of 4.4V for high side hysteresis and 3.9V for low side hysteresis, and is converted to the port of CPU9 or interrupt terminal. Is output.

Next, when the vehicle is stopped, the vehicle is driven by the vehicle speed sensor drive circuit shown in FIG. 3, for example, as shown in FIG.
The case where the digital vehicle speed signal 10 shown in is input will be described. The waveform of the (B) T1 vehicle speed signal input terminal of FIG. 5 input from the vehicle speed signal input terminal 2 shown in FIG. 2 is shown in FIG.
The waveform of the (I) T1 vehicle speed signal input terminal is shown in FIG.
(A) and (b) correspond to the waveforms of (a) and (b) shown in FIG. 5, respectively. ). The (J) T2DC limit waveform is limited to + 8V (actually, if the forward voltage drop of the diode is 0.6V, + 8V becomes + 8.6V), and the noise component is cut. Then, the DC component is removed and biased to the bias point of 4.15V in the same manner as described above. After that, it is clamped to + 5V and + 3.3V like the (K) T3 clamp waveform, but as time goes by, it gradually approaches the bias point of + 4.15V from the + 5V side. After that, in the same manner as described above, the noise component having a frequency sufficiently higher than the vehicle speed signal is removed, and the comparator 8IC3
Is converted to the (L) T4 comparator output waveform by
It is output to the port of PU9 or an interrupt terminal. Here, in the output waveform of the (L) T4 comparator, the portion (a) is 0 V and is not affected by the noise component.

Next, the case where the analog vehicle speed signal waveform shown in FIG. 6 is input will be described. The waveform of the T1 vehicle speed signal input terminal shown in FIG. 6D is the waveform input from the vehicle speed signal input terminal 2 shown in FIG. 2 and the waveform of the (M) T1 vehicle speed signal input terminal shown in FIG. It has been postponed.) This waveform corresponds to the resistance R1 of the limit circuit 3 shown in FIG.
And the diodes D1 and D2, as in the (N) T2DC limit waveform, -0.6V (forward voltage drop of the diode D2) and + 8V (actually, if the forward voltage drop of the diode is 0.6V, + 8V Is + 8.6V). Here, the negative voltage is applied to the diode D2
However, in order to make it easier to detect a vehicle speed signal at a lower speed, the voltage is not cut at 0V in consideration of the fact that the voltage of this waveform becomes low when the vehicle is at a low speed. It is designed to leave -0.6V. Then DC
DC by the coupling capacitor C1 of the cut circuit 4
The bias point 4.15 which is the center of + 5V and + 3.3V by the resistors R2 and R3 of the bias circuit 5 after the components are removed.
Biased to V. At this time, as in the case of the digital vehicle speed signal waveform, the voltage is attenuated by the formula 1 and the high-pass filter of the formula 2 is formed. Therefore, it is necessary to consider the formula 1 and the formula 2. After that, the clamp circuit 6
(O) As in the T3 clamp waveform, the voltage amplitude at high speed is clamped to + 5V by the diode D3 and + 3.3V by the diode D4 (actually, if the forward voltage drop of the diode is 0.6V, it is + 5V.
Becomes + 5.6V and + 3.3V becomes 2.7V). The clamped waveform is the active low-pass filter 7
As a result, a noise component having a frequency sufficiently higher than the vehicle speed signal is removed. Then, the (O) T3 clamp waveform is applied to the resistor R.
7, R8, R9, and R10 are used to prevent malfunction due to noise by using a comparator 8IC3 having a high-level side hysteresis of 4.4 V and a low-level hysteresis of 3.9 V that can be sufficiently detected even at a low speed. ) Converted to a T4 comparator output waveform and output to the port of the CPU 9 or the interrupt terminal.

In the above description, in the circuit shown in FIG. 2, the secondary circuit composed of the operational amplifiers IC1 and IC2, the resistors R4, R5 and R6, and the capacitors C2 and C3 is used to remove noise components having a frequency sufficiently higher than the vehicle speed signal. An active low-pass filter was used, which is n (n = 1, 2, 3, ...)
It may be composed of the following active filters. Also, instead of this active filter, the resistor R11 of FIG.
It is also possible to use a passive filter composed of the capacitor C4 and the capacitor C4, or to use a structure in which these filters are not used. Further, in the circuit of FIG. 2, the resistors R7 and R
With 8, R9 and R10, the high-side hysteresis that can be sufficiently detected at low speed is 4.4 V, and the low-side hysteresis is 3.
Comparator 8IC with input hysteresis of 9V
3, the waveform is converted with a configuration in which malfunction due to noise is prevented and is output to the port of the CPU 9 or the interrupt terminal.
The analog value may be input to the A / D conversion input terminal of. Further, in the circuit of FIG. 2, + 8V or +5 is used as the power source.
V or + 3.3V is required, but if there is no power source of each voltage, instead of the diode D1 that determines the upper limit of + 8V, the upper limit of + 8V is output from the vehicle battery voltage (VBAT). A circuit may be used. In the upper limit output of FIG. 11, it is necessary to adjust the resistors R12 and R13 so that the output becomes + 8V.
Similarly, instead of the diode D3 that determines the upper limit of + 5V in FIG. 2, the circuit of FIG. 11 that outputs the upper limit of + 5V from the battery voltage (VBAT) of the vehicle may be used. With the upper limit output of this Fig. 11, + 5V
It is necessary to adjust the resistors R12 and R13 so that Then, instead of the diode D4 that determines the lower limit of + 3.3V, the vehicle battery voltage (VBAT)
May output the lower limit of + 3.3V from + 3.3V. With the lower limit output of this Fig. 12,
It is necessary to adjust the resistors R14 and R15 so that the voltage becomes + 3.3V. In the circuit of FIG. 2, the power source is +8
Although V, +5 V, and +3.3 V are required, these voltage values do not have to be used and may be freely combined. At that time,
It does not have to be three power sources.

[0035]

As described above, according to the vehicle speed signal input circuit of the present invention, the limit circuit receives the digital vehicle speed signal or the analog vehicle speed signal and limits the positive and negative amplitudes of the signal, respectively, and cuts the DC signal. The circuit removes the DC component of the vehicle speed signal limited by the limit circuit, the bias circuit biases the vehicle speed signal from which the DC component has been removed to a predetermined level, and the vehicle speed signal biased by the clamp circuit. Is clamped in a predetermined amplitude range, the vehicle speed signal clamped by the clamp circuit is converted into two level signals by the comparator, and the converted signals are input to the CPU. Therefore, the digital vehicle speed signal and the analog vehicle speed signal are input. When realizing a vehicle speed signal input circuit that can operate for both Not issue or analog speed signal or not required input determination unit determines the required two systems of processing circuit and digital speed signal and an analog speed signal. Further, even when the vehicle is stopped, the signal to be input to the CPU can be created only by the input vehicle speed signal, so that it is not necessary to judge whether it is a digital vehicle speed signal or an analog vehicle speed signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a vehicle speed signal input circuit of the present invention.

FIG. 2 is a diagram showing an example of a concrete vehicle speed signal input circuit.

FIG. 3 is a diagram illustrating an example of a vehicle speed sensor drive circuit that drives an output of a digital vehicle speed sensor.

4 is a diagram showing an example of a digital vehicle speed signal driven by the circuit shown in FIG.

5 is a diagram showing an example of a digital vehicle speed signal when a vehicle driven by the circuit shown in FIG. 3 is stopped.

FIG. 6 is a diagram showing an example of an analog vehicle speed signal.

FIG. 7 is a diagram showing an example of a process of processing a digital vehicle speed signal by a vehicle speed signal input circuit.

FIG. 8 is a diagram showing an example of a process of processing a digital vehicle speed signal when the vehicle is stopped by a vehicle speed signal input circuit.

FIG. 9 is a diagram showing an example of a process of processing an analog vehicle speed signal by a vehicle speed signal input circuit.

FIG. 10 shows a passive filter.

FIG. 11 is a diagram showing an upper limit circuit using a battery voltage (VBAT).

FIG. 12 is a diagram showing a lower limit circuit using a battery voltage (VBAT).

FIG. 13 is a block diagram showing an example of a vehicle speed signal input circuit that is compatible with both digital vehicle speed signals and analog vehicle speed signals.

[Explanation of symbols]

1 Vehicle speed signal input circuit 2 Vehicle speed signal input terminal 3 limit circuit 4 DC cut circuit 5 Bias circuit 6 Clamp circuit 7 Low-pass filter 8 comparator 9 CPU 10 Digital vehicle speed signal 11 Analog vehicle speed signal 22 Input judgment section 23 DC cut circuit 24 limiter circuit 25 amplifier circuit 26 voltage divider 27 Changeover switch 28 Changeover switch 29 High frequency removal circuit 30 binarization circuit

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Claims (7)

(57) [Claims] 1. A limit circuit that receives a vehicle speed signal and limits positive and negative amplitudes of the signal, and a DC that removes a DC component of the limited vehicle speed signal.
A cut circuit; a bias circuit for biasing the vehicle speed signal from which the DC component has been removed to a predetermined level; and a clamp circuit for clamping the biased vehicle speed signal within a predetermined amplitude range. Vehicle speed signal input circuit characterized by. 2. The vehicle speed signal input circuit according to claim 1, further comprising a comparator for converting the vehicle speed signal clamped by the clamp circuit into two level signals. 3. A limit circuit for receiving a vehicle speed signal and limiting positive and negative amplitudes of the signal, respectively, and a DC for removing a DC component of the limited vehicle speed signal.
A cut circuit, a bias circuit for biasing the vehicle speed signal from which the DC component has been removed to a predetermined level, a clamp circuit for clamping the biased vehicle speed signal in a predetermined amplitude range, and the clamp circuit A vehicle speed signal input circuit, comprising: a low-pass filter that removes a frequency component having a frequency higher than a predetermined frequency from the vehicle speed signal. 4. The vehicle speed signal input circuit according to claim 3, further comprising a comparator for converting the vehicle speed signal from which frequency components having a frequency equal to or higher than a predetermined frequency are removed into a signal of two levels. 5. The vehicle speed signal input circuit according to claim 1, wherein the vehicle speed signal received by the limit circuit is a digital vehicle speed signal or an analog vehicle speed signal. 6. The limit circuit limits the positive amplitude for the digital vehicle speed signal to remove noise, and leaves the negative amplitude for the analog vehicle speed signal by a predetermined voltage. The vehicle speed signal input circuit according to claim 5, wherein the positive amplitude is cut to limit the positive amplitude. 7. The clamp circuit clamps the vehicle speed signal biased to a predetermined level by the bias circuit at two different voltages so that the amplitude of the vehicle speed signal falls between these two voltages. The vehicle speed signal input circuit according to claim 1, 2, 3, 4, 5 or 6.