JP3427342B2 - Electronic circuit - Google Patents

Electronic circuit

Info

Publication number
JP3427342B2
JP3427342B2 JP11007997A JP11007997A JP3427342B2 JP 3427342 B2 JP3427342 B2 JP 3427342B2 JP 11007997 A JP11007997 A JP 11007997A JP 11007997 A JP11007997 A JP 11007997A JP 3427342 B2 JP3427342 B2 JP 3427342B2
Authority
JP
Japan
Prior art keywords
resistor
amplifier
inverting amplifier
electronic circuit
inverting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11007997A
Other languages
Japanese (ja)
Other versions
JPH10290124A (en
Inventor
紀行 関澤
龍彦 大熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kenwood KK
Original Assignee
Kenwood KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kenwood KK filed Critical Kenwood KK
Priority to JP11007997A priority Critical patent/JP3427342B2/en
Publication of JPH10290124A publication Critical patent/JPH10290124A/en
Application granted granted Critical
Publication of JP3427342B2 publication Critical patent/JP3427342B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は電子回路に関し、さ
らに詳細には増幅回路等を含む電子回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit, and more particularly to an electronic circuit including an amplifier circuit and the like.

【0002】[0002]

【従来の技術】従来の電子回路の一例としての増幅回路
は、例えば図3に示すように、演算増幅器A1の出力電
圧を抵抗R1と抵抗R2とによって分圧し、抵抗R1に
印加される分圧電圧を演算増幅器A1の反転入力端子に
印加して、非反転増幅回路を構成している。ここで、抵
抗R1と抵抗R2は増幅回路の閉利得を決定するための
抵抗である。
2. Description of the Related Art An amplifier circuit as an example of a conventional electronic circuit divides an output voltage of an operational amplifier A1 by a resistor R1 and a resistor R2 and divides the voltage applied to the resistor R1 as shown in FIG. A voltage is applied to the inverting input terminal of the operational amplifier A1 to form a non-inverting amplifier circuit. Here, the resistors R1 and R2 are resistors for determining the closed gain of the amplifier circuit.

【0003】上記したような従来の増幅回路を実際に回
路構成した場合、配線基板上のパターン、配線等による
抵抗やリアクタンスによるインピーダンスZが抵抗R1
とアースとの間に存在する。
When the conventional amplifier circuit as described above is actually constructed, the resistance Z due to the resistance due to the pattern or wiring on the wiring board and the impedance due to the reactance is the resistance R1.
Exists between the earth and the earth.

【0004】[0004]

【発明が解決しようとする課題】したがって入力電圧を
vi、出力電圧をvoとしたとき、上記した従来の増幅
回路の閉利得Gは、演算増幅器A1を入力インピーダン
ス無限大、裸利得無限大の理想演算増幅器として、次の
式(1)に示すようになる。
Therefore, when the input voltage is vi and the output voltage is vo, the closed gain G of the conventional amplifier circuit described above is ideal for the operational amplifier A1 having infinite input impedance and infinite gain. The operational amplifier is represented by the following equation (1).

【0005】 G=vo/vi=(R1+R2+Z)/(R1+Z)……(1)[0005]   G = vo / vi = (R1 + R2 + Z) / (R1 + Z) (1)

【0006】しかしながら式(1)から明らかなよう
に、実際に増幅回路を構成した場合に、未知のインピー
ダンスZが加わるために、正確な閉利得(閉利得を増幅
率とも記す)が得られないという問題点があった。
However, as is clear from the equation (1), when an amplifier circuit is actually constructed, an unknown impedance Z is added, and thus an accurate closed gain (closed gain is also referred to as an amplification factor) cannot be obtained. There was a problem.

【0007】さらに、この未知のインピーダンスZはそ
の値が周波数によって変動するため、増幅回路の閉利得
が入力電圧viの周波数によって変動するという問題点
があった。このため、実際に増幅回路を構成した場合
に、正確、かつ周波数によって変動しない閉利得が得ら
れないという問題点が生ずる。このように信号電流等が
流れる線路に未知の値を呈するインピーダンスなどがあ
る場合に、信号電流等が周波数によって変動させられる
という問題点があった。
Further, since the value of the unknown impedance Z varies depending on the frequency, the closed gain of the amplifier circuit varies depending on the frequency of the input voltage vi. For this reason, when the amplifier circuit is actually configured, there arises a problem that an accurate closed gain that does not fluctuate depending on the frequency cannot be obtained. Thus, there is a problem that the signal current or the like is changed depending on the frequency when there is an impedance or the like having an unknown value in the line through which the signal current or the like flows.

【0008】本発明は実際に電子回路を構成した場合に
線路における未知の値のインピーダンスなどによる信号
電流の周波数による変動を抑制する電子回路を提供する
ことを目的とする。
It is an object of the present invention to provide an electronic circuit that suppresses fluctuations in signal current due to frequency due to impedance of an unknown value in a line when the electronic circuit is actually constructed.

【0009】[0009]

【課題を解決するための手段】本発明の請求項1記載の
電子回路は、信号電流が流れる第1の抵抗と、第1の抵
抗の一端に接続された反転増幅器と、反転増幅器の出力
端と第1の抵抗の他端との間に接続した第2の抵抗とか
らなり、第2の抵抗の抵抗値を第1の抵抗の抵抗値の反
転増幅器の利得倍としたことを特徴とする。
According to a first aspect of the present invention, there is provided an electronic circuit comprising: a first resistor through which a signal current flows; an inverting amplifier connected to one end of the first resistor; and an output end of the inverting amplifier. And a second resistor connected between the other end of the first resistor and the second resistor, wherein the resistance value of the second resistor is the gain of the inverting amplifier multiplied by the resistance value of the first resistor. .

【0010】本発明の請求項1記載の電子回路によれ
ば、配線基板上のパターン、配線等による抵抗やリアク
タンスによるインピーダンスが第1の抵抗に直列に存在
していても、第1の抵抗の一端の電位が反転増幅器によ
って増幅されて、反転増幅器の出力の電圧は第2の抵抗
を介して第1の抵抗の他端に印加され、かつ第2の抵抗
の抵抗値が第1の抵抗の抵抗値の反転増幅器の利得倍に
されているために、周波数の変動により第1の抵抗を介
してインピーダンスに流れる電流と第2の抵抗を介して
インピーダンスに流れる電流とは、互いに打つ消され
て、信号電流はインピーダンスに無関係になって、周波
数によって影響されることはなくなる。
According to the electronic circuit of the first aspect of the present invention, even if the resistance due to the pattern on the wiring board, the wiring, or the impedance due to the reactance exists in series with the first resistance, The potential at one end is amplified by the inverting amplifier, the voltage of the output of the inverting amplifier is applied to the other end of the first resistor through the second resistor, and the resistance value of the second resistor is equal to that of the first resistor. Since the resistance is multiplied by the gain of the inverting amplifier, the current flowing through the first resistor into the impedance and the current flowing through the second resistor into the impedance due to frequency fluctuations cancel each other out. , The signal current becomes independent of impedance and is no longer affected by frequency.

【0011】本発明の請求項2記載の電子回路は、入力
電圧を増幅する増幅器と増幅器の出力電圧を分圧する第
1および第2の抵抗からなる分圧回路とを備えて第2の
抵抗の一端が増幅器の出力端に接続されかつ第1および
第2の抵抗の共通接続点が増幅器の反転入力端子に接続
されて第2の抵抗に印加される分圧電圧を増幅器の反転
入力端子に印加する非反転増幅回路と、増幅器の反転入
力端子の電圧を増幅する反転増幅器と、反転増幅器の出
力端と第1の抵抗の非共通接続端子との間に接続した第
3の抵抗とからなり、第3の抵抗の抵抗値を第1の抵抗
の抵抗値の反転増幅器の利得倍としたことを特徴とす
る。
An electronic circuit according to a second aspect of the present invention comprises an amplifier for amplifying an input voltage and a voltage dividing circuit including first and second resistors for dividing an output voltage of the amplifier, and a second resistor. One end is connected to the output end of the amplifier and the common connection point of the first and second resistors is connected to the inverting input terminal of the amplifier, and the divided voltage applied to the second resistor is applied to the inverting input terminal of the amplifier. A non-inverting amplifier circuit for amplifying the voltage at the inverting input terminal of the amplifier, and a third resistor connected between the output terminal of the inverting amplifier and the non-common connection terminal of the first resistor, It is characterized in that the resistance value of the third resistor is set to the gain of the inverting amplifier multiplied by the resistance value of the first resistor.

【0012】本発明の請求項2記載の電子回路によれ
ば、増幅回路を実際に回路構成した場合、配線基板上の
パターン、配線等による抵抗やリアクタンスによるイン
ピーダンスが第1の抵抗の非共通接続端子とアースとの
間に存在しても、周波数の変動により第1の抵抗を介し
てインピーダンスに流れる電流と第3の抵抗を介してイ
ンピーダンスに流れる電流とは、第3の抵抗の抵抗値が
第1の抵抗の抵抗値の反転増幅器の利得倍にされている
ために、互いに打つ消されて、増幅回路の閉利得Gはイ
ンピーダンスに無関係になって第1および第2の抵抗値
によって定まり、実際に増幅回路を構成した場合に、正
確、かつ周波数によって変動しない正確な閉利得が得ら
れることになる。
According to the electronic circuit of the second aspect of the present invention, when the amplifier circuit is actually configured, the resistance due to the pattern on the wiring board, the wiring, etc. and the impedance due to the reactance are the non-common connection of the first resistance. Even if it exists between the terminal and the ground, the current flowing through the first resistance into the impedance and the current flowing through the third resistance into the impedance due to frequency fluctuations have a resistance value of the third resistance. Since the resistance value of the first resistor is multiplied by the gain of the inverting amplifier, they cancel each other out, and the closed gain G of the amplifier circuit becomes independent of impedance and is determined by the first and second resistance values. When the amplifier circuit is actually configured, an accurate and accurate closed gain that does not vary depending on the frequency can be obtained.

【0013】[0013]

【発明の実施の形態】以下、本発明にかかる電子回路を
実施の一形態によって説明する。図1は本発明の実施の
一形態にかかる電子回路の構成を示すブロック図であっ
て、増幅回路の場合を例示している。
BEST MODE FOR CARRYING OUT THE INVENTION An electronic circuit according to the present invention will be described below with reference to an embodiment. FIG. 1 is a block diagram showing the configuration of an electronic circuit according to an embodiment of the present invention, and illustrates the case of an amplifier circuit.

【0014】本発明の実施の一形態にかかる電子回路
は、演算増幅器A1の出力電圧を抵抗R1と抵抗R2と
によって分圧し、抵抗R1に印加される分圧電圧を演算
増幅器A1の反転入力端子に印加して、非反転増幅回路
を構成すると共に、反転入力端子の電圧を利得〃1〃の
反転増幅器(利得〃−1〃の増幅器)A2に入力電圧と
して供給し、理想反転増幅器A2の出力電圧を抵抗R1
と同一の抵抗値を有する抵抗R3を介して抵抗R1の終
端に印加する。ここで、反転増幅器A2は入力インピー
ダンス無限大でかつ利得〃1〃の理想反転増幅器(入力
インピーダンス無限大でかつ利得〃−1〃の理想増幅
器)とみなせるものとする。
In the electronic circuit according to the embodiment of the present invention, the output voltage of the operational amplifier A1 is divided by the resistors R1 and R2, and the divided voltage applied to the resistor R1 is inverted input terminal of the operational amplifier A1. To form a non-inverting amplifier circuit and supply the voltage at the inverting input terminal to the inverting amplifier with gain 〃1〃 (amplifier with gain 〃-1〃) A2 as the input voltage to output the ideal inverting amplifier A2. Voltage is R1
Is applied to the terminal end of the resistor R1 via the resistor R3 having the same resistance value. Here, the inverting amplifier A2 can be regarded as an ideal inverting amplifier having an infinite input impedance and a gain of "1" (ideal amplifier having an infinite input impedance and a gain of "-1").

【0015】なお、Zは電子回路としての増幅回路を実
際に回路構成した場合、抵抗R1とアースとの間に存在
する、配線基板上のパターン、配線等による抵抗やリア
クタンスによるインピーダンスであり、Eは直流電源で
あり、演算増幅器A1および反転増幅器A2に電源電圧
を供給している。
In the case where an amplifier circuit as an electronic circuit is actually constructed, Z is an impedance due to a resistance or a reactance existing between the resistor R1 and the ground due to a pattern on the wiring board, wiring, etc., and E Is a DC power supply, which supplies a power supply voltage to the operational amplifier A1 and the inverting amplifier A2.

【0016】本発明の実施の一形態にかかる電子回路の
作用について説明する。以下の説明において、抵抗R
1、R2、R3の抵抗値もR1、R2、R3によって表
示する。
The operation of the electronic circuit according to the embodiment of the present invention will be described. In the following description, the resistance R
The resistance values of 1, R2 and R3 are also indicated by R1, R2 and R3.

【0017】入力電圧viが印加された場合、演算増幅
器A1の非反転入力端子と反転入力端子のイマジナリシ
ョートにより、b点すなわち反転入力端子の電位vbお
よび反転増幅器A2の出力端cの電位vcは、次の式
(2)及び式(3)に示すごとくである。
When the input voltage vi is applied, the potential vb at the point b, that is, the inverting input terminal and the potential vc at the output terminal c of the inverting amplifier A2 are caused by an imaginary short circuit between the non-inverting input terminal and the inverting input terminal of the operational amplifier A1. , As shown in the following equations (2) and (3).

【0018】 vb=vi …(2) vc=−vi …(3)[0018] vb = vi (2) vc = -vi (3)

【0019】抵抗R1と抵抗R3との接続点aの電位v
aは、式(1)および式(2)から次の式(4)に示す
ようになる。
The potential v at the connection point a between the resistors R1 and R3
a becomes as shown in the following Expression (4) from Expression (1) and Expression (2).

【0020】 va=[{(vb−va)/R1}+{(vc−va)/R3}]×Z =[{(vi−va)/R1}+{(−vi−va)/R3}]×Z …(4)[0020]   va = [{(vb-va) / R1} + {(vc-va) / R3}] × Z       = [{(Vi-va) / R1} + {(-vi-va) / R3}] * Z                                                   … (4)

【0021】式(4)からvaは、次の式(5)に示す
ようになる。
The equations (4) to va are as shown in the following equation (5).

【0022】 va={(1/R1)−(1/R3)}vi/{(1/Z)+(1/R1) +(1/R3)} …(5)[0022]   va = {(1 / R1)-(1 / R3)} vi / {(1 / Z) + (1 / R1)           + (1 / R3)} (5)

【0023】いま、R1=R3(>0)に設定してある
ため、式(5)からva=0となる。
Since R1 = R3 (> 0) is set now, va = 0 from the equation (5).

【0024】一方、抵抗R2に流れる電流をI2とし
て、入力電圧viと出力電圧voとの関係は、次の式
(6)と式(7)に示すようになる。
On the other hand, assuming that the current flowing through the resistor R2 is I2, the relationship between the input voltage vi and the output voltage vo is given by the following equations (6) and (7).

【0025】 vo=va+I2(R1+R2) …(6) I2=(vb−va)/R1 …(7)[0025] vo = va + I2 (R1 + R2) (6) I2 = (vb-va) / R1 (7)

【0026】式(6)へ式(2)、式(7)を代入し
て、voを求めると次の式(8)のようになる。
By substituting the equations (2) and (7) into the equation (6) and obtaining vo, the following equation (8) is obtained.

【0027】 vo=va+{(vi−va)/R1}×(R1+R2) …(8)[0027]   vo = va + {(vi-va) / R1} × (R1 + R2) (8)

【0028】しかるに、前記のようにR1=R3のとき
はva=0であるため、本発明の実施の一形態にかかる
電子回路を構成する増幅回路の閉利得は次の式(9)に
示す如くになる。
However, since va = 0 when R1 = R3 as described above, the closed gain of the amplifier circuit constituting the electronic circuit according to the embodiment of the present invention is expressed by the following equation (9). It becomes like

【0029】 vo/vi=(R1+R2)/R1 …(9)[0029]   vo / vi = (R1 + R2) / R1 (9)

【0030】式(9)から明らかなように、閉利得Gは
インピーダンスZに無関係になり、抵抗R1と抵抗R2
とによって定まることになって、実際に増幅回路を構成
した場合に、正確、かつ周波数によって変動しない正確
な閉利得が得られる。したがって、本発明の実施の一形
態にかかる電子回路を音声信号増幅回路として用いた場
合、音質を向上させることができる。
As is apparent from the equation (9), the closed gain G becomes independent of the impedance Z, and the resistors R1 and R2 are
Therefore, when the amplifier circuit is actually constructed, an accurate closed gain that does not fluctuate with frequency can be obtained. Therefore, when the electronic circuit according to the embodiment of the present invention is used as the audio signal amplifier circuit, the sound quality can be improved.

【0031】なお、上記した本発明の実施の一形態にか
かる電子回路において増幅器が演算増幅器A1の場合を
示したが、演算増幅器と異なる他の増幅器を用いてもよ
い。
Although the amplifier in the electronic circuit according to the embodiment of the present invention described above is the operational amplifier A1, another amplifier different from the operational amplifier may be used.

【0032】さらに、上記した本発明の実施の一形態に
かかる電子回路において、反転増幅器A2の利得を1と
し、抵抗R1=R3としたが、反転増幅器A2の利得を
n(nは正の実数)とし、抵抗R3の抵抗値を抵抗R1
の抵抗値のn倍としても同様である。
Further, in the electronic circuit according to the embodiment of the present invention described above, the gain of the inverting amplifier A2 is 1 and the resistance R1 = R3. However, the gain of the inverting amplifier A2 is n (n is a positive real number). ), And the resistance value of the resistor R3 is the resistance R1
The same applies when the resistance value of n is multiplied by n.

【0033】以下、本発明にかかる電子回路を実施の他
の形態によって説明する。図2は本発明の実施の他の形
態にかかる電子回路の構成を示すブロック図である。
The electronic circuit according to the present invention will be described below with reference to another embodiment. FIG. 2 is a block diagram showing the configuration of an electronic circuit according to another embodiment of the present invention.

【0034】本発明の実施の他の形態にかかる電子回路
は図2に示すように、非反転増幅器A4の出力端に抵抗
R4の一端を接続し、非反転増幅器A4にて増幅された
信号電流を抵抗R4に流す。一方、非反転増幅器A4の
出力端に利得nの反転増幅器A3を接続し、非反転増幅
器A4の出力端の電圧を反転増幅器A3によって増幅す
る。反転増幅器A3の出力端には、抵抗R4の抵抗値の
反転増幅器A3の利得n倍の抵抗値を有する抵抗R5の
一端が接続してあって、抵抗R5の他端を抵抗R4の他
端に接続して構成してある。
In an electronic circuit according to another embodiment of the present invention, as shown in FIG. 2, one end of a resistor R4 is connected to the output end of a non-inverting amplifier A4, and a signal current amplified by the non-inverting amplifier A4 is connected. To the resistor R4. On the other hand, an inverting amplifier A3 having a gain n is connected to the output end of the non-inverting amplifier A4, and the voltage at the output end of the non-inverting amplifier A4 is amplified by the inverting amplifier A3. The output terminal of the inverting amplifier A3 is connected to one end of a resistor R5 having a resistance value that is n times as high as the resistance value of the resistor R4, and the other end of the resistor R5 is connected to the other end of the resistor R4. Connected and configured.

【0035】配線基板上のパターン、配線等による抵抗
やリアクタンスによるインピーダンスZ1が、抵抗R4
の他端と抵抗R5の他端との共通接続点とアースとの間
に存在する。なお、図2においてEは直流電源を示し、
配線基板上のパターン、配線等による抵抗やリアクタン
スによるインピーダンスZ2を介して直流電源Eから非
反転増幅器A4および反転増幅器A3に電源電圧を供給
してある。
Impedance Z1 due to resistance due to the pattern on the wiring board, wiring, etc. and reactance is equal to resistance R4.
Exists between the common connection point of the other end of the resistor R5 and the other end of the resistor R5 and the ground. In addition, in FIG. 2, E represents a DC power source,
A power supply voltage is supplied from the DC power supply E to the non-inverting amplifier A4 and the inverting amplifier A3 via a resistance on the wiring board, resistance due to wiring, etc. and impedance Z2 due to reactance.

【0036】上記した本発明の実施の他の形態にかかる
電子回路において、非反転増幅器A4の出力端の電位に
基づいて抵抗R4を介して非反転増幅器A4によって増
幅された信号電流が流れ、この電流は周波数の変動によ
るインピーダンスの変化にしたがって影響を受けて変動
する。しかるに、抵抗R4に流れる電流に基づく電圧は
反転増幅器A3によってn倍に反転増幅されて、抵抗R
4の抵抗値の反転増幅器A3の利得n倍の抵抗値を有す
る抵抗R5に流れる。
In the electronic circuit according to another embodiment of the present invention described above, the signal current amplified by the non-inverting amplifier A4 flows through the resistor R4 based on the potential of the output terminal of the non-inverting amplifier A4, and this The current is affected and changes according to the change in impedance due to the change in frequency. However, the voltage based on the current flowing through the resistor R4 is inverted and amplified n times by the inverting amplifier A3, and
The resistance value of No. 4 flows into the resistor R5 having a resistance value of n times the gain of the inverting amplifier A3.

【0037】したがって、本発明の実施の他の形態にか
かる電子回路においても、本発明の実施の一形態にかか
る電子回路の場合と同様に、非反転増幅器A4の出力端
の電圧がn倍に反転増幅されているためおよび抵抗R5
の抵抗値が抵抗R4の抵抗値の反転増幅器の利得n倍に
されているために、インピーダンスに流れる電流中の周
波数の変動による電流は打ち消されて、周波数の変動の
影響は受けない。
Therefore, also in the electronic circuit according to the other embodiment of the present invention, the voltage at the output end of the non-inverting amplifier A4 is n times the same as in the electronic circuit according to the one embodiment of the present invention. Because it is inverted and amplified, and the resistor R5
Since the resistance value of is set to n times the gain of the inverting amplifier of the resistance value of the resistor R4, the current due to the frequency variation in the current flowing through the impedance is canceled and is not affected by the frequency variation.

【0038】なお、A4は非反転増幅器であるのに対し
て、A3は反転増幅器であるために、電源ラインから供
給される電流の変化方向は互いに逆方向であるため、電
源ラインから供給される電流の変化に対しても、電源ラ
インに存在するインピーダンスZ2の影響を抑制するこ
とができる。これは、本発明の実施の一形態にかかる電
子回路においても同様である。
Since A4 is a non-inverting amplifier, A3 is an inverting amplifier, so that the currents supplied from the power supply lines change in opposite directions, so that they are supplied from the power supply line. The influence of the impedance Z2 existing in the power supply line can be suppressed even with respect to the change of the current. The same applies to the electronic circuit according to the embodiment of the present invention.

【0039】[0039]

【発明の効果】以上、説明したように本発明にかかる電
子回路によれば、周波数の変動により第1の抵抗を介し
てインピーダンスに流れる電流と第2の抵抗を介してイ
ンピーダンスに流れる電流とは、互いに打つ消されて、
信号電流はインピーダンスに無関係になって、周波数に
よって影響されることはなくなるという効果が得られ
る。
As described above, according to the electronic circuit of the present invention, the current flowing in the impedance via the first resistor and the current flowing in the impedance via the second resistor due to the frequency fluctuation are , Beat each other,
The effect is that the signal current becomes independent of impedance and is not influenced by frequency.

【0040】また、以上説明したように本発明にかかる
電子回路によれば、実際に電子回路を構成した場合に、
正確、かつ周波数によって変動しない正確な閉利得が得
られるという効果がある。
Further, as described above, according to the electronic circuit of the present invention, when the electronic circuit is actually constructed,
The effect is that an accurate and accurate closed gain that does not fluctuate with frequency can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の一形態にかかる電子回路の構成
を示すブロック図である。
FIG. 1 is a block diagram showing a configuration of an electronic circuit according to an embodiment of the present invention.

【図2】本発明の実施の他の形態にかかる電子回路の構
成を示すブロック図である。
FIG. 2 is a block diagram showing a configuration of an electronic circuit according to another embodiment of the present invention.

【図3】従来の電子回路としての増幅回路の構成を示す
ブロック図である。
FIG. 3 is a block diagram showing a configuration of an amplifier circuit as a conventional electronic circuit.

【符号の説明】[Explanation of symbols]

A1 演算増幅器 A2およびA3 反転増幅器 A4 非反転増幅器 R1、R2、R3、R4およびR5 抵抗 Z、Z1およびZ2 インピーダンス A1 operational amplifier A2 and A3 inverting amplifier A4 non-inverting amplifier R1, R2, R3, R4 and R5 resistors Z, Z1 and Z2 impedance

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】信号電流が流れる第1の抵抗と、第1の抵
抗の一端に接続された反転増幅器と、反転増幅器の出力
端と第1の抵抗の他端との間に接続した第2の抵抗とか
らなり、第2の抵抗の抵抗値を第1の抵抗の抵抗値の反
転増幅器の利得倍としたことを特徴とする電子回路。
1. A first resistor through which a signal current flows, an inverting amplifier connected to one end of the first resistor, and a second resistor connected between the output end of the inverting amplifier and the other end of the first resistor. The electronic circuit is characterized in that the resistance value of the second resistance is set to the gain of the inverting amplifier multiplied by the resistance value of the first resistance.
【請求項2】入力電圧を増幅する増幅器と増幅器の出力
電圧を分圧する第1および第2の抵抗からなる分圧回路
とを備えて第2の抵抗の一端が増幅器の出力端に接続さ
れかつ第1および第2の抵抗の共通接続点が増幅器の反
転入力端子に接続されて第2の抵抗に印加される分圧電
圧を増幅器の反転入力端子に印加する非反転増幅回路
と、増幅器の反転入力端子の電圧を増幅する反転増幅器
と、反転増幅器の出力端と第1の抵抗の非共通接続端子
との間に接続した第3の抵抗とからなり、第3の抵抗の
抵抗値を第1の抵抗の抵抗値の反転増幅器の利得倍とし
たことを特徴とする電子回路。
2. An amplifier for amplifying an input voltage and a voltage divider circuit comprising a first resistor and a second resistor for dividing an output voltage of the amplifier are provided, one end of the second resistor being connected to the output end of the amplifier, and A common connection point of the first and second resistors is connected to the inverting input terminal of the amplifier, and a non-inverting amplifier circuit that applies the divided voltage applied to the second resistor to the inverting input terminal of the amplifier, and an inverting amplifier circuit It comprises an inverting amplifier for amplifying the voltage of the input terminal and a third resistor connected between the output end of the inverting amplifier and the non-common connection terminal of the first resistor, and the resistance value of the third resistor is set to the first value. An electronic circuit characterized in that the resistance value of the resistor is multiplied by the gain of the inverting amplifier.
JP11007997A 1997-04-14 1997-04-14 Electronic circuit Expired - Fee Related JP3427342B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11007997A JP3427342B2 (en) 1997-04-14 1997-04-14 Electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11007997A JP3427342B2 (en) 1997-04-14 1997-04-14 Electronic circuit

Publications (2)

Publication Number Publication Date
JPH10290124A JPH10290124A (en) 1998-10-27
JP3427342B2 true JP3427342B2 (en) 2003-07-14

Family

ID=14526512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11007997A Expired - Fee Related JP3427342B2 (en) 1997-04-14 1997-04-14 Electronic circuit

Country Status (1)

Country Link
JP (1) JP3427342B2 (en)

Also Published As

Publication number Publication date
JPH10290124A (en) 1998-10-27

Similar Documents

Publication Publication Date Title
WO1996041415A1 (en) Detection circuit with hysteresis proportional to the peak input voltage
JPH09178828A (en) Sensor device
US4445054A (en) Full-wave rectifying circuit
JPH0344447B2 (en)
JP3427342B2 (en) Electronic circuit
JPH0432617Y2 (en)
JPH0635540Y2 (en) Differential amplifier
JP2938657B2 (en) Current detection circuit
DK168722B1 (en) Differential amplifier coupling
JP3332660B2 (en) Electric quantity measuring device
JPH0353801B2 (en)
JP3460932B2 (en) Absolute value circuit
JP4859353B2 (en) Amplification circuit and test apparatus
JPH047124B2 (en)
JP3066092B2 (en) Constant current circuit
JP2971613B2 (en) Comparator circuit
JPH10293146A (en) Inductance variation detector
JPS6340904Y2 (en)
JPH05315841A (en) Double voltage detection circuit with temperature compensation
JP2969665B2 (en) Bias voltage setting circuit
JP3073052B2 (en) Impedance measuring instrument
JP2684195B2 (en) Pulse pattern output circuit
JPH0473085B2 (en)
JP3440640B2 (en) Sound detection circuit
JPS59181802A (en) Current input type amplifier

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080516

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090516

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100516

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100516

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110516

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110516

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120516

Year of fee payment: 9

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120516

Year of fee payment: 9

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120516

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130516

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees