JP3426870B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as an MCU (micro controller unit) and a CPU (central processing unit), and particularly to reducing noise generated in a power supply or GND. And a semiconductor integrated circuit capable of

[0002]

2. Description of the Related Art A semiconductor integrated circuit such as a prior art MPU is composed of a plurality of types of various megacells in addition to a CPU. Also, the CPU is internally configured with a plurality of types of circuit blocks.

In recent semiconductor integrated circuits,
Problems such as malfunction of various machines other than the integrated circuit due to noise generated by the integrated circuit itself have been highlighted. For this reason, noise reduction has recently become essential.

The main cause of noise generation in the present semiconductor integrated circuits (particularly C-MOS circuits) is largely due to charging and discharging of gate capacitance and wiring capacitance. In addition, generally, if there are many circuits that charge and discharge at the same time, that much noise is generated. This noise is generally called simultaneous switching noise.

Until now, in semiconductor integrated circuits, F-MA has been used.
Designs have been made with a focus on improving X (maximum operating frequency). In an MCU including a plurality of megacells, the clock skew (clock shift) supplied to each megacell has been devised as much as possible. This means that the number of circuits that simultaneously charge and discharge at the same time is increased, which has led to frequent occurrence of simultaneous switching noise.

The conventional simultaneous switching noise will be described with reference to FIGS. First, as shown in FIG. 14, the MCU (51) includes a CPU (53), a megacell A (55), a megacell B (57), and a clock generator (59). This time mainly M
The PU will be described, but the same applies to the CPU.

FIG. 15 shows the internal circuit of the clock generator (59). Clock generator (59) is CP
U (53), Megacell A (55), Megacell B (57)
At the same time as distributing the clock to be supplied to, the buffer (in the figure, two inverters are used to substitute for the buffer) enhances the driving force.

FIG. 16 is a timing chart showing how noise is generated. In this explanation, the current amount and the noise generation amount are equivalent. As you can see in the figure, CPU (53), Megacell A (55), Megacell B
The skew of the clock supplied to (57) becomes zero.
In this case, the clock switches (changes from High to Low, and changes from Low to High).
(change to h)) and sudden noise is occurring. In other words, it means that the majority of circuits are operating at the same time by switching the clock. The circuit related to the critical path (the neck of the maximum operating frequency) is operating in the part where noise is not generated. Since the ratio of this circuit is small, noise generation during this period is small.

[0009]

As described in detail above, in the conventional semiconductor integrated circuit, the design is made mainly with the aim of improving the maximum operating frequency. Was being supplied. Therefore, there is a problem that a large number of circuits operate simultaneously immediately after the clock changes, and a large amount of noise is generated. Further, since the power supply voltage drops due to this momentary increase in current, there is a risk of malfunction.

Therefore, the present invention has been made in view of such a problem, and its object is to provide a semiconductor integrated circuit capable of suppressing simultaneous switching noise by delaying a clock supplied to each megacell. To provide.

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

To achieve the above object, a feature of the first invention is that a plurality of circuit groups that operate in synchronization with a clock and an external clock are input to each of the plurality of circuit groups. In a semiconductor integrated circuit having a clock supply means for generating and distributing a clock to be supplied,
The clock supply means is such that the skew is zero.
The basic clock is adjusted to generate a delayed clock delayed from the basic clock, based on the indication of whether the information to be supplied with said delayed clock to each circuit group, the basic clock or the delayed clock It is configured to select and distribute each circuit group, decode the input machine language instruction, and determine the critical path in each circuit group.
The critical path is determined by judging whether or not the instruction should be operated.
If it is determined that the command is to operate
Output the instruction information to supply this clock,
It is determined that it is not an instruction to operate the critical path
If the instruction information is
That is, a critical path determination means for outputting a report is provided .

According to the first aspect of the present invention, the critical path determining means inputs a machine language instruction for operating the circuit group and determines that the machine language instruction is an instruction using the critical path in the circuit group . In this case, the instruction information for supplying the basic clock to all the circuit groups is output to the clock supply means. As a result, noise is generated during critical path operation, but skew can be eliminated, and noise can be reduced by supplying a delayed clock during other operations.

The feature of the second invention is that, in the first invention, whether or not the critical path determination means should operate a critical path for each of the first half and the second half of the external clock and for each circuit group. It is to judge and output the instruction information for each circuit group according to the judgment result. First
The feature of the invention of 3 is that the skew is adjusted to zero.
A clock generation circuit for generating a basic clock
It is connected to the output side of the clock
Clock delay times that generate delayed clocks
And a delay means for delaying the basic clock,
Delay between basic clock and output clock of the delay means
The frequency of the basic clock is recognized based on the difference,
Frequency recognition hand that determines the first speed period and the second speed period
And the basic clock is selected during the first speed period
The delay clock is selected during the second speed period.
And a selection circuit that outputs to an external circuit.
It

According to the second invention, it is judged from the machine language instruction for operating the circuit group whether or not the instruction uses the critical path for each of the first half and the second half of the external clock and for each circuit group, and the instruction is given. The information is output to the clock supply means. As a result, the basic clock or the delayed clock can be supplied for each circuit group and for each of the first half and the second half of the clock, and noise reduction can be switched. According to the third invention
For example, the frequency recognition means is the output of the basic clock and the delay means.
Base clock frequency based on the delay difference from the clock
Recognize, for example, the first speed period and the low speed of the high speed operation period
A second speed period of the operating period is determined. First speed period
To select the basic clock for the second speed period
Selects the delayed clock and outputs it to an external circuit.
As a result, noise is generated during high-speed operation, but skew
Noise can be eliminated and noise is reduced during low-speed operation.
it can.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The first embodiment will be described with reference to FIGS. 1, 2 and 3. First, FIG. 1 is a circuit diagram showing the configuration of the first embodiment. The clock generator (5
It corresponds to 9). This circuit includes delay circuits (1) and (3) that delay a basic clock (CLK) input from the outside, buffers (5), (7) and (9) that amplify the clock, each megacell and a CPU. An F / F (11) for holding a switching signal s as to whether or not a delayed clock should be supplied, and a selector (13) for selecting a basic clock or a delayed clock based on the switching signal s.
It is composed of (15).

In this case, the inverter chains are used as the delay circuits (1) and (3), but not limited to the inverter chains, any circuit can be used as long as the clock can be delayed, for example, a circuit using a capacitor and a resistor. . Further, although two inverters are used as the buffers (5), (7) and (9), other means may be used as long as it has a function of amplifying the clock. Further, the F / F (11) is used as a means for holding the switching signal s, but other means may be used as long as the signal can be held.

The operation of the first embodiment will be described below with reference to FIGS. FIG. 2 shows a case where the switching signal s held in the F / F (11) is Low, and the upper basic clock (CLK, delay circuit (1) in FIG. 1 is selected by the selectors (13) and (15). , (3) that do not pass through (3) are selected, and buffers (5) and (7) are selected, respectively.
Entered in. That is, in this case, the clocks that change at the same timing are supplied to the CPU, the megacell A, and the megacell B as in the conventional technique shown in FIG. The amount of noise generated in this case is the same as that in the conventional technique.

Next, FIG. 3 shows the case where the switching signal s is High. In this case, the lower clock in FIG. 1 is selected by the selectors (13) and (15). That is, the delayed clock delayed by the delay circuits (1) and (3) is supplied to the CPU, the megacell A, and the megacell B. The delay time in this case is generally determined with reference to the maximum operating frequency of the circuit. By supplying the delay clock, the number of circuits operating at the same time decreases, but the total current consumed by the circuits (product of current and time: area) does not change, so the time that noise is generated increases. , As shown in Figure 3. Since it is generally considered that the peak should be reduced for noise, the noise of the entire semiconductor integrated circuit is reduced.

As described above, according to the configuration of the first embodiment,
By switching the switching signal s to Low or High, the clocks supplied to each megacell and the CPU can be switched between the basic clock and the delayed clock, and the clocks and clock conditions in each megacell to be used can be changed as necessary. You can eliminate cues and reduce noise.

A second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 4, the second embodiment is provided with an input pin (17) for inputting a control signal output from an external device (not shown) in addition to the components shown in FIG. 1, and is connected to the F / F (11). It was done. This input pin (17) is MCU,
Alternatively, it is a pin for communicating with the outside of the CPU. According to the second embodiment, since the input pin (17) is provided, Low or High output from the external device.
Since the h signal can be held in the F / F (11) as the switching signal s, it is possible to freely reduce noise as shown in FIG. 3 from the outside.

A third embodiment of the present invention will be described with reference to FIG. In the third embodiment, as shown in FIG. 5, in addition to the constituent elements shown in FIG. 1, common data is transmitted and received in a BUS (19).
And a machine language instruction decoder (21) for inputting the machine language instruction and decoding the machine language instruction so that the processing is performed as predetermined. Using the machine language instruction decoder (21) and BUS (19), the F / F (1
The switching signal s is written in 1).

As shown in the operation diagram of FIG. 6, when the switching signal s is changed from Low to High during the execution of the MPU by the machine language instruction, the delay clocks are supplied to the mega cells A and B after the changed timing, Noise is reduced. According to the third embodiment, the user can instruct noise reduction by executing a normal machine language instruction.

A fourth embodiment of the present invention will be described with reference to FIGS. 7, 8 and 9.
Will be explained. In the fourth embodiment, as shown in FIG.
In addition to the components shown in, a frequency recognition circuit (23) for recognizing the operating frequency of a basic clock (CLK) input from the outside is provided, and the frequency recognition signal n is output to the F / F (11). Has been done. This frequency recognition circuit (23) inputs an external clock (CLK), recognizes a high speed operation period and a low speed operation period from the operation frequency of the external clock, and outputs a Low signal as a frequency recognition signal n during the high speed operation period. During the low speed operation period, the High signal is output.

FIG. 8A is a circuit diagram showing an example of the configuration of the frequency recognition circuit (23). As shown in the figure, a delay circuit 25 including an odd number of inverters inputs an external clock, loops the output to the input, and is connected to the AND gate 27 and the latch circuit 29. The output of the AND gate 27 is input to one end of the latch hold time securing buffer 31 and the OR gate 33, and the buffer 31
Is output to the D terminal of the latch circuit 29. Furthermore, the output from the latch circuit 29 is input to the other end of the OR gate 33, and the frequency recognition signal n is output from the OR gate 33.

The operation of each point a, b, c and the frequency recognition signal n of the frequency recognition circuit (23) configured as above is shown in FIG. 8 (B). The frequency recognition signal n is Low during the high speed operation period of the external clock, but can be High only during the low speed operation period. In general, assuming 20 Mhz operation, normal operation may not occur unless a clock having no skew is supplied to the mega cell. Therefore, by using the frequency recognition circuit (23) to set the frequency recognition signal n to Low during the 20 Mhz operation period, noise is generated but skew can be eliminated.

FIG. 9 shows a situation in which noise is low during low speed operation (10 Mhz) and noise occurs during high speed operation (20 Mhz). As described above, according to the fourth embodiment, the processing speed is slow during the low speed operation period, but noise can be reduced, and the noise can occur during the high speed operation period, but the processing speed can be increased.

A fifth embodiment of the present invention will be described with reference to FIGS. In the fifth embodiment, as shown in FIG.
In addition to the components shown in, the basic clock is input, the machine language instruction is input and decoded, and it is determined whether the instruction to be decoded and executed is an instruction that uses the critical path in each megacell. A critical path determination circuit (35) for
It is configured to output to 1). Generally, when a critical path is used in each megacell, it does not operate normally unless a clock having no clock skew is supplied.

When the critical path determination circuit (35) determines that the decoded instruction is an instruction that uses the critical path in each megacell, it outputs the Low signal as the switching signal s, and otherwise outputs the High signal. To do. FIG. 11 shows an example of a conceptual diagram for explaining the function of the critical path determination circuit (35). When a machine language instruction is input, the machine language instruction register (3
A machine language instruction is output to the table (39) via 7), and the micro ROM start address is output from the table (39) to the micro ROM (41). Micro RO
A control signal is output from the M (41) to the microcomputer.
It

The table (39) contains MOVE and AD.
Instruction mnemonics such as D and CMP, corresponding micro ROM start address (0 to n), data d1 indicating whether the instruction uses the critical path and whether the data uses the critical path Data d2 representing the above is created. OR for each start address
The gate 43 takes the logical sum of the data d1 and d2, and the result is output as the switching signal s. A control code is prepared for each address (0 to n) in the micro ROM (41). In this example, when either the instruction or the data uses the critical path, the switching signal s is set to High and output to the F / F (11).

As described above, according to the fifth embodiment, noise is generated during the critical path operation, but the normal operation can be performed, and the noise can be reduced while the other circuits are operating.

A sixth embodiment of the present invention will be described with reference to FIGS. In the sixth embodiment, as shown in FIG.
In addition to the selector (1
F / F (11) and (12) are provided for each of 3) and (15),
Each F / from the critical path judgment circuit (45)
The switching signals s and t are output to F (11) and (12). That is, the critical path determination circuit (4
5) determines whether or not the instruction uses the critical path for each of the megacells (A) and (B), and further determines whether or not the delay clock should be supplied in each of the first half and the second half of the basic clock. It has a function to do. As a result, the duty cycle of the clock (ratio of Low and High periods)
Can also be controlled.

FIG. 13 is a timing chart showing the operation of the sixth embodiment. Critical path judgment circuit (4
It can be seen from 5) that the critical path is used in the first half of the third clock of the megacell A, and only the switching signal s is Low in the first half of the third clock. As a result, the basic clock is selected by the selector (13) and supplied to the mega cell A. By this measure, the first half period of the third clock supplied to the megacell A becomes longer than the clock supplied to the CPU and the megacell B (a = c).
<B): Although some noise cannot be prevented, normal operation can be performed despite the critical path.

[0041]

As described above in detail, according to the first aspect of the invention, the clocks to be supplied as necessary are delayed from the basic clock by the circuits used in each circuit group and the operating conditions such as the operating speed. Since it can be switched with the clock, it is possible to suppress simultaneous switching noise due to simultaneous operation of many circuits. Especially the kritika
Supply the basic clock to the circuit group during lupus operation
Switching the circuit to normal operation of the circuit group
The delay clock can be supplied during other operations.
Noise can be reduced by using the
It becomes possible to realize a conductor integrated circuit. Second invention
According to this, in addition to the effect of the first invention,
The basic clock or delay clock is applied to each of the first and second half of the clock.
Lock can be supplied and noise reduction can be switched.
Wear. According to the third aspect of the invention, the operation speed can be adjusted to meet the needs.
Clocks to be supplied together are basic clock and delayed clock
You can switch with and. For example, an external clock
Select the basic clock during the high-speed operation period and
Select the delay clock only in the
If you do not supply a clock with no skew,
If not, select the basic clock to ensure normal operation.
Highly reliable semiconductor integration that can enable operation
A circuit can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 6 is a waveform chart for explaining the operation of the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a configuration of a frequency recognition circuit according to a fourth embodiment.

FIG. 9 is a waveform chart for explaining the operation of the fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 11 is a conceptual diagram illustrating a function of a critical path determination circuit according to the fifth embodiment.

FIG. 12 is a circuit diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 13 is a waveform chart for explaining the operation of the sixth embodiment of the present invention.

FIG. 14 is a diagram illustrating an internal structure of a conventional MCU.

FIG. 15 is an internal circuit diagram of a conventional clock generator.

FIG. 16 is a waveform diagram for explaining the operation of the conventional MCU.

[Explanation of symbols]

1,3 delay circuit 5,7,9 buffer 11,12 F / F 13,15 selector 17 input pins 19 BUS 21 Machine language instruction decoder 23 Frequency recognition circuit 25 delay circuit 27 AND gate 29 Latch circuit 31 Latch hold time securing buffer 33 OR gate 35 Critical path judgment circuit 37 Machine Language Instruction Register 39 tables 41 Micro ROM 43 OR gate 45 Critical path judgment circuit 51 MCU 53 CPU 55 Mega Cell A 57 megacell B 59 clock generator

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-220522 (JP, A) JP-A-4-515 (JP, A) JP-A-6-216729 (JP, A) JP-A-6- 283999 (JP, A) JP-A-6-162224 (JP, A) JP-A-3-263279 (JP, A) JP-A-2-102561 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 1/10

Claims (3)

(57) [Claims] 1. A semiconductor integrated circuit comprising: a plurality of circuit groups that operate in synchronization with a clock; and a clock supply unit that inputs an external clock and generates and distributes a clock to be supplied to each of the plurality of circuit groups. In the circuit, the clock supply means is such that the skew is zero.
The basic clock is adjusted to generate a delayed clock delayed from the basic clock, based on the indication of whether the information to be supplied with said delayed clock to each circuit group, the basic clock or the delayed clock It is configured to select and distribute each circuit group, decode the input machine language instruction , and
Judge whether it is an instruction to operate the critical path
However, it is determined that the instruction should operate the critical path.
If it is turned off, the basic clock should be supplied to
Should output the instruction information and operate the critical path.
When it is judged that it is not an instruction, the delay clock is supplied.
To output the instruction information to
A semiconductor integrated circuit comprising disconnecting means . 2. The critical path determining means determines whether or not the critical path should be operated for each of the first half, the second half, and each of the circuit groups of the external clock, and outputs the instruction information according to the determination result. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is output for each circuit group. 3. A clock generating circuit for generating a basic clock adjusted so that the skew becomes zero, and a delayed clock which is connected to an output side of the clock generating circuit and delays the basic clock. And a delay means for delaying the basic clock,
Based on the delay difference between the clock and the output clock of the delay means.
Then, the frequency of the basic clock is recognized and the first speed
Frequency determining means for determining a frequency period and a second speed period, and selecting the basic clock for the first speed period,
A semiconductor integrated circuit comprising: a selection circuit that selects the delayed clock and outputs the selected delayed clock to an external circuit during the second speed period .