JP3420810B2 - Barcode reader - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bar code reader used in POS and the like. 2. Description of the Related Art FIG. 12 is a block diagram showing a circuit section of a generally used bar code reader. The circuit portion of the bar code reader includes a waveform processing circuit 2 for digitizing an output signal of the image sensor 1 as shown in the figure, a memory portion 3 as one storage means for storing an output value of the waveform processing circuit 2, and a memory. The waveform processing circuit 2 comprises a microprocessor 4 which decodes bar code symbols based on the data of the unit 3. The waveform processing circuit 2 stores all image data of the image sensor 1 in the memory unit 3. After transmitting the information to the input port 5 of the microprocessor 4, the microprocessor 4 performs decoding based on the image data in the memory unit 3. [0003] By the way, barcode symbols include JAN, E as one-dimensional codes for commodity goods.
Code39, Code128, NW7, I as one-dimensional codes for AN and UPC codes and FA, logistics, and OA
TF and the like. Further, there are a multi-stage barcode symbol using a plurality of stages of the above-described various codes, and a two-dimensional barcode symbol such as Code49 in which the number of stages is variable from 2 to 8. In recent years, with the progress of barcode systems, systems for reading various barcode symbols attached to the surface of a product placed on a moving body such as a belt conveyor have been found in FA and physical distribution applications.
In each application, a system for reading a multistage barcode symbol or a two-dimensional barcode symbol is also found. What greatly affects the efficiency of the system such as the speed of the belt conveyor is the reading speed of the barcode reader. Conventionally, the output signal of the image sensor digitized by the waveform processing means is stored in a storage means,
The bar code symbol is decoded based on the data in the storage means.While all the data is input to the storage means, the decoding process cannot be performed and the system is in a waiting state, so from the start of signal output by the image sensor to the completion of decoding. Requires a time that is obtained by adding the total data input time to the storage means and the decoding time by the decoding means, and thus the time required to read the barcode symbol is prolonged. An object of the present invention is to provide a bar code reader for reading various bar code symbols at high speed in order to solve such problems. SUMMARY OF THE INVENTION [0009] To achieve the above object,
Means for solving the problems of the present invention are: light projecting means for irradiating light onto a bar code label; light receiving means for forming reflected light from the bar code label on an area image sensor; and an output of the area image sensor. Waveform processing means for digitizing a signal, storage means for storing image data digitized by the waveform processing means, and decoding means for decoding a barcode symbol based on the image data stored in the storage means. In the bar code reader provided, from the image data digitized by the waveform processing means, the number of black or white data for each line or a plurality of lines corresponding to the horizontal and vertical directions of the pixels of the area image sensor is determined. Data detecting means for detecting and storing the detected number in the storage means, wherein the decoding means detects the data And the contents of the stage reference, a configuration in which the decoding of the bar code information from the bar code label the entire image data stored in the storage means. According to this configuration, the number of white or black data of the image data input to the storage means can be determined in the horizontal and vertical directions. By detecting and storing for each direction,
By referring to this content, it is possible to detect and decode the position of the barcode information from the image data of the entire barcode label. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a barcode reader according to the present invention.
Here, reference numeral 10 denotes a two-dimensional barcode symbol on the barcode label, and reference numeral 11 denotes a light projecting unit for irradiating the barcode symbol 10, and a plurality of LEDs having a wavelength of 660 nm are arranged on the line. The light receiving means includes a reflection mirror 12 and a light receiving lens 13, and the light reflected from the bar code 10 is guided to the light receiving lens 13 by the reflection mirror 12. Numeral 14 denotes a television camera having a 512 × 512 pixel CCD area image sensor, which outputs a composite video signal including a horizontal synchronizing signal and a vertical synchronizing signal to an image formed by the light receiving lens 13 in accordance with the broadcasting standard NTSC. I do. The circuit section 15 includes: a television camera 14; a waveform processing means for separating and amplifying only an image signal from an NTSC composite video signal obtained by the television camera 14 to perform binarization processing; a storage means; Decoding means for decoding based on image data. FIG. 2 is a schematic block diagram of the circuit section 15. Two waveform processing circuit 16 is different method as the waveform processing means having the characteristic (a), and (b), a storage capacity 32K bytes of RAM as a memory means in the first division <br/> problem solving means Two frame memories 17 configured
It comprises four frame memories 17 (a) to 17 (d) in (a) and (b) and another second means for solving the problem, and a microprocessor 18 for executing the decoding means. In the embodiment of the third problem solving means, the waveform processing circuit 16 (a) and the frame memory 17 (a) are both one for simplicity of description, but the first and second problem solving means are used. You may use more than one. Here, 16 (a) is a first waveform processing circuit, 16 (b) is a second waveform processing circuit, 17 (a) is a first frame memory, and 17 (b) is a second frame processing circuit. A memory, 17 (c) is a third frame memory, and 17 (d) is a fourth frame memory. First and second waveform processing circuits 16 (a), 1
6 (b) is a waveform processing circuit which separates a composite video signal, which is an output signal from the television camera 14, into a horizontal synchronizing signal, a vertical synchronizing signal and an image signal, separates and amplifies only the image signal, and binarizes it. , And converts them into digital signals of “H” and “L” according to the analog output value of the video signal. These first and second waveform processing circuits 16 (a) and 16 (b) are composed of first and second separation / amplification circuits 19 composed of operational amplifiers and the like.
(A) and 19 (b), and first and second filter circuits 20 (a) and 20 (b) which are also constituted by operational amplifiers and the like.
And first and second binarizing circuits 21 (a) and 20 (b) which are also constituted by operational amplifiers and the like. In this embodiment, the binarizing circuit converts the image data into a digital signal depending on whether the analog voltage of the video signal (image data) input to the operational amplifier is higher or lower than the voltage (threshold voltage) set by the terminal voltage of the operational amplifier. Was converted to. The characteristics of the waveform processing circuit are changed by changing the voltage. The power supply is a single 5V power supply, and the threshold value of the first waveform processing circuit 16 (a) is 2V.
The threshold value of the second waveform processing circuit 16 (b) was set to 1V. The storage control means comprises a frame memory control circuit for controlling connection of a plurality of frame memories, generating addresses, and converting the binary image data into serial / parallel data. Is constituted by a first frame memory control circuit 22, or the second storage control means is constituted by a second frame memory control circuit 30, or a third frame memory control circuit 33, a fourth frame memory control circuit 34. The details of these connections will be described with reference to the block diagrams of FIGS. In FIG. 2, reference numeral 18 denotes a microprocessor, in which the LED of the light emitting unit, the buzzer for reading completion, and the control circuit of the buzzer and the LED are omitted. FIG. 3 shows a first waveform processing circuit 16 (a),
A second waveform processing circuit 16 (b), a first frame memory 17 (a), a second frame memory 17 (b), and a first frame memory control circuit 22 for controlling connection with the microprocessor 18; This shows an embodiment of the first problem solving means. As shown, the first waveform processing circuit 16 (a) and the second waveform processing circuit 16 (b) are respectively controlled by the first frame memory 1 by the first frame memory control circuit.
7 (a) and the second frame memory 17 (b), the digitized image data is simultaneously sent to the first frame memory 17 (a) via the address data bus 26 and to the first frame memory 17 (b) via the address data bus 25, respectively. It is stored in the second frame memory 17 (b). After inputting the fact that all the pixels of the television camera 14 are stored in both frame memories from the first frame memory control circuit to the input port 27 of the microprocessor 18, the microprocessor 18 sends the first frame memory 17 (a). Is decoded through the address data buses 24 and 26. If the image data stored in the first frame memory 17 (a) is not normal, the output port 2 of the microprocessor
By switching the first frame control circuit at 3,
The microprocessor 18 has a second frame memory 17
The decoding of (b) is performed through the address data buses 24 and 25. [0026] FIG. 4 shows a second real施例.
In this embodiment, in addition to FIG. 3 of the first embodiment , an image data selection circuit 29 which is a comparison circuit composed of an operational amplifier is used as image data selection means, and the amplitude of an output signal from the television camera 14 is 3 V. If so, the microprocessor 18 inputs the output of the image data selection circuit 29 to the input port 28 of the microprocessor 18 so that the decoding of the first frame memory 17 (a) is performed first through the address data buses 24 and 26. . When the amplitude of the output signal from the television camera 14 is 3 V or less, the microprocessor 18 controls the image data selection circuit 29 so that the decoding of the second frame memory 17 (b) is performed first through the address data buses 24 and 25. Output to microprocessor 1
8 input port 28. [0027] Since the previously decryption processing is performed from the image data binarized by this way a more optimal image processing circuit, than the processing speed is the first real施例faster. FIG. 5 shows a first waveform processing circuit 16 having a different system or characteristic.
(A), a second waveform processing circuit 16 (b), a first frame memory 17 (a), a second frame memory 17
And (b), shows a third actual <br/>施例the second frame memory control circuit 30 for controlling the connection between the microprocessor 18. In the case indicated by the solid line, the microprocessor 18 is connected to the second frame memory 17 (b) through the address data buses 25 and 24 and decodes the stored image data. A first waveform processing circuit 16 (a) is connected to the first frame memory 17 (a), and the next image data is input simultaneously with the decoding of the image data in the second frame memory 17 (b). . In the case indicated by the dashed line, the microprocessor 18 is connected to the first frame memory 17 (a) through the address data buses 26 and 24, and when the first line is input in the case indicated by the solid line. Frame memory 17
The image data stored in (a) is decoded. Second
The second waveform processing circuit 16 (b) is connected to the frame memory 17 (b) of the first frame memory 17 (b).
New image data is input simultaneously with the decoding of the image data in FIG. Switching between the case shown by the solid line and the case shown by the broken line is performed by an output signal from the output port 23 of the microprocessor 18. Further, the first frame memory 17 (a) and the second frame memory 17 (b) are assigned to the same area on the address as viewed from the microprocessor 18, thereby simplifying the programming of the microprocessor 18. FIG. 6 shows a first waveform processing circuit 16 (a) and a second waveform processing circuit 1 having different systems or characteristics.
6 (b), the first frame memory 17 (a), the second frame memory 17 (b), and the third frame memory 17
(C), a fourth frame memory 17 (d), shows a fourth actual施例frame memory control circuit 3 for controlling the connection between the microprocessor 18 (33). When indicated by the solid line, the microprocessor 18 stores the address data bus 24 in the third frame memory 17 (c) or the fourth frame memory 17 (d).
It is connected to 31 or 32 and decodes stored image data. First frame memory 17
(A) is connected to the first waveform processing circuit 16 (a), and the second frame memory 17 (b) is connected to the second waveform processing circuit 16 (b). At the same time when the image data in the memory 17 (c) or the fourth frame memory 17 (d) is decoded, the next image data is stored in the first frame memory 17 (a) and the second frame memory 17 (b).
Are input at the same time. In the case indicated by the broken line, the microprocessor 18 stores the address data bus 24 and the address data bus 24 in the first frame memory 17 (a) or the second frame memory 17 (b).
26 or 25, and the first frame memory 17 input in the case indicated by the solid line.
(A) or decoding the image data stored in the second frame memory 17 (b). A first waveform processing circuit 16 (a) is connected to the third frame memory 17 (c), and a second waveform processing circuit 16 (b) is connected to the fourth frame memory 17 (d). The new image data is stored in the third frame memory 1 simultaneously with the decoding of the image data.
7 (c), and are simultaneously input to the fourth frame memory 17 (d). Switching between the case indicated by the solid line and the case indicated by the broken line is performed by an output signal from the port 23 of the microprocessor 18. Also, the first frame memory 17
(A) and the second frame memory 17 (b) or the third frame memory 17 (c) and the fourth frame memory 17 (d) are assigned to the same area on the address as viewed from the microprocessor 18. As a result, the programming of the microprocessor 18 is simplified. FIG. 7 shows a fifth real施例.
This embodiment, in addition to FIG. 6 is a fourth real施例, the image data selection circuit 29 is a comparator circuit which is constituted by an operational amplifier used as an image data selection means. When the microprocessor is decoding based on the image data stored in the third frame memory 17 (c) or the fourth frame memory 17 (d), the first frame memory 17 (c)
(A) is connected to the first waveform processing circuit 16 (a), and the second frame memory 17 (b) is connected to the second waveform processing circuit 16 (b). Is larger than 3 V, the microprocessor 18 decodes it based on the image data stored in the third frame memory 17 (c) or the fourth frame memory 17 (d), The decoding of the first frame memory 17 (a) is performed by the address data buses 24 and 26.
The output of the image data selection circuit 29 is input to the input port 28 of the microprocessor 18 so as to perform the processing. When the amplitude of the output signal from the television camera 14 is 3 V or less, the microprocessor 18 controls the third frame memory 1
7 (c) or the image data stored in the fourth frame memory 17 (d), and then decode the second frame memory 17 (b) through the address data buses 24 and 25 first. The output of the image data selection circuit 29 to the input port 28 of the microprocessor 18
To enter. [0034] Since the previously decryption processing is performed from the image data binarized by this way a more optimal image processing circuit, than the processing speed is the fourth actual施例faster. FIG. 8 shows the first
Waveform processing circuit 16 (a) and first frame memory 17
(A) and shows a sixth real施例the frame memory control circuit 4 for controlling the connection between the microprocessor 18 (34). The image data digitized by the first waveform processing circuit 16 (a) by the fourth frame memory control circuit 34 is stored in the first frame memory 17 (a). At this time, the area of the frame memory is stored in a horizontal 504 × vertical 511 area smaller than the area image sensor image. Left horizontal 8X vertical 512 and horizontal 504
In the X-vertical 1 area (shown by hatching in the figure), data which is binarized data of "H" (black pixels on the area image sensor) for each horizontal pixel line and for each vertical pixel 32 pixels Is detected by the data detection circuit 35 and stored. The data detection circuit 35 includes a counter. One 8-bit counter cleared by a horizontal synchronization signal was used for each horizontal pixel line. In addition, since it is necessary for the black pixel of the vertical pixel to store the number of data by each vertical address, storing the number for each line requires 512 counters, which is not practical. Sixteen were used. After inputting the fact that all the pixels of the television camera 14 are stored in both frame memories from the fourth frame memory control circuit 34 to the input port 27 of the microprocessor 18, the microprocessor 18 transmits the first frame memory 17 (a ) Is decoded through the address data buses 24 and 26. At this time, the microprocessor 18 checks the value detected by the data detection circuit 35 stored in the first frame memory 17 (a) before starting decoding the barcode information, and determines the area in which the barcode information is stored. And the size of the barcode, and the like, and decoding is performed from the area where the barcode is presumed to be stored. By using the embodiment of FIG. 8, the decryption process can be performed from the location where the barcode information is stored, so that the decryption process becomes faster. [0036] In the above sixth real施例of, has been described one waveform processing circuit and a frame memory, by using other multiple waveform processing circuit and a frame memory and the storage control unit, further having a total processing time Can be shortened. [0037] Figure 9 is a conventional storage device is one and (a), a first processing necessary to decode completion from the output start of the analog signal by the image sensor of the real施例(b) of the present invention It is a comparison of time. Note that the processing is performed in real time from the output of the analog signal from the image sensor to the binarization of the image signal. When the conventional technique is used, the processing time of the n bar codes is reduced by the input time of all image data to the frame memory (even when the normal image data is all input to the frame memory by the waveform processing circuit). n · trnj) and the decoding time by the microprocessor (n · tdn)
j) When necessary and abnormal data (image data that is not correctly binarized and a decoding error occurs) occurs m times,
Further, m · (trmj + tdmj) is required, and a total of n · (trnj + tdnj) + m · (trmj + tdm)
j). Here, trnj (trmj) is the input time of all image data to the n (m) th frame memory, td
nj (tdmj) indicates an n (m) -th decoding time, and trnj (t
rmj) and tdnj (tdmj) are each constant. Further, j indicates the characteristic of the waveform processing circuit. For example, t
d31 indicates a time for decoding image data obtained by binarizing the image data of the first image data by the waveform processing circuit characteristic 1. In this embodiment, a waveform processing circuit having two characteristics is used. However, when normal image data cannot be obtained with the two characteristics, the characteristics of each circuit can be changed by a port output from the microprocessor. Therefore, j = 1, 3, ‥ The characteristics are changed using the first waveform processing circuit. The same applies to j = 2, 4,. The input time of all image data (trnj
(Trmj)) is one screen (512 × 512) when an NTSC television camera is used as in this embodiment.
It takes 33 ms to load the image data of (pixel) into the frame memory. Although the decoding time varies depending on the image data, it is set to 100 ms here. Here, T indicates normal image data, and F indicates abnormal image data. In the conventional example of FIG. 9A, n = 3 and m = 1, and 532 ms is required. [0040] In the first real施例of the present invention, however, FIG. 9
As shown in (b), since image data is stored in two frame memories by waveform processing circuits having different characteristics,
After inputting the image data 1, even if the image data of tr1 has a decoding error, the normal image data of tr2 can be decoded immediately. This is 499 ms, which is 3 times higher than the conventional example.
It is reduced by 3 ms. [0041] In the second real施例, since an image data selection means is 100ms shorter than 399ms and the first actual施例as shown in FIG. 9 (c). FIG. 10 (a)
2 shows a conventional example in which abnormal data continues twice. From this figure, it can be seen that the entire processing time requires 665 ms. In the case of such image data, even if the embodiment of the second problem solving means is used as shown in FIG.
ms is required and only 33 ms is reduced. But the third
By use real施例, it is possible to store the next image data in the image data decoding may 533ms next 132ms shortened as shown in Figure 10 (c). FIG. 11A shows a conventional example as shown in FIG.
The same is shown (532 ms required). In contrast, FIG.
As shown in FIG. 1 (b), when the embodiment of the fourth problem solving means is used, the effects of the first and third embodiments are obtained, which is 433 ms, which is 99 ms shorter. In the fifth embodiment, since the image data selecting means is provided in addition to the fourth embodiment , it becomes 333 ms as shown in FIG. 11C, which can be shortened by 199 ms. In this embodiment, the microprocessor used has 64 Kbytes of ROM and 2 Kbytes of RAM. The barcode symbol 1 may be a one-dimensional barcode symbol or a multi-stage barcode symbol. The image sensor may be a charge-coupled device (CCD) image sensor, a charge injection device (CD1) image sensor, or another photoresponsive device. In addition, the array may be one that exists on a straight line like a linear image sensor or one that exists on a surface like an area image sensor. In this embodiment, the NTSC system, which is a Japanese standard, is used as the television camera 14, but the PAL system or another system may be used. Further, the area image sensor having 512 × 512 pixels is used, but the area image sensor may have 722 × 494 pixels or another number of pixels. Further, when digitizing in the waveform processing circuit, a binarizing circuit is used, but digitization may be performed by an AD converter. According to the configuration of the present invention, the number of white or black data of the image data input to the storage means is determined by
By detecting and storing one line or several lines in the horizontal and vertical directions, by referring to this content, the position of the barcode information can be detected and decoded from the image data of the entire barcode label. The decoding speed can be improved. As a result, the overall processing time can be reduced, and various barcode symbols can be read at high speed.
Operability is improved. Furthermore, in the case of a system that reads a bar code attached to the surface of a product placed on a moving object such as a belt conveyor, the speed of the moving object can be increased, the efficiency of the system increases, and the economic effect is enormous. Some of them have great industrial effects.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a schematic configuration of a barcode reader according to an embodiment of the present invention. FIG. 2 is a block diagram showing a schematic circuit section of an embodiment of the present invention. relationship between the first storage means in the real施例decoding means and second storage means in the real施例decoding means and the waveform processing means of the block diagram showing the relationship between the waveform processing means [4] the present invention of the present invention a storage unit in the fourth actual施例diagrams Figure 5 present block diagram illustrating the relationship between the third storage means and decoding means and the waveform processing means in real施例of invention 6 the invention showing a sixth decoding means and a block diagram showing the relationship of the fifth storage means and decoding means and the waveform processing means in real施例of a block diagram showing the relationship between the waveform processing means 7 present invention the present invention; FIG shows the relationship between the storage means and decoding means and the waveform processing means in real施例of The block diagram Fig. 9 Conventional and the present invention 1, the first, second, third implementation of the second graph showing a comparison of the processing time in the real施例in FIG. 10 prior art and the present invention graph 11 fourth conventional example the invention showing a comparison of the processing time in the example, shows a circuit portion of the graph 12 shows a conventional bar code reader showing a comparison of the processing time in the fifth real施例Block Diagram [Description of References] 10 Two-dimensional barcode symbol 11 LED 12 Reflecting mirror 13 Light receiving lens 14 TV camera 15 Circuit section 16 (a) First waveform processing circuit 16 ( b ) Second waveform processing circuit 17 (a) First frame memory 17 (b) Second frame memory 17 (c) Third frame memory 17 (d) Fourth frame memory 18 Microprocessor 19 Separation / amplification circuit 20 Filter circuit 21 Binarization time 22 first frame memory control circuit 23 output port 24 address data bus 25 address data bus 26 address data bus 27 input port 28 input port 29 image data selection circuit 30 second frame memory control circuit 31 address data bus 32 address data bus 33 third frame memory control circuit 34 fourth frame memory control circuit 35 data detection circuit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tetsuya Kannon 1006 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electric Industrial Co., Ltd. 5176 (JP, A) JP-A-4-52884 (JP, A) JP-A-62-227979 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06K 7/10 G06K 3 / 06 302

Claims (1)

(57) [Claims] [Claim 1] Light projection for irradiating light on a barcode label
Means and the reflected light from the bar code label
Light receiving means for forming an image on the image sensor;
Processing means for digitizing the output signal of the image sensor
And image data digitized by the waveform processing means.
Storage means for storing data stored in the storage means;
Decode barcode symbols based on image data
A bar code reader having decoding means
From the image data digitized by the shape processing means,
Horizontal and vertical directions of the pixels of the area image sensor
Black or white every single line or multiple lines corresponding to
The number of pieces of data is detected, and the detected number is stored in the storage means.
Data detecting means for storing the data.
The data stored in the storage means is referred to the contents of the data detection means.
From the image data of the entire barcode label
-A bar code reader for decoding code information .