JP3417610B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a floating gate.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional example E of the present invention.
The manufacturing method of PROM is shown. In order to manufacture this conventional example, as shown in FIG. 5A, a SiO ₂ film (not shown) for a pad having a film thickness of 50 nm and a film thickness of 100 nm are formed on the surface of the Si substrate 11. And the SiN film (not shown) are sequentially formed, and then a resist (not shown) is processed on the SiN film to form a pattern of the element active region.

After that, RI using this resist as a mask
After patterning the SiN film with E and removing the resist, impurities for forming a channel stopper are ion-implanted into the Si substrate 11 using the SiN film as a mask.
Then, the SiO ₂ film 12 is formed on the surface of the element isolation region by LOCOS oxidation using the SiN film as an oxidation prevention mask. After that, the SiN film and the SiO ₂ film for the pad are sequentially removed by etching, and the SiO ₂ film 13 as the gate oxide film for the floating gate having a film thickness of 25 nm is formed on the surface of the element active region.

Next, as shown in FIG. 5B, the film thickness is 15
nm polycrystal Si film 14 is deposited on the entire surface, and POCl ₃
Exposed to vapors such as phosphorus and phosphorus from the vapors
4 is performed for 1 hour at a temperature of 950 ° C., and then the polycrystalline Si film 14 is divided into patterns in the extending direction of the control gate to be formed later. A resist (not shown) is processed above. Then, the polycrystalline Si film 14 is patterned by RIE using this resist as a mask, and then the resist is removed.

Thereafter, a SiO ₂ film having a thickness of 15 nm is formed on the surface of the polycrystalline Si film 14 by thermal oxidation at a temperature of 1100 ° C., and a SiN film having a thickness of 15 nm is formed on the SiO ₂ film by the CVD method. Formed on the surface of this SiN film for 2 to 3n.
ON as an insulating film for capacitive coupling after being oxidized to a film thickness of m
The O film 15 is formed on the surface of the polycrystalline Si film 14.

After that, a polycrystalline Si film 1 having a film thickness of 30 nm is formed.
6 is deposited on the entire surface and exposed to vapor such as POCl ₃ to thermally diffuse phosphorus or the like into the polycrystalline Si film 16 from this vapor at a temperature of 950 ° C. for 1 hour. A resist (not shown) is processed on the polycrystalline Si film 16 to form a control gate pattern.

RI using this resist as a mask
The polycrystalline Si film 16, the ONO film 15, and the polycrystalline Si film 14 are sequentially patterned with E, and then the resist is removed. By this patterning, a control gate is formed by the polycrystalline Si film 16, and the polycrystalline Si film 14 is separated for each memory cell to form a floating gate.

After that, the polycrystalline Si films 16 and 14 and SiO
_{2 With the} film 12 or the like as a mask, P with an acceleration energy of about 100 keV and a dose amount of about 1 × 10 ¹⁴ cm ⁻²
Hos ⁺ 17 is ion-implanted into the Si substrate 11. Then, perform annealing for 30 minutes at a temperature of 1000 ° C.,
An N ⁻ type diffusion layer 18 is formed.

Next, as shown in FIG. 5C, the film thickness is 30
A 0 nm SiO ₂ film 21 is deposited on the entire surface by the CVD method,
The entire surface of the SiO ₂ film 21 and the exposed SiO ₂ film 13
RIE is performed to form sidewalls of the SiO ₂ film 21 on the polycrystalline Si films 14, 16 and the like. Then, a SiO ₂ film 22 having a film thickness of 25 nm is deposited on the entire surface by a CVD method, and heat treatment is performed in dry oxygen at a temperature of 1000 ° C. for 20 minutes to densify the SiO ₂ film 22.

After that, the polycrystalline Si films 16 and 14 and SiO
_{The 2} films 21, 12 and the like are used as a mask and the SiO ₂ film 22 is used.
While preventing metal contamination with As ⁺ 23 with acceleration energy of about 70 keV and a dose amount of about 8 × 10 ¹⁵ cm ^-2
(FIG. 7) is ion-implanted into the Si substrate 11. And
Annealing is performed in dry oxygen at a temperature of 1000 ° C. for 40 minutes to form an N ⁺ type diffusion layer 24.

Next, as shown in FIG. 5D, the film thickness is 60
CV the SiO ₂ film 25 as an interlayer insulating film having a thickness of 0 nm.
After being deposited on the entire surface by the D method, a resist (not shown) is processed on the SiO ₂ film 25 into a pattern of contact holes for bit lines and source lines. Then, RIE is performed using this resist as a mask to open a contact hole 26 reaching the diffusion layer 24 in the SiO ₂ film 25 or the like, and then the resist is removed.

After that, an Al film 27 having a thickness of 1.2 μm is deposited on the entire surface, and a resist (not shown) is processed on the Al film 27 to form a pattern of bit lines, source lines and the like. Then, the Al film 27 is patterned by RIE using this resist as a mask, and then the resist is removed.

After that, P-Si as an overcoat film is formed.
An N film 28 is deposited on the entire surface, and a resist (not shown) is processed on the P-SiN film 28 to have a pattern of openings for electrode pads. Then, RIE is performed using this resist as a mask to form an opening (not shown) for the electrode pad in P-SiN.
After forming the film 28, the resist is removed. Further, sintering is performed on the Al film 27 to complete this one conventional example.

[0014]

By the way, the wall of the mass spectrometer of the ion implantation apparatus contains a small amount of mobile ions such as Na ⁺ due to its raw material and manufacturing process. Therefore, when ions of Phos ⁺ 17 and As ⁺ 23 are implanted, ions other than these ions collide with the inner wall of the mass spectrometer, so that the movable ions 31 are sputtered from the inner wall as shown in FIGS. It comes and comes flying. In particular, since the dose amount is large at the time of ion implantation of As ⁺ 23,
At this time, the amount of flying mobile ions 31 is large.

However, since the movable ions 31 are secondary ions, they have low kinetic energy and reach only the surface of the SiO ₂ films 13 and 22 or the vicinity thereof. In addition, the mobile ions 31 pass through the SiO ₂ films 13 and 22 and the Si substrate 1
Even if it reaches to the middle of 1
Since os ⁺ 17 is injected and the mobile ions 31 are captured by this Phos ⁺ 17, there is no problem.

However, the mobile ions 31 easily move in the SiO ₂ film. Therefore, as a result of the subsequent heat treatment, as shown in FIG. 6, the movable ions 31 flying with the Phos ⁺ 17 move in the SiO ₂ film 13, and the moving ions 31 flying with the As ⁺ 23 move the SiO ₂ films 22, 21. It was easy for these mobile ions 31 to penetrate into the vicinity of the polycrystalline Si film 14, which is the floating gate, by moving inside.

When these movable ions 31 penetrate into the polycrystalline Si film 14 during operation, the electrons injected into the polycrystalline Si film 14 by the memory operation and the movable ions 31 are neutralized, The stored data may be lost. Therefore, it is difficult to say that the above-mentioned conventional example has excellent data retention characteristics. Therefore, the inventor of the present application, as shown in FIG. 7, ion-implants Phos ⁺ 17 in a state in which the polycrystalline Si films 14, 16 and the like are covered with the PSG film 32, and the PSG film 32 and the SiO ₂ film 21 are And polycrystalline S
An improved example of forming the side walls of the i films 14 and 16 has been considered.

In this improved example, the mobile ions 31 flying with Phos ⁺ 17 move in the SiO ₂ film 13 or the mobile ions 31 flying with As ⁺ 23 are SiO 2.
_When the mobile ions 31 move to the vicinity of the polycrystalline Si film 14 by moving in the _two films 22 and 21,
Can be prevented. However, even in this improved example, FIG.
As shown in, mobile ions 31 flying with As ⁺ 23
Move in the SiO ₂ films 22 and 13 and move to the polycrystalline Si film 14
It was not possible to prevent the invasion to the vicinity of.

[0019]

According to another aspect of the non-volatile semiconductor memory device of the present invention, a floating gate 14 on a gate oxide film 13 is provided.
A side wall 33 is provided on the floating gate 1 so that the side edge of the gate oxide film 13 is closer to the floating gate 1 than the side edge of the side wall 33.
4 is located below the side wall 33 and on the side wall 3
A portion between the side edge of the gate oxide film 13 and the side edge of the gate oxide film 13 is filled with the PSG film 34.

According to another aspect of the non-volatile semiconductor memory device of the present invention,
The first side wall 33 is formed on the floating gate 14 on the gate oxide film 13.
And a side edge of the gate oxide film 13 and a side edge of the first sidewall 33 are separated from the floating gate 14 by an equal distance. A second side wall 36 made of a PSG film covers the side end surface of the oxide film 13.

According to another aspect of the non-volatile semiconductor memory device of the present invention,
The nonvolatile semiconductor memory device according to claim 2, wherein a surface of a first portion of the semiconductor substrate 11 where the gate oxide film 13 is not provided is lower than a surface of a second portion below the gate oxide film 13. The second side wall 36 reaches the surface of the first portion.

[0022]

In the nonvolatile semiconductor memory device according to the first aspect, since the side end surface of the gate oxide film 13 is covered with the PSG film 34, the movable ions 31 enter the gate oxide film 13 from the side end surface of the gate oxide film 13. It is possible to prevent this from moving in the gate oxide film 13 and penetrating to the vicinity of the floating gate 14.

According to another aspect of the nonvolatile semiconductor memory device of the present invention,
Since the second side wall 36 made of the PSG film covers the side end face of the gate oxide film 13, the movable ions 31 enter from the side end face of the gate oxide film 13 into the gate oxide film 13 and move in the gate oxide film 13. As a result, it is possible to prevent the invasion to the vicinity of the floating gate 14.

Further, since the second side wall 36 made of the PSG film also covers the first side wall 33, the mobile ions 31 enter from the surface of the first side wall 33 into the first side wall 33. It is also possible to prevent it from moving in the side wall 33 of the above and penetrating to the vicinity of the floating gate 14.

Moreover, since the second side wall 36 is not the film covering the entire surface that prevents the invasion of the movable ions 31, the impurity 2 with the side walls 33, 36 and the like as a mask is used.
The diffusion layer 24 formed by the ion implantation of No. 3 can be made shallow.

In the non-volatile semiconductor memory device according to claim 3,
Since the second side wall 36 made of the PSG film covers not only the side end face of the gate oxide film 13 but also a portion deeper than the side end face, the movable ions 31 move from the side end face of the gate oxide film 13 to the gate oxide film 13. The effect of preventing the particles from moving into the gate oxide film 13 and penetrating to the vicinity of the floating gate 14 is further enhanced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First to third embodiments of the present invention applied to an EPROM will be described below with reference to FIGS.
The components corresponding to those of the conventional example shown in FIGS. 5 and 6 and the improved example shown in FIG. 7 are designated by the same reference numerals.

FIG. 2 shows the manufacturing method of the first embodiment. Also in the manufacture of the first embodiment, as shown in FIG. 2A, SiO ₂ as the gate oxide film for the floating gate is formed.
The same steps as in the case of manufacturing the conventional example described above are performed until the film 13 is formed and the control gate and the floating gate are formed by the polycrystalline Si films 16 and 14 as shown in FIG. 2B. To do.

However, in order to manufacture the first embodiment, the PSG film 32 having a film thickness of about 1 to 100 nm is then formed.
Is deposited on the entire surface, and then the same steps as those for manufacturing the above-mentioned conventional example are performed again to form an N ⁻ type diffusion layer 18.

Next, as shown in FIG. 2C, the BPSG film 33, etc., which has an etching rate slower than that of the SiO ₂ film 13, is removed by C
It is deposited to a film thickness of 300 nm by the VD method. However, BPS
The film thickness of the G film 33 is 300 n, which is equal to the film thickness of the PSG film 32.
It may be thinner than m. Then, RIE is performed on the entire surface of the BPSG film 33 and the exposed PSG film 32 and the SiO ₂ film 13 to form sidewalls made of the BPSG film 33 and the PSG film 32 on the polycrystalline Si films 14, 16 and the like.

After that, the side edge of the SiO ₂ film 13 is made to recede under the side wall by isotropic etching such as wet etching, and then the film thickness is 10 n at a temperature of 1000 ° C.
m SiO ₂ film (not shown) is formed. Then, a PSG film 34 having a film thickness of, for example, 50 nm is deposited on the entire surface, and RIE is performed on the entire surface of the PSG film 34 to obtain SiO 2.
_{2 The} PSG film 34 fills the cavity under the side wall formed by the receding of the film 13. The above-mentioned Si having a film thickness of 10 nm
The O ₂ film prevents diffusion of phosphorus from the PSG film 34,
This is for preventing the profile of the diffusion layer 18 from changing.

Thereafter, a SiO ₂ film, a PSG film and a SiO ₂ film each having a film thickness of 10 nm are sequentially deposited by the CVD method, and as shown in FIG. 1, an interlayer insulating film 35 composed of these three layer films is formed. 1000 in dry oxygen after forming
This interlayer insulating film 35 is densified by performing a heat treatment for 30 minutes at a temperature of ° C. Then, the same process as in the case of manufacturing the above-mentioned conventional example is executed again to form the N ⁺ type diffusion layer 24, and further, as shown in FIG.
To the syntax for completing the first embodiment.

In the first embodiment manufactured as described above,
Since formed on the entire surface of the PSG film 32 before the Phos ⁺ 17 ions are implanted, by trapping mobile ions 31 fly with Phos ⁺ 17 In this PSG film 32, the movable ions 31 of the polycrystalline Si film 14 It is possible to prevent invasion to the vicinity.

In particular, as shown in FIG. 1, Phos ⁺ 1
During ion implantation As ⁺ 23 a large amount of mobile ions 31 than the ion implantation of 7 flying, since the interlayer insulating film 35 comprising PSG film is formed on the entire surface, the mobile ions 31 fly with As ⁺ 23 This can be captured by the interlayer insulating film 35. Moreover, the BPSG film 33 that is the side wall
Since the PSG film 34 is also embedded in the lower part of the polycrystalline silicon film 1 even if the mobile ions 31 penetrate the interlayer insulating film 35, the mobile ions 31 move in the SiO ₂ film 13 and
It is possible to prevent invasion up to the vicinity of 4.

Further, preventing the invasion of the movable ions 31 can not only improve the data retention characteristics of the memory cell but also suppress the characteristics of the transistors in the peripheral circuits from changing over time. This has the effect of improving the reliability of the EPROM as a whole. Moreover, as is clear from the above description of the manufacturing method, it has good consistency with the steps of the manufacturing method of the conventional example shown in FIG. 5, is easy to introduce into the current production line, and increases the number of steps. There is little increase in manufacturing cost.

FIG. 3 shows a second embodiment. In the second embodiment, the PSG film 3 is formed below the BPSG film 33 which is the side wall.
4 is not provided, but the side wall made of the PSG film 36 is provided further outside the BPSG film 33, and the configuration is substantially the same as that of the first embodiment shown in FIGS. have.

In the second embodiment as described above, the movable ions 31
Can be prevented by the PSG film 36 from entering the SiO ₂ film 13, and before the formation of the interlayer insulating film 35
Since s ⁺ 23 can be ion-implanted, the acceleration energy of As ⁺ 23 can be lowered and ΔR _P can be reduced as compared with the first embodiment described above.
The diffusion layer 24 can be shallow.

FIG. 4 shows a third embodiment. In the third embodiment, the surface of the portion of the Si substrate 11 where the SiO ₂ film 13 is not provided is lower than the surface of the portion below the SiO ₂ film 13 by 0.1 to 0.2 μm. The second embodiment has substantially the same configuration as that of the second embodiment shown in FIG. The depth of the diffusion layer 18 is 0.3 μm.
It is a degree. For this reason, the mobile ions 31 are transferred to the SiO ₂ film 1.
The effect of preventing penetration from the side end face of No. 3 into the SiO ₂ film 13 is greater than that of the second embodiment.

Although the first to third embodiments described above apply the invention of the present application to the EPROM, the invention of the present application can also be applied to the EEPROM and the like.

[0040]

According to the nonvolatile semiconductor memory device of the first aspect, it is possible to prevent mobile ions from moving in the gate oxide film and penetrating into the vicinity of the floating gate.
It is possible to prevent the stored data from being erased by neutralizing the electrons that have been injected into the floating gate and the mobile ions that have penetrated into the floating gate. There is.

According to another aspect of the non-volatile semiconductor memory device of the present invention,
Since it is possible to prevent mobile ions from moving in the gate oxide film or in the first side wall and penetrating into the vicinity of the floating gate, the electrons that have been injected into the floating gate and the floating ions have also penetrated into the floating gate. It is possible to prevent the stored data from being erased by neutralization with mobile ions,
Excellent data retention characteristics.

Moreover, since the diffusion layer formed by ion implantation of impurities using the sidewalls and the like as a mask can be made shallow, the short channel effect can be reduced, and miniaturization can be promoted.

In the non-volatile semiconductor memory device according to claim 3,
Since the effect of preventing mobile ions from moving in the gate oxide film and penetrating to the vicinity of the floating gate is even greater,
The effect of preventing the stored data from being erased by the neutralization of the electrons injected into the floating gate and the mobile ions penetrating into the floating gate is further enhanced, and the data retention characteristic is further improved. Are better.

[Brief description of drawings]

FIG. 1 is an enlarged side sectional view of a main part of a first embodiment of the present invention in a manufacturing process.

FIG. 2 is a side sectional view showing the manufacturing method of the first embodiment in the order of steps.

FIG. 3 is an enlarged side sectional view of a main part of the second embodiment in the manufacturing process.

FIG. 4 is an enlarged side sectional view of a main part of the third embodiment in the manufacturing process.

FIG. 5 is a side sectional view showing a manufacturing method of a conventional example of the invention of the present application in the order of steps.

FIG. 6 is an enlarged side sectional view of a main part of a conventional example in a manufacturing process.

FIG. 7 is an enlarged side sectional view of a main part of an improved example by the inventor of the present application.

[Explanation of symbols]

11 Si substrate 13 SiO ₂ film 14 Polycrystalline Si film 33 BPSG film 34 PSG film 36 PSG film

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A floating gate on a gate oxide film is provided with a side wall, a side edge of the gate oxide film is located closer to the floating gate than a side edge of the side wall, and A non-volatile semiconductor memory device in which a portion between the side edge of the side wall and the side edge of the gate oxide film is filled with a PSG film. 2. A floating gate on the gate oxide film is provided with a first side wall, and a side edge of the gate oxide film and a side edge of the first side wall are equal in distance from the floating gate. The first side wall and the side end surface of the gate oxide film are separated from each other by PS.
A nonvolatile semiconductor memory device in which a second side wall made of a G film covers. 3. The surface of a first portion of the semiconductor substrate where the gate oxide film is not provided is lower than the surface of a second portion below the gate oxide film, and the first portion The nonvolatile semiconductor memory device according to claim 2, wherein the second sidewall reaches the surface of the non-volatile semiconductor memory device.