JP3416725B2 - Insulated gate field effect transistor and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI type insulated gate field effect transistor suitable for use at high frequency and high voltage, and a method for manufacturing the same.

[0002]

2. Description of the Related Art A plan view of an insulated gate field effect transistor according to the prior art is shown in FIG. 4 and 4A-4A 'in FIG.
A sectional view is shown in FIG. 5 (a), and a sectional view taken along 4B-4B 'is shown in FIG. 5 (b). Here, the first crystal silicon semiconductor substrate 101
A semiconductor substrate having a stacked structure of an SOI method, which has an insulating film 102 made of, for example, a silicon oxide film on the main surface side and has a single crystal silicon semiconductor layer 103 on the upper surface of the insulating film 102, is used.

In the single crystal silicon semiconductor layer 103, a p-type channel region 104, a high-concentration n-type source region 105 continuous with the channel region 104, and a channel region 10 are formed.
4 and the source region 105, the source region 1 is continuous with the high-concentration p-type body contact region 106 and the channel region 104 formed so as to divide the source region 105 into a plurality of regions.
05 and the body contact region 106, a low-concentration n-type drain offset region 107 formed on the opposite side, and a high-concentration n-type drain region 108 continuous to the drain offset region 107 are formed. The body contact region 106 is held at the substrate potential (ground potential).

A gate insulating film 1 is formed on the channel region 104.
09, a gate electrode 110 is formed, a source electrode 111 is formed on the upper surfaces of the source region 105 and the body contact region 106, a drain electrode 112 is formed on the upper surface of the drain region 108, and the gate electrode 11 is formed.
0 is covered with an insulating film 113 (reference document: S.Ma.
tsumoto et al., "Device Characteristics of a 30-V-
CIss Thin-Film SOIPower MOSFET ", IEEE Trans. Electr
on Devices, vol.ED-43, p.746, 1996).

FIG. 6 is a plan view of another conventional insulated gate field effect transistor, and 6A-6 in FIG.
Fig. 7 (a) is a sectional view taken along line A ', and Fig. 7 (b) is a sectional view taken along line 6B-6B'.
It was shown to. Again, the single crystal silicon semiconductor substrate 201
On the first main surface side of the insulating film 2 made of, for example, a silicon oxide film
02, and a semiconductor substrate having an SOI stacked structure having a single crystal silicon semiconductor layer 203 over the insulating film 202 is used.

In the single crystal silicon semiconductor layer 203, a p-type channel region 204, a high-concentration n-type source region 205 continuous with the channel region 204, and a channel region 20.
4 and the source region 205 so as to divide the source region 205 into a plurality of p-type body contact regions 2
06, a low-concentration n-type drain offset region 207 continuous with the channel region 204 and on the opposite side of the source region 205 or the body contact region 206, and a high-concentration n-type drain region 208 continuous with the drain offset region 207 are formed. Has been done.

A gate insulating film 2 is formed on the channel region 204.
09, the gate electrode 210 is formed, the source electrode 211 is formed on the upper surfaces of the source region 205 and the body contact region 206, and the drain electrode 212 is formed on the upper surface of the drain region 208.
0 is covered with an interlayer film 213 (reference: J. Sl)
eight et al., "A Compact Body Contact Technology fo
r SOI Transistor ", in Tech.Dig.IEEE IEDM'97, Sessio
n 16.4, 1997).

[0008]

However, as shown in FIG. 4 and FIG.
In the conventional insulated gate field effect transistor shown in FIG. 3, the body contact region 106 has a high concentration so that it makes ohmic contact with the source electrode 111, and during photolithography, the alignment margin and the p-type Considering mutual diffusion of impurities and n-type impurities, it is necessary to increase the width of the body contact region 106, which increases the element area by that amount and increases the input capacitance of the field effect transistor. It was not suitable for conversion.

On the other hand, in another conventional insulated gate field effect transistor shown in FIGS. 6 and 7, the body contact region 206 has a low concentration so as to make a Schottky contact with the source electrode 205, and the photolithography is performed. At the time of (a), it is not necessary to consider the alignment margin and the mutual diffusion of the p-type impurity and the n-type impurity, and the body contact region 206 can be made narrower, and the element area can be reduced accordingly. , The input capacity is reduced and the speed can be increased.

However, the body contact region 20
Since 6 has a low concentration, electric field concentration occurs at the channel end, the parasitic MOSFET at the channel edge easily operates, and the operation of the insulated gate field effect transistor becomes unstable.

An object of the present invention is to suppress the increase in the lateral surface of the device to achieve high speed operation, but to alleviate the electric field concentration at the channel edge to suppress the operation of the parasitic MOSFET at the channel edge, thereby reducing the transistor operation. (EN) A stabilized insulated gate field effect transistor and a method for manufacturing the same.

[0012]

A first invention for solving the above problems provides a semiconductor substrate having a laminated structure having a single crystal silicon semiconductor layer on a single crystal silicon semiconductor substrate via a first insulating film. A channel region of a first conductivity type in the single crystal silicon semiconductor layer, a source region of a second conductivity type opposite to the first conductivity type that is continuous with the channel region, and a channel region that is continuous with the channel region. A drain offset region of the second conductivity type located on the opposite side of the source region and having a lower concentration than that of the source region; and a second conductivity type of the second conductivity type continuous with the drain offset region and having a higher concentration than the drain offset region. A drain electrode, a gate electrode is formed on at least the channel region via a gate insulating film, a source electrode is formed on the source region, and the drain region is formed. In an insulated gate field effect transistor in which a drain electrode is formed in the source electrode, a high concentration first conductivity type first body contact region that makes ohmic contact with the source electrode is continuous with the channel region and is provided outside the source region. The second body contact region of the first conductivity type having a low concentration and in Schottky contact with the source electrode is continuous with the channel region and the source region and is divided into a plurality of source regions.

A second invention is the manufacturing method of the first invention, in which the semiconductor substrate of the first invention is prepared and a channel region in the first conductivity type single crystal silicon semiconductor layer of the semiconductor substrate is provided. Forming a gate insulating film on the upper surface of the region including the portion to be formed, then forming a gate electrode on the upper surface of the gate insulating film, and then forming a second conductivity type drain offset region in the single crystal silicon semiconductor layer. Then, second conductivity type ion implantation is performed on the portion of the single crystal silicon semiconductor layer that will be the source region, and first conductivity type ion implantation is performed on the portion that will be the first body contact region. Is ion-implanted into the portion to be the drain region and second-conductivity type is implanted into the region to be the drain region to diffuse, and thereafter, the upper surface of the source region and the first and second body contact regions. The source electrode, and configured to respectively form a drain electrode on the upper surface of the drain region.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a plan view of an insulated gate field effect transistor according to the present invention.
1A is a cross-sectional view taken along the line 1A-1A 'in FIG. 1, and FIG. 2B is a line 1B in FIG.
-1B 'sectional drawing, FIG.2 (c) is 1C-1C' sectional drawing of FIG.

In the insulated gate field effect transistor of this embodiment, for example, a single crystal silicon semiconductor is formed on the first main surface side of a p-type high resistance single crystal silicon semiconductor substrate 10 with an insulating film 11 made of, for example, a silicon oxide film interposed therebetween. A layered substrate of SOI with layer 1 is used. The single crystal silicon semiconductor layer 1 is a field insulating film 2 made of a silicon oxide film.
Is surrounded by the single crystal silicon semiconductor layer 1
Has a gate electrode 4 on the first main surface side with a gate insulating film 3 interposed therebetween.

In the single crystal silicon semiconductor layer 1, a high-concentration p-type first body contact region 6 is formed outside the source region portion, and the high-concentration n-type source region 5 inside the first body contact region 6 has a low concentration p. Second body contact region 7 of the mold
Is divided into a plurality. Further, in the single crystal silicon semiconductor layer 1, a p-type channel region 12 located below the gate insulating film 3 and the gate electrode 4, a low-concentration n-type drain offset region 8, and a high-concentration n-type drain region 9 are formed.
Are formed. An insulating film 13 made of an oxide film covers the gate electrode 4. A source electrode 14 is connected to the source region 5, the first body contact region 6 and the second body contact region 7, and a drain electrode 15 is connected to the drain region 9. First and second body contact regions 6,
7 is held at the substrate potential (ground potential).

In this embodiment, since the first body contact region 6 arranged at the source end (upper and lower sides in FIG. 1) has a high concentration so that the contact with the source electrode 14 becomes ohmic contact, the channel end is formed. The threshold voltage of the parasitic MOSFET increases, the operation of the parasitic MOSFET is suppressed, and the operation of the insulated gate field effect transistor is stabilized. Further, since the second body contact region 7 arranged so as to divide the source region 5 has a low concentration so as to make a Schottky contact with the source electrode 14, the area of the body contact region 7 can be reduced (the first body contact region). 6), the parasitic capacitance can be reduced and the speed can be increased by reducing the element area. The second body contact region 7 has the smallest width, the first body contact region 6 has the second largest width, and the source region 5 has the second largest width.

[Second Embodiment] FIG. 3 is an explanatory view of an initial portion of a method of manufacturing the insulated gate field effect transistor shown in FIGS. In the present embodiment, the SO in which the single crystal silicon semiconductor layer 1 is provided on the p-type high resistance single crystal silicon semiconductor substrate 10 with the silicon oxide film 11 interposed therebetween, for example.
A semiconductor substrate having a laminated structure of I is used.

Then, after forming a portion 12 'which becomes the channel region 12 in the single crystal silicon semiconductor layer 1, a gate oxide film 3 is formed and, for example, phosphorous polycrystal silicon is deposited and processed to form a gate electrode 4 (FIG. 3 (a)). After that, phosphorus is ion-implanted and diffused on the side to be the drain offset region 8 to form a low concentration n-type region 8 ′. (Fig. 3 (b)).

Thereafter, for example, boron is ion-implanted only in the corresponding region to form the p-type second body contact region 7 which becomes the Schottky contact, and the high-concentration n-type source region 5 and the high-concentration n-type are formed. For example, phosphorus is ion-implanted only in the corresponding region to form the drain region 9 of the same, and boron is ion-implanted only in the corresponding region to form the p-type high-concentration first body contact region 6 that becomes ohmic contact. After that, diffusion is performed. Thereby, the source region 5, the first body contact region 6, the second
Body contact region 7 and drain region 9 are formed.

After that, for example, a silicon oxide film is deposited and processed to form an insulating film 13, and then, for example, aluminum is deposited and processed to form a source electrode 14 and a drain electrode 15. Through the above steps, the insulated gate field effect transistor shown in FIGS. 1, 2A and 2B is completed.

It is needless to say that the p-type and n-type conductivity types described above can be reversed.

[0023]

As described above, according to the present invention, the high-concentration first body contact region is arranged outside the source region so that the contact with the source electrode is an ohmic contact. The operation of the parasitic transistor is suppressed and the operation is stabilized. Further, since the second body contact region is made lighter in concentration to form the source electrode and the Schottky barrier, the area of the second body contact region can be reduced, the parasitic capacitance can be reduced, and the speed can be increased.

[Brief description of drawings]

FIG. 1 is a plan view of an insulated gate field effect transistor of the present invention.

2A is a sectional view taken along the line 1A-1A ′ in FIG. 1, and FIG.
1B-1B 'sectional view, and (c) is a 1C-1C' sectional view of FIG.

3 (a) and 3 (b) are explanatory views of an initial stage portion of the method for manufacturing an insulated gate field effect transistor of the present invention.

FIG. 4 is a plan view of a conventional insulated gate field effect transistor.

5A is a cross-sectional view taken along the line 4A-4A ′ in FIG. 4, and FIG.
4B-1B 'is a cross-sectional view of FIG.

FIG. 6 is a plan view of another conventional insulated gate field effect transistor.

7A is a sectional view taken along line 6A-6A ′ of FIG. 6, and FIG.
FIG. 6B is a sectional view taken along line 6B-6B ′ of FIG.

[Explanation of symbols]

1: single crystal silicon semiconductor layer, 2: field insulating film,
3: gate insulating film, 4: gate electrode, 5: high concentration source region, 6: high concentration first body contact region, 7: low concentration second body contact region, 8: low concentration drain offset region, 9: high concentration Drain region, 10: high-resistance single crystal silicon semiconductor substrate, 11: insulating film, 12: channel region, 13: insulating film, 14: source electrode, 15: drain electrode.

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Claims (2)

(57) [Claims] 1. A semiconductor substrate having a laminated structure having a single crystal silicon semiconductor layer on a single crystal silicon semiconductor substrate via a first insulating film, wherein a channel of the first conductivity type is provided in the single crystal silicon semiconductor layer. A region, a source region of a second conductivity type opposite to the first conductivity type that is continuous with the channel region, and a source region of the second conductivity type that is located opposite to the source region and continuous with the channel region. A drain offset region having a concentration lower than that of the drain offset region, and a drain region of the second conductivity type having a concentration higher than that of the drain offset region and continuous to the drain offset region, and a gate insulating film at least on the channel region. An insulating gate field effect transistor having a gate electrode formed therethrough, a source electrode formed in the source region, and a drain electrode formed in the drain region. In the transistor, a high-concentration first body type contact region of the first conductivity type that is in ohmic contact with the source electrode is provided outside the source region so as to be continuous with the channel region, and a low concentration of Schottky contact with the source electrode is provided. And second of the first conductivity type
An insulated gate field effect transistor, characterized in that a body contact region is connected to the channel region and the source region and the source region is divided into a plurality of parts. 2. A semiconductor substrate according to claim 1 is prepared, and a gate insulating film is formed on an upper surface of a region including a portion to be a channel region in the first conductivity type single crystal silicon semiconductor layer of the semiconductor substrate, After that, a gate electrode is formed on the upper surface of the gate insulating film, and then a second electrode is formed in the single crystal silicon semiconductor layer.
A conductive type drain offset region is formed, and thereafter, a second conductive type ion implantation is performed in a portion of the single crystal silicon semiconductor layer that becomes a source region, and a first conductive type ion implantation is performed in a portion that becomes a first body contact region. And ion implantation of the first conductivity type into a portion to be the second body contact region,
A second conductivity type ion is implanted and diffused into a portion to be a drain region, and then a source electrode is formed on the upper surfaces of the source region and the first and second body contact regions, and a drain electrode is formed on the upper surface of the drain region. The method for manufacturing an insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor is formed.