JP3409639B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical power device using a U-shaped insulating electrode.

[0002]

2. Description of the Related Art As a structure related to the present invention, there is an apparatus described in Japanese Patent Application Laid-Open No. 6-252408 published by the present applicant. Since the basic structure of the above-mentioned device is similar to that of the embodiment of the present invention except for the characteristic part of the present invention, the structure of the conventional device will be described with reference to FIGS. 1 to 4 showing the embodiment of the present invention. Will be explained. It should be noted that the numbers and names of parts in the drawings are appropriately changed for description.

FIG. 1 is a bird's eye view showing the semiconductor device. Figure 2
Is a cross-sectional view and corresponds to the front cross-section in FIG. FIG. 3 is another cross-sectional view of the semiconductor device, showing the same part as the cross section of the side surface of FIG. 4 is a front view of the semiconductor device, which is the same portion as the upper surface of FIG. FIG. 1 is a cross-sectional view taken along a plane perpendicular to the plane of the drawing through the line segment AA ′ in FIG. 4, and FIG. 3 is a cross-sectional view taken along a plane perpendicular to the line segment BB ′. .

In the figure, reference numeral 1 is an n + type substrate region, 2 is an n − type drain region, and 3 is an n + type source region. On the semiconductor surface, there are a plurality of trenches whose sidewalls are almost vertical and parallel to each other. A MOS type electrode 4 made of p + type polysilicon is embedded in the inner wall thereof so as to be insulated from the surrounding n type region by an insulating film 5. Further, as shown in FIG. 2, the source electrode 13 is in ohmic contact with the source region 3 and the MOS type electrode 4. Therefore,
Since the MOS type electrode 4 is always at the same potential as the source region 3, the MOS type electrode 4 and the insulating film 5 are collectively referred to as "fixed potential insulating electrode 6". 7 is the drain region 2
In the part sandwiched between the two fixed potential insulated electrodes 6,
This is the channel region of this semiconductor device. Reference numeral 8 denotes a gate region formed of a p-type semiconductor region, which is separated from the source region 3 but is in contact with the drain region 2 and the insulating film 5. Reference numeral 9 is an interlayer insulating film. Reference numeral 11 is a drain electrode which makes ohmic contact with the drain region 1, and 18 is a gate electrode which makes ohmic contact with the gate electrode 8. Note that, in order to clarify the explanation, in FIGS. 1 and 4, the description of the surface electrode shown in FIGS. 2 and 3 is omitted.

The operation of this semiconductor device will be described. Figure 1
In the semiconductor device shown in FIG. 4, the source electrode is grounded (0 V
The drain electrode is connected to a proper positive potential via a load before use.

Description will be made with reference to FIG. First, the device is in the cutoff state, but when the gate electrode 18 is grounded, the device is in the cutoff state. A depletion region associated with the built-in potential is formed around the fixed potential insulated electrode 6, but the distance between two fixed potential insulated electrodes facing each other in the channel region (hereinafter,
If this is called "channel thickness H"), the depletion region forms a sufficient potential barrier for conduction electrons in the channel region 7.
For example, the impurity concentration of the channel region 7 is 1 × 10 ¹⁴ cm
By setting the “channel thickness H” to about 2 μm or less to about ³ to obtain a sufficient potential barrier that prevents conduction electrons of the n + type source region from moving to the drain region 2 side through the channel region 7. You can

Further, the distance from the source region 3 to the bottom of the fixed potential insulating electrode 6 (hereinafter, referred to as "channel" is referred to as "channel" so that the height of the potential barrier is not lowered by the influence of the electric field from the drain region 2 side. The length L ”is set to be 2 to 3 times or more the channel thickness H. Under this condition, the cutoff state of the channel region 7 is maintained until the avalanche breakdown condition.

Next, the gate electrode 18 is turned on.
When a positive potential is applied to the p-type gate region 8, the potential of the p-type gate region 8 rises and holes flow into the interface of the insulating film in contact with the p-type gate region 8 to form an inversion layer. Inversion layer is p + type MOS type electrode 4
Since the electric field from to the channel region 7 is shielded, the depletion region shrinks or disappears, and the channel opens. When the potential of the gate region 8 becomes higher, the p-type gate region 8 and n
Between the drain region 2 or the channel region 7 of the mold
The n-junction is in a forward bias state, and holes that are minority carriers are injected into the n-type region. These n-type regions are made to have a low impurity concentration in order to improve the high breakdown voltage or the blocking property of the channel. Therefore, when a large number of minority carriers are injected, the conductivity is improved and the n-type regions are emitted from the source region 3. The electrons move to the substrate region 1 with high conductivity.

By the way, the current flowing into the gate electrode 18 becomes a hole flow from the p-type gate region 8 and finally almost all flows into the source region 3. Most of it spreads inside the drain region 2 and contributes to the improvement of the conductivity of this region, but there is also a part that flows along the interface of the insulating film 5 and flows into the source region 3 at the shortest distance. Since this portion does not contribute to the conductivity modulation of the drain region 2, if there are many portions, the so-called "current amplification factor" (drain current / gate current) ratio becomes low and the efficiency deteriorates.

[0010]

As described above, in this semiconductor device, there is a portion of the injected holes that does not contribute to conductivity modulation of the drain region, and the current amplification factor is not improved as expected. was there. An object of the present invention is to solve such a problem and to realize a semiconductor device having such a structure with a high current amplification factor.

[0011]

[Means for Solving the Problems] In order to solve the problems,
The present invention has a configuration as described in the claims. That is, in claim 1, first, the semiconductor device having the following structure is targeted. For example, one main surface of the drain region, which is an n-type semiconductor, has a plurality of grooves arranged in parallel to each other. A source region of the same conductivity type (here, n-type) is provided on the main surface sandwiched by the trench, and the drain region is insulated from the drain region by an insulating film inside the trench, and has the same potential as the source region. Having a fixed potential insulated electrode maintained at. It should be noted that this electrode is made of a conductive material (for example, p + type polysilicon) having a property of forming a depletion region in the drain region adjacent to the insulating film. Further, the drain region and the gate region of the opposite conductivity type (here, p-type) not in contact with the source region and in contact with the drain region and the insulating film are provided, and one of the drain regions adjacent to the source region is further provided. And a channel region sandwiched between the fixed potential insulated electrodes. When the potential of the gate region is kept at the same potential as the potential of the source region, the potential barrier formed by the depletion region in the channel region electrically connects the source region and the drain region. In the cutoff state, the potential of the gate region is such that the pn junction formed between the gate region (here, p type) and the source region (here, n type) is in a forward bias state. Is formed by forming an inversion layer (here, formed of holes) at the interface of the insulating film in contact with the gate region, and shielding the electric field from the fixed potential insulating electrode forming the depletion region, Shrinking or eliminating the depletion region to make the channel region conductive,
Further, the conductivity of the drain region is improved by injecting minority carriers (here, holes) into the drain region.

With respect to the above construction, Japanese Patent Laid-Open No. 6-
No. 252408 filed by the applicant. In the present invention, in the semiconductor device having such a structure, the insulating film interface (that is, the sidewall of the groove) in contact with the channel region further has at least the mobility among the minority carriers (here, holes). It is configured to have a plane orientation with low mobility in a direction parallel to the main surface (that is, a direction connecting the source region and the gate region). Note that the "plane orientation with low mobility" means selecting a plane orientation in which the mobility of the minority carrier is lower than other plane orientations among various crystal plane orientations of a semiconductor. Specifically, the plane orientation as described in claims 2 and 3 is applicable.

A second aspect limits one of the more specific constitutions of the first aspect, but when the channel region is an n-type silicon single crystal region, minority carriers (here, holes) are used. The interface of the insulating film where the inversion layer is formed (that is, the sidewall of the groove) is a {100} plane having a low mobility for the minority carriers (holes in this case).

Further, claim 3 limits one of the more specific constitutions of claim 1 as well, but when the channel region is a p-type silicon single crystal region, minority carriers (electrons here). The insulating film interface (that is, the sidewall of the groove) on which the inversion layer is formed is {110}
And a direction parallel to the main surface (that is, a direction in which electrons in the inversion layer move from the gate region to the source region) is a <110> direction in which mobility with respect to the minority carriers (here, electrons) is low. It has a certain structure.

[0015]

According to the structure of the present invention as described above, even when the same gate current is injected as compared with the case where it is not, of the minority carriers injected from the gate region, the The current that flows through the inversion layer to the source region and does not contribute to conductivity modulation of the drain region is reduced, and as a result, the current amplification factor is improved.

Further, claim 2 is a more specific limitation of claim 1. When this transistor is formed on an n-type silicon substrate, if the plane orientation is selected as described above, the current amplification will be the highest. The rate is improved.

Also, claim 3 is a more specific limitation of claim 1, but when this transistor is formed on a p-type silicon substrate, if the plane orientation is selected as described above, The current amplification factor is most improved.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention is described in detail below.
1 to 4 are views showing an embodiment of the present invention, and FIG. 1 is a bird's-eye view showing the semiconductor device. FIG. 2 is a cross-sectional view and corresponds to the cross section of the front surface in FIG. FIG. 3 is another cross-sectional view of the semiconductor device, showing the same part as the cross section of the side surface of FIG. 4 is a front view of the semiconductor device, which is the same portion as the upper surface of FIG. FIG. 1 is a cross-sectional view taken along a plane perpendicular to the plane of the drawing through the line segment AA ′ in FIG. 4, and FIG. 3 is a cross-sectional view taken along a plane perpendicular to the line segment BB ′. .

In the figure, reference numeral 1 is an n + type substrate region, 2 is an n − type drain region, and 3 is an n + type source region. On the semiconductor surface, there are a plurality of trenches whose sidewalls are almost vertical and parallel to each other. A MOS type electrode 4 made of p + type polysilicon is embedded in the inner wall thereof so as to be insulated from the surrounding n type region by an insulating film 5. Further, as shown in FIG. 2, the source electrode 13 is in ohmic contact with the source region 3 and the MOS type electrode 4. Therefore,
Since the MOS type electrode 4 is always at the same potential as the source region 3, the MOS type electrode 4 and the insulating film 5 are collectively referred to as "fixed potential insulating electrode 6". 7 is the drain region 2
In the part sandwiched between the two fixed potential insulated electrodes 6,
This is the channel region of this semiconductor device. Reference numeral 8 denotes a gate region formed of a p-type semiconductor region, which is separated from the source region 3 but is in contact with the drain region 2 and the insulating film 5. Reference numeral 9 is an interlayer insulating film. Reference numeral 11 is a drain electrode which makes ohmic contact with the drain region 1, and 18 is a gate electrode which makes ohmic contact with the gate electrode 8. Note that, in order to clarify the explanation, in FIGS. 1 and 4, the description of the surface electrode shown in FIGS. 2 and 3 is omitted.

The device structure according to the present invention as described above is basically the same as that described in the section of the prior art, and the only difference is the plane orientation of the interface in contact with the insulating film 5 in the channel region 7. Is. Also, since the basic operation of the device is the same as described in the section of the prior art,
The description will be omitted, and the features of the present invention will be described below.

FIG. 5 shows the above-mentioned semiconductor device (channel region 7).
Is a n-type silicon), and the device is formed with the plane orientation of the insulating film interface of the channel region 7 as the {110} plane and the direction of the flow of holes as the <110> axis direction. It is a graph which measured and compared the current amplification factor, although it was made by setting the plane orientation of the same interface as {100}. The horizontal axis of the graph is the drain current density of the transistor chip, and the vertical axis is the so-called "current amplification factor" (drain current value /
Gate current value).

As shown in FIG. 5, the transistor according to the present invention in which the plane orientation of the insulating film interface is {100} has a higher current amplification factor. Although the drain region 2 of the prototype transistor was epitaxially grown on the substrate region 1, the thickness of the drain region was set to about 50 μm so that the semiconductor device has a breakdown voltage of at least 600V. The drain-source voltage at the time of measurement is 5V.

Further, FIGS. 1 to 4 show a version in which the substrate region 1 is an n-type, which corresponds to claim 2. According to the present invention, as described in claim 3, for example, the substrate region 1 is p-type (when the channel region 7 is p-type silicon), and the conductivity types of all the semiconductor regions are exchanged. That is, in this case, since an inversion layer due to electrons is formed at the interface of the insulating film, the plane orientation having the lowest electron inversion layer mobility, that is, the {110} plane is selected, and the direction of the electron flow is selected. The structure may be made so that the direction parallel to the surface of is the <110> direction.

The present invention is not limited to the above-mentioned silicon, and is similarly applicable to the case of using a compound semiconductor such as germanium, SiC, or a III-V group semiconductor.

[Brief description of drawings]

FIG. 1 is a perspective view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 3 is another sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 4 is a surface view showing an embodiment of a semiconductor device according to the present invention.

FIG. 5 is a graph of current amplification factor for explaining the effect of the present invention.

[Explanation of symbols]

1 ... Substrate area 2 ... Drain region 3 ... Source area 4 ... MOS type electrode 5 ... Insulating film 6 ... Fixed potential insulated electrode 7 ... Channel area 8 ... Gate area 9 ... Interlayer insulating film 11 ... Drain electrode 13 ... Source electrode 18 ... Gate electrode H ... Channel thickness L ... Channel length

Claims (3)

(57) [Claims] 1. A source region of the same conductivity type having a plurality of grooves arranged in parallel with each other on one main surface of a semiconductor substrate of one conductivity type which is a drain region, and the main surface sandwiched by the grooves. In the inside of the groove, the drain region is insulated from the drain region by an insulating film, and has a fixed potential insulating electrode kept at the same potential as the source region, the fixed potential insulating electrode, It is made of a conductive material having a property of forming a depletion region in the drain region which is adjacent to the drain region through the insulating film, and has an opposite conductivity which does not contact the source region and contacts the drain region and the insulating film. A gate region of a mold, a part of the drain region adjacent to the source region, and a channel region sandwiched between the fixed potential insulating electrodes, the potential of the gate region is Electric And a potential barrier formed by the depletion region in the channel region, the source region and the drain region are electrically cut off, and the potential of the gate region is When the potential is such that the pn junction formed between the gate region and the source region is in a forward bias state, an inversion layer is formed at the interface of the insulating film in contact with the gate region and the depletion region is formed. The electric field from the fixed potential insulated electrode that is being formed is shielded,
A semiconductor device having a structure in which the depletion region is reduced or disappears to bring the channel region into a conductive state, and the conductivity of the drain region is improved by injecting minority carriers into the drain region. The semiconductor device is configured such that the interface in contact with the insulating film has a plane orientation in which at least minority carrier mobility in a direction parallel to the main surface is low. 2. The semiconductor device according to claim 1, wherein the channel region is an n-type silicon single crystal region, and a plane orientation of the insulating film interface is a {100} plane. 3. The channel region is a p-type silicon single crystal region, a plane orientation of the insulating film interface is a {110} plane, and a crystal axis direction parallel to the main surface is a <110> direction. The semiconductor device according to claim 1, wherein the semiconductor device is provided.