JP3408721B2 - Synthetic diversity receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to obtaining reliable reception data in a radio apparatus that performs combined diversity reception using reception data from a plurality of branches in the communication field.

[0002]

2. Description of the Related Art FIGS. 9 and 10 are block diagrams showing the configuration of a general conventional combining diversity receiver. First, in the apparatus having the configuration shown in FIG. 9, a receiver having N branches and a plurality of antennas 11 and 12 for receiving radio waves
1N and detection and (RS
SI) a detection unit 21, 22 to 2N that performs measurement, a synthesis diversity processing unit 100 that performs synthesis diversity processing based on RSSI information obtained by the detection unit for each branch,
The reception data processing unit 200 processes the reception data based on the demodulation data subjected to the combining diversity process. In this case, the reference clock used for the combining diversity is always the demodulation clock of the branch 1, and the reference clock is fixed.

The apparatus having the configuration shown in FIG. 10 has frame reference signal detection units 31, 32 to 3N for detecting a frame reference signal for each branch, and the phase information timing of each branch is adjusted according to the detected timing. Combined diversity receiver with phase correction 101, received data processor 20 for processing received data based on demodulated data
It consists of zero.

Next, the operation of the conventional device will be described. First, in the first conventional combining diversity receiver shown in FIG. 9, the detection unit 2 corresponding to each antenna receives the radio waves received by the plurality of antennas 11 and 12 to 1N.
Detection and RSSI measurement are performed at 1, 22 to 2N. The phase information and RSSI information after detection are output from the detection unit and input to the combining diversity processing unit 100b. Further, the demodulation clock is input to the synthesis diversity processing unit 100b from the detection unit 21 which is set in advance as the reference clock generation unit. Of course, the demodulation clock is output by the detection unit 21.
However, it is not limited to this and may be anywhere from 21 to 2N set in advance. The combining diversity processing unit performs a combining diversity process for each branch based on the RSSI information. Synthetic diversity processing simply calculates the demodulated data by simply adding the phase information of each branch, or weights the phase information of each branch in proportion to the level of the RSSI information, and then adds them. This is a process for obtaining demodulated data with higher accuracy than that of a normal receiving circuit, for example. The demodulated data subjected to the combining diversity process is input to the reception data processing unit 200b, where the reception data is processed. Therefore, according to this combined diversity receiver, even if the received electric field level fluctuates due to fading or the like and the received electric field levels of some branches drop, good reception sensitivity can be obtained by combining the received data of multiple branches. Can be maintained, and stable processing of received data becomes possible.

Further, in the second conventional combining diversity receiver shown in FIG. 10, a plurality of antennas 11 and 12 are provided.
The radio waves received at 1N to 1N are detected by the detection units 21, 22 to 2N corresponding to the respective antennas and the RSSI is measured. Phase information after detection, demodulation clock, R
The SSI information is output, and the frame reference signal detector 51,
52 to 5N. The frame reference signal detection unit detects the frame reference signal based on the phase information, and inputs the timing as a frame signal to the phase-combining combined diversity receiver 111. The combining diversity processing unit with phase correction corrects the phase shift based on the frame signal for each branch, and then performs the combining diversity processing based on the RSSI information. Therefore, according to this combined diversity receiver, the reception electric field level fluctuates due to fading or the like, and even if the reception electric field levels of some branches drop, good reception sensitivity can be maintained by combining, and It is possible to process the received data stably without being adversely affected by the phase shift of the demodulation clock of each branch.

[0006]

The conventional combined diversity receiver is constructed as described above. In the first conventional example, the received electric field level drops due to fading and the interfering wave with a large received electric field level is input. If the reception state of the branch used as the reference clock is significantly deteriorated, there is a problem that the reference clock of the branch deviates from the correct timing. Further, in the second conventional example, since the phase shift of the demodulation clock of each branch is corrected, the correct timing can be obtained and the received data due to the correct timing can be correctly demodulated. However, there is a problem that the circuit scale becomes large. It was

The present invention has been made in order to solve the above problems. By selecting a demodulation clock of a branch in a stable receiving state as a reference clock, the circuit scale can be reduced and received data can be received without error. The purpose is to obtain a combining diversity receiver for combining.

[0008]

A combination diversity receiver according to the present invention has a structure in which radio waves from a plurality of branches are respectively demodulated and then combined and received.
Each of the demodulation clocks obtained in the demodulation circuit is input, and a reference clock selection unit that selects a demodulation clock of the highest level expected from the plurality of demodulation clocks or a measurement result and outputs it as a reference clock is provided. The combining diversity process is performed using the selected reference clock.

Furthermore, the level measurement is performed during a set period, and the demodulation clock is selected before the first reception timing at which each detection / demodulation circuit starts reception after the lapse of this predetermined period.

Furthermore, the level measurement is performed in the preamble portion in the corresponding slot performed by the detection / demodulation circuit, and the demodulation clock is selected in the preamble portion based on the result of the level measurement.

Furthermore, the level measurement is performed in a plurality of preceding frames, and the demodulation clock is selected such that the demodulation clock having the maximum average measurement level or the maximum predicted measurement level is selected.

Further, the level measurement is performed by limiting the target branch, and the demodulation clock is selected by selecting the demodulation clock having the maximum expected or measured level among these target branches.

Furthermore, a branch provided with an interfering wave detector, and the branch judged to have received the interfering wave by this interfering wave detector is
Removed from the target branch.

[0014]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. A description will be given of a combined diversity receiver which selects one of a plurality of demodulated clocks as a reference clock in the present embodiment. FIG. 1 is a configuration block diagram of a combined diversity receiver having a reference clock selection function. In FIG. 1, it is assumed that the receiver has N branches. As a new element that the device of this embodiment has, there is a reference clock selection unit 50 that selects a reference clock based on the level of each branch. A plurality of antennas 11, 12 to 1N for receiving other radio waves and a wave detector 21, 22 to 2 corresponding to each of the antennas for performing radio wave and RSSI measurement.
N and a reception diversity data processing unit 200 that processes reception data based on demodulation data that has been subjected to the combination diversity processing are the conventional apparatus. Is an element equivalent to.

Next, the operation of the apparatus having the above configuration will be described. Radio waves received by the plurality of antennas 11 and 12 to 1N are detected by the detectors 21 and 22 corresponding to the respective antennas.
Detection and RSSI measurement are performed at 2N. The phase information after detection, the demodulation clock, and the RSSI information are output from the detection unit, and the phase information 101, 201, N01 and the like are sent to the combining diversity processing unit 100 and the demodulation clocks 101, 201, N.
01 and the like and RSSI information 103, 203, N03 and the like are input to the reference clock selection unit 50. The reference clock selection unit 50 compares the amplitude of the RSSI information of each branch to detect the maximum level branch, and outputs the demodulation clock of the branch having the maximum level as the reference clock 510. In the combining diversity receiving unit 100, the demodulation information of each branch is weighted and combined with the reference clock 510 selected by the reference clock selecting unit 50 as a reference in proportion to the level of each branch, and demodulated data is obtained. Ask. The demodulation data 110 that has been subjected to the weighting synthesis processing is
The received data is input to the received data processing unit 200, where the received data is processed.

According to the above-mentioned combining diversity receiver,
Even if the reception electric field level fluctuates due to fading or the like and the reception electric field levels of some branches drop, or even if an interfering wave U wave is input to some branches, good reception sensitivity can be maintained, In addition, it is possible to process the received data in a stable manner while reducing the adverse effect of the phase shift of the demodulation clock of each branch.

In the above apparatus, more specific switching timing will be described. FIG. 2 is a diagram for explaining the timing of level measurement and the switching timing of the reference clock. The timing generation unit 300 shown in FIG. 1 gives a timing signal 310 to the reference clock selection unit 50 to switch the reference clock selection unit 50 to enable a burst operation of received data. That is, in order to prevent the phase of the reference clock from becoming discontinuous and causing an error in the received data, the clock switching within the slot is prohibited, and the RSSI information (level) in the receiving slot at the timing t1 one frame before. Based on the above, the clock of the branch having the highest level at the timing t1 is selected at the timing t2. This is P
This is effective in a system using a TDMA method such as HS. FIG. 2 shows a case where the timing is switched in the first slot (R1). Of course, it is possible to switch independently for each slot, and it is applicable to all slots. Since the clock switching in the receiving slot is prohibited in this way, the phase of the reference clock does not become discontinuous at the processing timing of the received data, and stable processing of the received data can be performed.

A case will be described in which another timing is used as the reference clock selection timing. That is, FIG.
In this case, the same reception slot one frame before is set as the measurement period for level measurement, and the reference clock is selected immediately before the reception timing of the next frame after the period of the one frame has elapsed. On the other hand, a case will be described below in which one receiving slot is switched to a period that does not affect the combining processing timing. FIG. 3 is a diagram for explaining the new level measurement timing and the reference clock switching timing. According to the timing shown in FIG. 2, a signal input every frame such as a call signal is effective, but a signal input only once in one burst such as a control signal does not correspond to RSSI information one frame before. It doesn't mean anything. Therefore, as shown in FIG. 3, the RSS of each branch is provided at the timing t3 at the beginning of the reception burst.
The I information is compared, and control is performed so that the reference clock is switched at the timing t4 immediately after that. In the control signal in wireless communication, the amount of preamble bits for bit synchronization in the demodulator is larger than that of the call signal, so R
Even if the SSI comparison and the clock switching are performed within the same preamble bit, it is possible to sufficiently follow the time. Moreover, since the clock switching in the preamble bit is before entering the data area, no error occurs in the demodulated data.

The measurement / switching timing shown in FIG. 2 and the measurement / switching timing shown in FIG. 3 may be externally selected. FIG. 4 is a block diagram showing the configuration of an apparatus for selecting the switching timing by the external setting. For example, if the setting signal from the setting unit 400 is H, the RS one frame before
The reference clock is selected based on the SI information, and if L, the reference clock is selected based on the RSSI information at the head position of the slot. As a result, stable reception processing suitable for the form of the received signal can be performed.

Embodiment 2. In the above embodiment, the reference clock is selected based on the measurement result of one frame before the setting period or at one point of the slot period to be selected. In the present embodiment, a case will be described in which a future level is predicted from results of a plurality of past measurement points and a reference clock is selected. FIG. 5 is a block diagram of a combined diversity receiver having a reference clock selection function in this embodiment. The apparatus having the configuration of FIG. 5 has a “reference clock with predictive function selection unit 60” that predicts from which branch the input from which branch will be the maximum RSSI at the next frame timing based on the level change of each branch. For example, based on the RSSI information of the frames of the three past levels, it is approximated by a quadratic curve to predict the next level, and the demodulation clock of the branch of the maximum level is used as the reference clock of the slot of the next frame timing. As a result, it is possible to further reduce the adverse effect of the phase shift of each branch.

FIG. 6 is a diagram for explaining the level measurement timing and the reference clock switching timing of the device having the configuration of FIG. 5, and shows the case of measurement in two consecutive frames of the PHS second slot. The increase / decrease of RSSI of each branch at the reception slot of 1 frame before the reception slot and the reception slot of 12 frames before the clock selection is calculated, and the RSSI of which branch is calculated at t13 of the next frame based on the calculated value. Expect maximum. Control is performed so that the reference clock is selected in the first reception slot tA of the frame including t13, for example, so that the demodulation clock of the branch having the maximum expected value is used as the reference clock. Naturally, by controlling each slot independently,
Switching is possible in all slots. Further, the accuracy of the predicted value can be further improved by increasing the past data in addition to the two slots. The optimum value may be selected according to the fading pitch of the system.

Embodiment 3. In the above embodiment, the case where the demodulated clocks from all the branches are collected and the reference clock is selected from the RSSI information level has been described. However, the branch affected by the interference wave may be excluded from the selection target of the reference clock, or the reference clock may be selected only from the specific branch in order to reduce the circuit scale. FIG. 7 shows a block diagram of a combined diversity receiver having a reference clock selection function in the present embodiment.
In the configuration of FIG. 7, an interfering wave (hereinafter referred to as U wave) detection unit 500 is provided to detect a branch that has received the U wave.
The detection result of the U wave is output to the reference clock selection unit 50d, and control is performed so that the clock of the branch that receives the U wave is excluded from the selection target of the reference clock. In this way, the adverse effect of the U wave can be prevented.

In order to prevent the clocks of all the branches from being selected as the reference clock by the U-wave countermeasure circuit 500, a U-wave branch number limiting unit 600 is provided, and the U-wave branch number limiting unit 600 allows the maximum U to pass. When the setting of the wave number is output and the set number of branches, for example, the setting is 2, U protects the detection circuit 500 so that three or more RSSI exclusion processes cannot be performed at the same time. It is possible to prevent the adverse effect of the U wave detection function.

A case will be described in which the number of branches to be selected for the reference clock is simply reduced in order to reduce the circuit scale. FIG. 8 is a diagram showing a configuration in which the number of branches to be selected is two. In this case, the number of branches may be properly selected according to the system.

[0025]

As described above, according to the present invention, since the reference clock is selected based on the RSSI information for each branch, even if the reception status of some branches deteriorates, Since the received data can be combined based on various clocks, there is an effect that reliable data reception can be performed.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a combining diversity receiver according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a timing of level measurement and a switching timing of a reference clock.

FIG. 3 is a diagram illustrating another switching timing according to the first embodiment.

FIG. 4 is a configuration block diagram of another combined diversity receiver according to the first embodiment.

FIG. 5 is a configuration block diagram of a combining diversity receiver in the second embodiment.

6 is a diagram for explaining the level measurement timing and the reference clock switching timing of the apparatus of FIG.

FIG. 7 is a configuration block diagram of a combining diversity receiver according to a third embodiment of the present invention.

FIG. 8 is a configuration block diagram of another combining diversity receiver according to the third embodiment.

FIG. 9 is a configuration block diagram of a combining diversity receiver which is a first conventional example.

FIG. 10 is a configuration block diagram of a combining diversity receiver which is a second conventional example.

[Explanation of symbols]

1 1 system branch, 2 2 system branch, N N system branch, 11 1 system antenna, 12 2 system antenna, 1N
N system antenna, 21 1 system detector, 22 2 system detector,
2N N-system detection unit, 50, 50b, 50d, 50e Reference clock selection unit, 60 Reference clock selection unit with predictive function, 100 Combined diversity reception unit, 200 Reception data processing unit, 300, 300b, 300c, 300
d, 300e timing generation unit, 400, 400c,
400d setting unit, 500 U wave detecting unit, 600 U wave branch number limiting unit.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04B ⁷ /02-7/12 H04L 1/02-1/06

Claims (6)

(57) [Claims] 1. In a configuration in which radio waves from a plurality of branches are respectively demodulated and then combined and received, each demodulation clock obtained by each detection / demodulation circuit is input and expected from the plurality of demodulation clocks. Alternatively, a combined diversity receiver is provided with a reference clock selection unit that selects a demodulated clock of the maximum level based on the measurement result and outputs it as a reference clock, and performs combined diversity processing using the reference clock. 2. The level measurement is performed during a set period, and the demodulation clock is selected before the first reception timing at which each detection / demodulation circuit starts reception after the lapse of the predetermined period. The combined diversity receiver according to claim 1. 3. The level measurement is performed in a preamble portion in a corresponding slot performed by a detection / demodulation circuit, and the demodulation clock is selected in the preamble portion based on the result of the level measurement. 1. The synthetic diversity receiver according to 1. 4. The level measurement is performed in a plurality of preceding frames, and the demodulation clock is selected such that the demodulation clock having the maximum average measurement level or the maximum predicted measurement level is selected. Item 1. The combined diversity receiver according to item 1. 5. The level measurement is performed by limiting the target branch, and the demodulation clock is selected by selecting the demodulation clock having the maximum expected or measured level among the target branches. 1. The synthetic diversity receiver according to 1. 6. The combined diversity reception according to claim 5, wherein an interference wave detector is provided, and the branch judged to have received the interference wave by the interference wave detector is excluded from the target branches. Machine.