JP3406141B2 - Driving method of plasma display panel and plasma display panel display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel (hereinafter referred to as PDP) and a plasma display panel display device, and in particular, electric charges remain depending on the state when the operation is stopped, and the electric charge is displayed. The present invention relates to a method of driving a PDP and a PDP display device that affect the display.

In recent years, in display devices, there has been a great demand for thinning, diversification of information to be displayed and installation conditions, large screen and high definition, and a display device satisfying these demands has been demanded. There is. LCDs, fluorescent display tubes, ELs, and PDPs are used as thin display devices.
There are various methods such as. Among such thin display devices, a display device using a PDP is particularly attracting attention because it has excellent characteristics such as flicker-free, easy screen enlargement, high brightness, and long life.

[0003]

2. Description of the Related Art PDPs are classified into a two-electrode type in which a selective discharge (address discharge) and a sustain discharge are performed with two electrodes, and a three-electrode type in which an address discharge is performed using a third electrode. In a color PDP that performs gradation display, ultraviolet rays generated by discharge excite a fluorescent substance formed in a discharge cell, but this fluorescent substance is weak against impact of ions, which are positive charges simultaneously generated by discharge. There are drawbacks. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened. In order to avoid this, the color PDP generally uses a three-electrode structure utilizing surface discharge. Furthermore, this 3
Also in the electrode type, there are cases where the third electrode is formed on the substrate on which the first and second electrodes for sustaining discharge are arranged, and there is a case where the third electrode is arranged on the other opposite substrate. Further, even when the above-mentioned three kinds of electrodes are formed on the same substrate, there are cases where the third electrode is arranged on the two electrodes for sustaining discharge, and where the third electrode is arranged below the two electrodes. is there. Furthermore,
There are cases where visible light emitted from a phosphor is viewed through the phosphor (transmission type), and there is a case where reflection from the phosphor is viewed (reflection type). In addition, the discharge cells have their spatial connections with adjacent cells cut off by barriers (ribs, barriers). This barrier is provided on all four sides so as to surround the discharge cell and is completely sealed, or is provided on only one and the other is disconnected by optimizing the gap (distance) between electrodes. There is.

The present invention can be applied to any of the above-described plasma display panels (Plasma Display Panels: PDPs). However, when the present invention is applied to a three-electrode type in which the problem of display failure due to residual charge is likely to occur. It is particularly effective in the panel in which the third electrode is formed on the opposite substrate other than the substrate of the electrode for sustaining discharge, and the barrier is vertical (that is, perpendicular to the first electrode and the second electrode). , Parallel to the third electrode), and a part of the sustain electrode is formed of a transparent electrode.

As the above-mentioned three-electrode / surface-discharge PDP, there is known a PDP whose schematic plan view is shown in FIG. 12 is a schematic sectional view (vertical direction) in one discharge cell of the panel of FIG. 11, and FIG. 13 is also a schematic sectional view in the horizontal direction. In the drawings shown below, the same functional parts are designated by the same reference numerals.

The panel is composed of two glass substrates 21 and 29. The first substrate 21 is provided with a first electrode (X electrode) 12 and a second electrode (Y electrode) 13 which are parallel sustain electrodes, and these electrodes are transparent electrodes 22a and 22b and a bus electrode 23a. 23b. Since the transparent electrode has a role of transmitting the reflected light from the phosphor, it is formed of ITO (transparent conductive film containing indium oxide as a main component) or the like. In addition, the bus electrode must be formed with low resistance in order to prevent voltage drop due to electrical resistance, such as Cr (chrome) or Cu (copper).
Formed by. Further, they are covered with a dielectric layer (glass) 24, and a MgO (magnesium oxide) film 25 is formed as a protective film on the discharge surface. In addition, the third electrode (address electrode) 13 is formed on the second substrate 29 facing the first glass substrate 21 in a form orthogonal to the sustain electrodes. Further, a barrier 14 is formed between the address electrodes, and a phosphor 27 having red, green, and blue emission characteristics is formed between the barriers so as to cover the address electrodes. Barrier 1
Two glass substrates are assembled so that the ridge 4 and the MgO surface 25 are in close contact with each other. Phosphor 27 and MgO surface 25
The space therebetween is the discharge space 26.

FIG. 14 is a schematic block diagram showing a peripheral circuit for driving the PDP shown in FIGS. 11 to 13. Each of the address electrodes 13-1, 13-2, ... Is connected to the address driver 105, and an address pulse at the time of address discharge is applied by the address driver. The Y electrodes Y1, Y2, ... Are connected to the Y scan driver 102. Y scan driver 1
02 is connected to the Y sustain pulse generation circuit 103, and the pulse at the time of address discharge is the Y scan driver 1
02, sustain pulses and the like are generated by the Y sustain pulse generation circuit 103, and are applied to the Y electrodes via the Y scan driver 102. The X electrodes 12 are commonly connected and taken out over all display lines of the panel. The X sustain pulse generation circuit 104 generates a write pulse, a sustain pulse, and the like. X sustain pulse generation circuit 1
Reference numeral 04a is connected to the write pulse generation circuit 104b, and the sustain discharge pulse is X sustain pulse generation circuit 1
The write pulse at the time of 04a is generated in the write pulse generation circuit 104b at the time of reset, and is applied to the X electrode via the X sustain pulse generation circuit 104a.
These driver circuits are controlled by the control unit 106, and the control circuits are controlled by synchronizing signals (VSYNC, HSYNC, CLOCK) and display data signals (DATA) input from the outside of the device.

FIG. 15 shows the PDP shown in FIGS. 11 to 13.
15 is a waveform diagram showing a conventional method of driving by the circuit shown in FIG. 14, showing one subfield period in a so-called conventional "address / sustain discharge period separated type / write address system". In this example, one subfield is divided into a reset period, an address period, and a sustain discharge period. In the reset period, first, all the Y electrodes are set to the 0V level, and at the same time, the full-area write pulse composed of the voltage Vs + Vw (about 330V) generated by the write pulse generation circuit 104b is applied to the X electrodes, and the display state up to that point is reached. Regardless of this, discharge is performed in all cells on all display lines. The address electrode potential at this time is about 100 V (Vaw). Next, the potentials of the X electrode and the address electrode become 0 V, the voltage of the wall charge itself exceeds the discharge start voltage in all cells, and the discharge is started. This discharge self-neutralizes and the discharge ends. This is so-called self-erase discharge. By this self-erasing discharge, the state of all cells in the panel becomes a uniform state without wall charges.
This reset period has the effect of putting all cells in the same state regardless of the lighting state of the previous subfield,
This is performed so that the next address (writing) discharge can be stably performed.

Next, in the address period, address discharge is performed line-sequentially in order to turn on / off the cells according to the display data. First, a scan pulse of −VY level (about −150 V) is applied to the Y electrode, and a voltage Va is applied to the address electrode corresponding to the cell that causes the sustain discharge, that is, the cell to be turned on among the address electrodes.
An address pulse of (about 50 V) is selectively applied to cause discharge between the address electrode and the Y electrode of the cell to be lit. Next, this is used as priming to generate a discharge between the X electrode (voltage Vx = 50 V) and the Y electrode, and the amount of wall charges capable of sustaining discharge is accumulated on the MgO surface of both electrodes.

Thereafter, the same operation is sequentially performed on the other display lines, and new display data is written on all the display lines. Then, in the sustain discharge period, the voltage is alternately applied to the Y electrode and the X electrode by Vs (about 180
V) sustain pulse is applied to sustain discharge,
Image display of one subfield is performed. At this time, in order to avoid discharge between the address electrode and the X electrode or the Y electrode, a voltage Vaw of about 100V is applied to the address electrode.

In the "address / sustain discharge separated type / write address system", the display brightness is determined by the length of the sustain discharge period, that is, the number of sustain pulses. In a PDP display device, one screen is displayed in one frame period, and one frame period is divided into a plurality of subframe periods having different lengths, and each bit of a bit data string representing grayscale data is associated. Grayscale display is performed by displaying in a sub-frame period having a weight. Specifically, as an example of multi-gradation display, a driving method in the case of performing 256-gradation display is shown in FIG. In this example, one frame is divided into eight subfields: SF0 to SF7. And
In these subfields SF0 to SF7, the reset period and the address period have the same length. The length of the sustain discharge period is 1: 2: 4: 8: 1.
The ratio is 6: 32: 64: 128. Therefore, by selecting the sub-frame to be turned on, it is possible to display the difference in brightness of 256 gradations from 0 to 255.

The above is an outline of a general PDP display device. In such a PDP display device, a microcomputer is generally used in order to perform the control operation as described above. When the power switch is turned on, the microcomputer performs the initialization operation as in the normal one, and first performs the self-erasing operation and the sustain discharge operation by applying the full-area write pulse for several cycles, and then the normal operation shown in FIG. The cycle of the reset operation, the address operation, and the sustain discharge operation was started.

Further, driving the PDP requires a large amount of high-voltage power as compared with a logic circuit unit such as a microcomputer, and the PDP power source and the logic circuit unit power source are separately provided.
In order to stabilize the power supply for PDP, a large withstand voltage capacitor or the like has been used. Therefore, when the power switch is turned off, the voltage of the power supply for the PDP drops more slowly than the power supply for the logic circuit section, and when the voltage of the power supply for the logic circuit section reaches a level at which the circuit does not operate, the control signal is output. The PDP stops outputting and the PDP stops in the state immediately before that. That is, the state in which the PDP is stopped was determined at the timing when the power supply was stopped, and the stopped state was not fixed.

[0014]

SUMMARY OF THE INVENTION As described above, the PDP
Is not determined, the state in each cell of the PDP, specifically, the state of wall charge differs depending on whether the state immediately before the stop is the reset period, the address period, or the sustain discharge period. It will be. Figure 17
It is a figure explaining distribution of wall charge by an operating state when a PDP device stops, and a problem by it.

FIG. 17 (1) shows a state in which the write pulse is applied during the reset period or when the write pulse is stopped immediately after the reset period ends. In this state, since the whole-area write pulse is applied, the address electrode, the X electrode,
No charges are accumulated on the Y electrode. 17 (2)
Indicates the state when the operation is stopped during the address period or immediately after the end of the address period. In this state, as shown in the figure, positive charges remain on the surface of the dielectric film facing the Y electrodes, and negative charges remain on the surface of the dielectric film facing the address electrodes and the Y electrodes. This residual charge continues to remain unless some erase processing is performed. Here, if the stopped state is for a short time, there is also gas ionized by discharge in the cell,
Since the state is similar to the state after the normal sustain discharge is completed, the discharge is performed by applying the full write pulse, and the normal operation is possible.

However, if the gas in the cell is left for a long time in the state of (2) in FIG. 17, the wall charges are recombined and neutralized, but the X electrode and the Y electrode are negative and positive, respectively. Wall charges will remain. As shown in (3) of FIG. 17, when the voltages due to the residual charges on the X electrode and the Y electrode in this state are set to −50 V and +50 V, a full write pulse of 350 V is applied to the X electrode and 0 is applied to the Y electrode.
When performing the reset operation of holding at V, the voltage actually applied between the X electrode and the Y electrode is 250 due to the residual charge.
It becomes V. In this case, the discharge for writing on the entire surface is not performed, which causes a problem that the erased state does not occur. In addition, since the discharge in the address period varies depending on the display data, the state of residual charge varies from cell to cell, which causes a problem of non-uniformity in which the erased state varies from cell to cell. When the data is not erased in the reset period as described above, the normal discharge is not performed even in the following address period and sustain discharge period, and the previous display data is erased until full write is performed again in the reset period after the sustain discharge period. Will be displayed. When the previous display data is displayed in this way, there arises a problem that a viewer of the PDP gives a very strange feeling.

Even if electric charges remain at the time of stop, it is possible to surely perform discharge for full erase by increasing the voltage of the full write pulse. For this purpose, the breakdown voltage of the cell structure and the drive circuit is increased. Therefore, there is a problem that the circuit scale becomes large. The present invention has been made to solve such a problem, and does not cause a problem that the previous display data is displayed at the time of activation.
The purpose is to realize a DP device.

[0018]

SUMMARY OF THE INVENTION The present invention is a method of driving a plasma display panel having a plurality of cells for selectively performing discharge light emission, the method including a reset step of bringing all the cells into a predetermined state, and a plurality of steps. A method of driving a plasma display panel, comprising: an addressing step of setting the cells in a state corresponding to display data; and a sustaining discharge step of causing a plurality of cells to emit light according to the set state. Is detected, and an initialization step of initializing the memory information of the display panel when it is detected that an operation stop factor has occurred.

Further, the plasma display panel display device of the present invention includes a plasma display panel having a plurality of cells for selectively performing discharge light emission, a reset means for bringing all the plurality of cells into a predetermined state, and a plurality of cells. In the plasma display panel display device, the plasma display panel operation stop factor is generated in the plasma display panel display device including the addressing means for setting the cell to the state corresponding to the display data and the sustaining discharge means for making the plurality of cells emit light according to the set state. It is characterized by further comprising: an operation stop factor detecting means for detecting that the operation stop factor is detected; and an initialization means for initializing the memory information of the plasma display panel when the occurrence of the operation stop factor is detected.

In the plasma display panel driving method and the display device of the present invention, when an operation stop factor such as a decrease in the voltage of the power source supplied to the device occurs,
Initialize the memory information on the display panel and then stop.
As a result, the state at the time of stop becomes a state in which discharge for complete erase can be surely performed when the reset operation is performed,
There is no problem such as the previous display data being displayed.

As described above, the stop of the power supply can be considered as the cause of the operation stop. Currently used PDP
In the device, in order to prevent the restart speed from decreasing, the display data that is not discharged is written in the power saving mode. However, even if the restart speed decreases in the future, the power supply to the PDP device will be stopped. By doing so, it is possible to further reduce power consumption. In such a case, the main body may output a stop signal to the PDP device, and the operation stop factor detecting means may detect this stop signal.

When the cause of the operation stop of the plasma display panel occurs, the setting to the state corresponding to the display data of a plurality of cells thereafter is prohibited or the first reset is performed from the time the cause of the operation stop occurs. After waiting until, the setting to the state corresponding to the display data of a plurality of cells is prohibited. If the cause of stopping the operation of the plasma display panel occurs during the address operation or during the sustain discharge, the initialization may be forcibly performed by applying an erase pulse for erasing the residual charges of a plurality of cells. If the cause of the operation stop is the address operation, it is desirable to perform the sustain discharge for at least one cycle and then perform the initialization.

The initialization operation is performed by setting the voltage of the erase pulse high and performing self-erase discharge, or by setting the voltage of the erase pulse to the same level as during the sustain discharge, and after stopping the application of the erase pulse,
In each cell, the charge on the wall surface and the charge of the gas in the cell are neutralized by narrow erase, or after the application of the erase pulse is stopped,
In each cell, the wall voltage is determined by the wide erasing which is determined by the applied voltage of the erase pulse.

[0024]

1 is a block diagram of a PDP according to an embodiment of the present invention.
It is a figure which shows the whole structure of a display apparatus. As is clear from comparison between FIG. 1 and FIG. 14, the difference from the conventional example is that a DC / DC converter 121 including a voltage detection circuit 120 is provided, and further, the control unit 106 detects a voltage. The difference is that the control performed by receiving the detection signal of the circuit 120 is added. Therefore, here, the points different from the conventional example will be mainly described, and the description of the same parts as the conventional example will be omitted or only a brief description will be given.

FIG. 2 is a diagram showing the structure of the control unit 106. As shown in FIG. 2, the display data control unit 107 includes a frame memory 108 and a data control circuit 131.
Panel drive control unit 109 (scan driver control unit 11
0) is composed of a scan control circuit 132 and a microcontroller (MCU) 133. The display data control unit 107 has a conventional configuration, and VSYNC and HSY supplied via the panel drive control unit 109.
The display data signal DATA supplied from the outside is temporarily stored in the frame memory 108 according to the synchronization signal such as NC and the clock signal CLOCK, and the address for each sub-frame supplied from the panel drive control unit 109 in the next frame cycle. The data stored in the frame memory 108 in synchronization with the period start signal is transferred to the address driver 10
Supply to 5. In addition, during the reset period and the sustain discharge period, all the address electrodes have a predetermined voltage Vaw (about 10
Fixed to 0V). The scan control circuit 132 has a configuration as shown in FIG. 3 and is controlled by the MCU 133.

In the circuit of FIG. 3, the waveform ROM 51 stores pulse waveforms to be applied to the X electrode and the Y electrode in each operation period, and by reading out the pulse waveform, a waveform signal in each operation period is generated. Waveform ROM5
1 only stores the minimum unit of the pulse waveform in each operation period, and when repeating the same waveform such as the address period or the sustain discharge period, the minimum unit of the corresponding waveform ROM 51 from the address counter 52 is stored. A necessary waveform signal is generated by outputting an address signal that loops. Specifically, Vc (Vsync
By inputting the (clear) signal, each block is reset and the address counter 52 starts operating.
In this state, the pulse waveform of the reset period is read first. Next, when the address showing the pulse waveform of the address period is reached, the shift pulse waveform of the address period is output from the waveform ROM 51. The operation of latching the first address at this time by the address latch 50 and loading the first address latched when the final address of the minimum unit is reached to the address counter 52 is repeated. This operation is such that the count value of the counter 57 coincides with the number of repetitions of the minimum unit pulse waveform in the stored address period output from the register 60, and the output signal from the comparator 58 causes the output of the address latch 50 to be output. It continues until the loading to the address counter 52 is prohibited,
A required number of shift pulses necessary for the address period are generated.

When this load signal is prohibited, the address counter 52 exits from the pulse generation cycle of the address period and enters the cycle generation pulse of the sustain discharge period. At this time, the counter 57 is reset by the signal from the address counter control ROM 57, and the register 60 is switched to output the number of times of repeating the pulse waveform of the minimum unit in the sustain discharge period. As a result, the same operation as in the address period is performed, and the pulse waveform in the sustain discharge period is repeated the required number of times.

When the required pulse waveform is repeated during the sustain discharge period, and the count value of the counter 57 also coincides with the number of times the minimum unit pulse waveform is repeated during the sustain discharge period, the address latch 50 is output by the output signal from the comparator 58. Is prohibited from being loaded into the address counter 52, and when the address value of the address counter 52 advances accordingly, the address counter control R
It is reset by the OM 57 and restarts from the address that produces the pulse in the first reset period. At this time, the counter 57 is reset by the signal from the address counter control ROM 57, and the register 6
0 is also reset to output the first value.

Although not shown, the microcontroller 133 can access the address counter 52, the address counter control ROM 57 and the counter 57, can detect the state thereof, and load a predetermined value for the counter. It is possible to It is also possible to access the register 60 and set its value to a desired state. When the interrupt signal from the voltage detection circuit 120 is generated, the microcontroller 133 immediately accesses these and confirms the state thereof, and detects which drive period is at that time.
Then, according to the detected state, a blocking process described later is performed. For example, a predetermined address is loaded into the address counter 52, and setting is made so that the pulse waveform for interruption processing stored separately in the waveform ROM 51 is read out, and when the readout of the interruption processing pulse is completed, the address counter control ROM 57 Set to stop the operation of the address counter 52.

FIG. 4 is a diagram showing the configuration of the voltage detection circuit of FIG. 1. The first and second voltage detectors 122 and 123 have the same configuration as shown in FIG. 5, except that the threshold levels are different. Have. The voltage detector of FIG. 5 is a comparator having hysteresis in the detected voltage, and the input Vin has a predetermined voltage Vs + Vh.
When the voltage becomes equal to or higher than is, the output / RESET becomes the "high (H)" level and the detection operation is started. Vin is V
When it is lower than s, / RESET becomes H.

The voltage detection circuit of FIG. 4 uses two voltage detectors of FIG. 5, and when the input voltage Vin becomes Vth1 or less, / RESET1 of the first voltage detector 122 is "H".
Changes from "L" to "L". In the second voltage detector 123, / RESET2 changes from "H" to "L" when the input voltage Vin becomes Vth2 or less. Where Vth1> Vth
There is a relationship of 2, and when the voltage drops, the detection signal is output at a different voltage level and input to the panel drive control unit 109.

In the panel drive control unit 109, / RESE
An interrupt is generated at the falling edge of T1, and it is detected which operation period it is in, and immediately shifts to the interruption processing. Then, when / RESET2 further changes from "H" to "L", all the operations are stopped. FIG. 6 is a diagram showing a sequence when the power is cut off in this embodiment. As described above, since the high-voltage power supply for driving the PDP is provided with a large-capacity capacitor, etc., when the voltage is cut off from the outside, such as when the AC power supply is stopped, the logic voltage starts to drop first, and The driving high-voltage power supply does not drop immediately. In this embodiment, the decrease of the logic voltage Vcc is constantly monitored by the voltage detection circuit, and when the logic voltage starts to decrease and decreases to Vth1 or less, the panel drive control unit 109.
/ RESET1 is input to, and an interrupt request is generated at the falling edge of the signal, and the interruption process is immediately performed. After that, when the logic voltage Vcc drops to Vth2 or less, / RESET2 is input and all the operations are stopped.

There are various types of blocking processing. The simplest way is to fix the display data to the data on the side where discharge does not occur immediately after / RESET1 is input so that each cell is set according to the display data input from the outside. As described above, the voltage of the high voltage power supply for driving the PDP drops more slowly than the voltage for logic, so the reset operation, the address operation, and the sustain discharge operation are sequentially performed, but the data to be written is the data that does not cause the discharge. The state in which there is no wall charge after the entire writing is once performed by the reset operation is maintained.

As another interruption processing, whatever the operation being performed when / RESET1 is input, the next reset operation is performed and the operation of the PDP device is stopped when the reset operation is completed. May be. The above interruption process causes no problem when the voltage drop of the PDP driving high-voltage power supply drops sufficiently slowly as compared with the logic power supply, but cannot be erased when the voltage drop is fast to some extent. If it is desired to erase as quickly as possible, the operation up to that point is immediately stopped as a cutoff process, and if wall charge is accumulated, an erase pulse is applied to all cells to eliminate wall charge. Make it uniform. FIG. 7 is a flowchart showing the processing in such a case.

The power supply detection circuit 120 detects a decrease in the logic voltage, and an interrupt is generated due to the detection of the power supply cutoff, that is, the microcontroller (MCU) 133.
Input to / RESET1 changes from "H" to "L". In response to this, the MCU 133 causes the shutoff processing routine 5
00 is started. In step 503, it is determined whether it is a reset period, and if it is a reset period, step 504
Then, the application of the entire write pulse being applied is performed to the end, and then the PDP device is stopped. If it is not the reset period, it is determined in step 505 whether it is the address period. If it is the address period, the process proceeds to step 506. In step 506, the address operation is stopped with the selective writing to the line being performed at that time lastly, and in step 507, only one sustain discharge cycle is performed.
This step is performed in order to fix the polarity of the residual charge and erase the accumulated charge more reliably. Then, it proceeds to step 508. If the determination in step 505 is not the address period, it is the sustain discharge period. In this case, the process directly proceeds to step 508. In step 508, erasing processing is performed on the entire surface writing. After the above operation, the operation of the PDP device is stopped.

FIGS. 8 to 10 are time charts of the above interruption processing, and FIG. 8 shows the processing when the time when / RESET1 changes from “H” to “L” is the reset period, and FIG. Shows the processing during the address period, as shown in FIG.
0 indicates processing during the sustain discharge period. / RESET
When the time when 1 changes from “H” to “L” is the reset period, the operation is stopped at the time when the application of the full-scale write pulse at that time is finished, as shown in FIG.

When the time when / RESET1 changes from "H" to "L" is the address period, Y at that time is set.
When the application of the shift pulse to the electrode, the application of the data signal to the address electrode, and the application of the predetermined voltage of the X electrode are completed, the application of the pulse thereafter is stopped. After that, in order to stabilize the residual charge, sustain discharge is performed for only one cycle, and then an erase pulse similar to the full write pulse is applied to stop the operation. In addition, in FIG.
Two erase pulses are applied to ensure that the opposite polarity wall charges are erased.

When the time when / RESET1 changes from "H" to "L" is the sustain discharge period, the application of the subsequent sustain discharge pulse is stopped as soon as the application of the sustain discharge pulse is finished, and then the erase pulse is applied. Apply. By performing the above blocking process, the state of all cells in the PDP panel 100 can be made uniform without wall charges.

In the above example, the self-erase discharge in which a high voltage pulse similar to the full-scale write pulse is applied as the erase pulse is performed, but the narrow width erase and the wide width erase described above are also possible.

[0040]

As described above, according to the present invention, the influence of the state at the time of the next start when the vehicle is stopped is eliminated, and the problem that the previous display data is displayed when the vehicle is started does not occur.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a PDP device according to an embodiment.

FIG. 2 is a diagram showing a configuration of a control unit in the embodiment.

FIG. 3 is a diagram illustrating details of a scan control circuit according to an embodiment.

FIG. 4 is a diagram showing a configuration of a voltage detection circuit.

5 is a detailed circuit diagram of a voltage detector used in the circuit of FIG.

FIG. 6 is a diagram showing a shutoff sequence of the embodiment.

FIG. 7 is a flowchart showing a blocking process for applying an erase pulse.

FIG. 8 is a time chart of a cutoff process when a voltage drop is detected during a reset period.

FIG. 9 is a time chart of interruption processing when a voltage drop is detected in the address period.

FIG. 10 is a time chart of interruption processing when a voltage drop is detected during a sustain discharge period.

FIG. 11 is a schematic plan view of a three-electrode / surface discharge / AC PDP.

FIG. 12 is a schematic cross-sectional view of a three-electrode / surface discharge / AC PDP.

FIG. 13 is a schematic sectional view of a three-electrode / surface discharge / AC PDP.

FIG. 14 is a block diagram of a drive circuit for a three-electrode / surface discharge / AC PDP.

FIG. 15 is a diagram showing a conventional drive waveform.

FIG. 16 is a time chart of an address / sustain discharge separated type address system in which gradation display is performed on a PDP.

FIG. 17 is a diagram illustrating the occurrence of reset failure depending on the state when the operation is completed.

[Explanation of symbols]

11 ... Y electrode (second electrode) 12 ... X electrode (first electrode) 13 ... Address electrode (third electrode) 100 ... Plasma display panel 102 ... Y scan driver 103 ... Y sustain pulse generation circuit 104a ... Sustain pulse generation circuit 104b ... Write pulse generation circuit 105 ... Address driver 106 ... Control unit 108 ... Frame memory 109 ... Panel drive control unit 110 ... Scan driver control unit 120 ... Voltage detection circuit

Front page continuation (72) Inventor Tetsuya Sakamoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP-A-58-102988 (JP, A) JP-A-48-91933 (JP, A) JP-A-8-76712 (JP, A) JP-A-8-234695 (JP, A) JP-A-7-44128 (JP, A) JP-A-62-192797 (JP, A) (58) Survey Areas (Int.Cl. ⁷ , DB name) G09G 3/288 G09G 3/20 670 G09G 3/28

Claims (14)

(57) [Claims] 1. A plasma display panel driving method having a plurality of cells for selectively discharge light emission, and a reset step of the plurality of cells to all predetermined state, displays the plurality of cell data In a driving method of a plasma display panel, which comprises an addressing step of setting a state corresponding to, and a sustain discharge step of causing the plurality of cells to emit light according to a set state, a cause of operation stop of the plasma display panel is generated. and operation stopping cause detection step of detecting that, when it is detected that the operation stop factor occurs, the
An initialization step of initializing memory information stored in the plasma display panel , wherein the initialization step includes the plasma display panel.
The first reset process from the point when the operation stop factor occurs
To display data of multiple cells after
Plasma characterized by prohibiting the setting to a charged state
Display panel driving method. Wherein selectively discharge light emission to a plasma display panel driving method having a plurality of cells for performing a reset procedure for the plurality of cells to all predetermined state, displays the plurality of cell data an address step of setting the state corresponding to, in the driving method of a plasma display panel and a sustain discharge step of emitting light according to the state set of the plurality of cells, the operation stop cause of the plasma display panel is generated and operation stop factor detection step of detecting that it has, when it is detected that the operation stop factor occurs, the
The memory information stored in the plasma display panel provided with an initialization step for initializing the operation stop cause of the plasma display panel is generated
If the time is the addressing step,
By applying an erase pulse to erase the residual charge
The plasma display characterized by performing the initialization process
The driving method of Rei panel. 3. A driving method of a plasma display panel according to claim 2, after the operation stop factor of the plasma display <br/> panel is detected that occurs,
A method of driving a plasma display panel, wherein the sustain discharge process is performed for at least one cycle, and then the initialization process is performed. 4. A plasma display panel driving method having a plurality of cells for selectively discharge light emission, and a reset step of the plurality of cells to all predetermined state, displays the plurality of cell data an address step of setting the state corresponding to, in the driving method of a plasma display panel and a sustain discharge step of emitting light according to the state set of the plurality of cells, the operation stop cause of the plasma display panel is generated and operation stop factor detection step of detecting that it has, when it is detected that the operation stop factor occurs, the
The memory information stored in the plasma display panel provided with an initialization step for initializing the operation stop cause of the plasma display panel is generated
If the time is the sustain discharge step, the plurality of cells
By applying an erase pulse to erase the residual charge
A method for driving a plasma display panel, which comprises performing the initialization step . 5. The method for driving a plasma display panel according to claim 2 , wherein the voltage of the erase pulse is set high so that the initialization step is self-erase discharge. Driving method for plasma display panel. 6. The method for driving a plasma display panel according to claim 2 , wherein the initialization step includes applying charge on a wall surface in each cell after the application of the erase pulse is stopped. A method of driving a plasma display panel, wherein a pulse width of the erase pulse is set so as to perform a narrow erase in which electric charge of gas in a cell is neutralized. 7. The method for driving a plasma display panel according to claim 2 , wherein in the initialization step, after the application of the erase pulse is stopped, wall charge is erased in each cell. A method of driving a plasma display panel, wherein a pulse width of the erase pulse is set so that the erase is a wide width determined by an applied voltage of the pulse. 8. A plasma display panel and, reset means to said plurality of cells for all predetermined state and a plurality of cells for selectively discharging emission
When the address means to set the state corresponding to the plurality of cells in the display data, in the plasma display panel display device and a sustain discharge hand stage to emit light in accordance with the state set of the plurality of cells, the initialization and operation stop factor detection means to detect that the operation stop factor of the plasma display panel is generated, when detecting that said operation stop factor occurs, the memory information stored in the plasma display panel a initialization means for, said initialization means, said plasma display panel
From the time when the operation stop factor occurs, the reset means
After performing the first reset operation,
Plasma display panel display device, which is prohibited from being set to a state corresponding to the display data of the cell . 9. The plasma display panel and, reset means to said plurality of cells for all predetermined state and a plurality of cells for selectively discharging emission
When the address means to set the state corresponding to the plurality of cells in the display data, in the plasma display panel display device and a sustain discharge hand stage to emit light in accordance with the state set of the plurality of cells, the initialization and operation stop factor detection means to detect that the operation stop factor of the plasma display panel is generated, when detecting that said operation stop factor occurs, the memory information stored in the plasma display panel a initialization means for, said a when the operation stop cause is detected to be generated
Corresponding display data to the cells by dressing means
When it is set to the closed state, the initialization means,
An erase pulse is applied to erase the residual charges of the plurality of cells.
A plasma display panel display device characterized by: 10. The plasma display panel display device according to claim 9 , wherein after the occurrence of the operation stop factor is detected, the sustain discharge unit performs a sustain discharge operation for at least one cycle, and then the sustain discharge operation is performed. A plasma display panel display device for initializing the plasma display panel by an initialization means. 11. A plasma display panel and, reset means to said plurality of cells for all predetermined state and a plurality of cells for selectively discharging emission
When the address means to set the state corresponding to the plurality of cells in the display data, in the plasma display panel display device and a sustain discharge hand stage to emit light in accordance with the state set of the plurality of cells, the initialization and operation stop factor detection means to detect that the operation stop factor of the plasma display panel is generated, when detecting that said operation stop factor occurs, the memory information stored in the plasma display panel a initialization means for, said Wei is when the operation stop cause is detected to be generated
Depending on the state in which the cells are set,
If it is emitting light, the initialization means
Apply an erase pulse to erase the residual charges of multiple cells.
A plasma display panel display device characterized by that. 12. The plasma display panel display device according to claim 9, wherein the initialization means applies an erase pulse having a pulse width set to be self-erase discharge. Plasma display panel display device. 13. The plasma display panel display device according to claim 9, wherein the resetting means charges the cells on the wall surface and the cells in each cell after the application of the erase pulse is stopped. A plasma display panel display device for applying an erase pulse having a short pulse width so that the erase is a narrow erase in which the charge of the internal gas is neutralized. 14. The plasma display panel display device according to claim 9, wherein the initialization unit applies the erase pulse to the wall voltage in each cell after the application of the erase pulse is stopped. A plasma display device for applying an erase pulse having a long pulse width so that the erase is a wide erase determined by the applied voltage of.