JP3403788B2 - Image input device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device for encoding an image signal generated by a solid-state image sensor.

[0002]

2. Description of the Related Art At present, devices such as videophones are being developed with the spread of the integrated services digital network (ISDN). In order to maintain compatibility between these devices, the signal processing format is standardized. The format was decided by the International Telegraph and Telephone Consultative Committee (CCITT),
As one of them, H.M. There is a format of 261. In this format, the CIF format is defined as an intermediate format of the pixels forming the screen. The pixel configuration of the CIF format is 288 pixels vertically and 325 pixels horizontally. Therefore, the format H.264. The H.261-compliant videophone is once converted to this intermediate format regardless of the input pixel arrangement. Next, the configuration of the videophone conforming to the above format will be described. The composition of the videophone is, for example, Hitachi Review (Hitachi Review) Vol.40 (1991) N.
It is shown in o.3. A concrete block diagram is shown in FIG. 4 of the above-mentioned document, but when the input is an NTSC signal which is a current television signal, the operation is such that a color signal and a luminance signal are separated and AD conversion is performed on the other hand. Next, CIF- which generates a CIF signal
Converted to CIF format by LSI, CODE
It is encoded by a CODER-LSI that generates an R signal.
At this time, generally three frame memories are used.
The frame memories will be referred to as first, second and third frame memories. Of these, the first and second frame memories are for storing the image after encoding, and the remaining third frame memory is for storing the CIF-converted image of the current frame. . The image after encoding is necessary for comparing the images of the previous frame and the current frame at the time of encoding and encoding only the difference. In addition, the frame memory for storing the image of the current frame needs to absorb the encoding operation and the operation of the AD converter for outputting the image signal, which are asynchronous. The specific operation will be described below. Here, it is assumed that the image obtained by encoding the immediately preceding frame is stored in the first frame memory. When a certain block is read from the third frame memory into the CODER-LSI, the CODER-LSI performs a motion search for peripheral pixels. Then, when the data in the block best match, the operation of encoding the difference between the two blocks is performed. Then, the encoded data is inversely transformed, and this time the inversely transformed block data is stored in the second frame memory. Repeat this,
In the next frame, the second frame memory is now used as the image after encoding the immediately preceding frame.
As described above, the reason why the second and first frame memories are switched and used for each frame is that since the information of the already encoded portion is also used at the time of motion search, the data of that portion cannot be rewritten. Is.

Next, in the above-mentioned document, NTSC is used as an input.
Although signals are used, FIG. 16 shows a case where the signals are replaced with a solid-state image sensor having a CIF format pixel number. In FIG. 16, 102 is a solid-state image sensor, and 118 is A.
D conversion means, 106 is an encoding means, and 109 is a drive circuit as drive signal generation means. Further, what corresponds to the three frame memories used in the above document is the first image storage means 108, the second image storage means 110, and the third image storage means 111. In the above configuration, since the solid-state image sensor 102 is arranged in the CIF format, a C signal is provided between the AD conversion unit 118 and the encoding unit 106.
There is no conversion means to IF format.

Next, the internal structure and operation of the solid-state image sensor 102 will be described. The solid-state image sensor 102
Is, for example, Technical Report Vol. 15, N
o. 16, a photoelectric conversion means 110 corresponding to a photodiode, a charge transfer means 112 corresponding to a vertical CCD register and a horizontal CCD register, and a charge detection means 116 corresponding to a charge detection circuit are roughly configured. Further, the drive signal and the operation of the above three means will be described with reference to FIG. FIG. 17 is a block diagram of the above document in which the supplied drive signal is added. In the figure, 120 is a photodiode, 1
Reference numeral 12a is a vertical CCD register, 112b is a horizontal CCD register, and 116 is a charge detecting means. Further, the vertical CCD register drive signal 128 and the horizontal CCD register drive signal 13 are output from the drive circuit 109 which is the drive signal generating means.
0, charge reset signal 132, output amplifier drive signal 13
4 is output and input to the solid-state image sensor 102. In the above structure, the signal charge generated by photoelectrically converting the incident light on the photodiode 120 is the vertical CC.
When a read signal is output to the D register drive signal 128, it is read to the vertical CCD register 112a. The signal charge is the vertical CCD register drive signal 1
It is transferred by the vertical CCD register 112 a driven by the horizontal CCD register 112 and the horizontal CCD register 112 b driven by the horizontal CCD register drive signal 130, and input to the charge detection means 116. As a result, the signal charge is converted into an analog voltage and becomes the output of the solid-state image sensor 102. The timing at which the output signal of the solid-state image sensor 102 is output will be described with reference to FIG. First, the photodiode 1
20 from the read signal for reading from the 20 to the vertical CCD register 112a, the charge reset signal 13
2 resets the charge in the photodiode. After that, charge is accumulated in the photodiode 120 for ts time,
It is read from the photodiode 120 to the vertical CCD register 112a by a read signal. And FIG.
As shown in, the charges in the vertical CCD register 112a are transferred to the horizontal CCD register 112b one by one in the horizontal blanking period, and the signal charges for one line are read out using the horizontal CCD register 112b in the video signal period. The solid-state image sensor 102 periodically outputs a signal at the above timing. On the other hand, the encoding unit 106 operates asynchronously with the solid-state image sensor 102. For example, if the processing of the previous frame in the encoding unit 106 is completed at time t1 in FIG. 18, the (n-1) th frame image is obtained. It is read into the first image storage means 108 and encoded. Also, at time t
If the processing of the previous frame is completed in 2, the nth frame image is read into the first image storage means 108 and encoded.

[0005]

In the method according to the prior art, the solid-state image sensor 102 and the encoding means 106 operate asynchronously. Further, the output signal of the solid-state image sensor 102 is such that when a signal of one horizontal line is output, the next one horizontal line is output. Pixel, vertical 8
It requires an output for each block of pixels. Therefore, in the conventional method, the output signal of the solid-state image sensor 102 is once stored in the third image storage means 111, and the encoding means 106 performs encoding using the data. As a result, the amount of hardware has been increased.

[0006]

In order to solve the above-mentioned problems, an image input device of the present invention is a solid-state image sensor for converting incident light into an image signal, and the image signal transferred from the solid-state image sensor. A rearrangement means for rearranging the output order of the data, and an encoding means for encoding the rearranged image signal, and a predetermined image in the encoding means.
According to the progress of signal encoding, the encoding means is
Generation of a drive signal to the drive signal generation means of the image sensor
It is characterized by having means for requesting . Further, a storage means for reducing the waiting time of the encoding means is provided between the rearranging means and the encoding means. Further, the solid-state image sensor for converting incident light into an image signal, and the encoding means for encoding the image signal transferred from the solid-state image sensor, the solid-state image sensor for the encoding incorporates a means rearranging the output order of the data of the image signal, said code
Depending on the progress of the encoding of a predetermined image signal in the encoding means
The encoding means is a means for generating a drive signal for the solid-state image sensor.
It is characterized in that it has means for requesting the generation of a drive signal to the stage . Further, the image input device is a videophone.

[0007]

In the above construction, when the coding process of a certain block is completed, the coding device requests the drive signal generating device of the solid-state image pickup device for the data of the next block. Thereby, the drive signal generating means outputs the data from the rearranging means when the data necessary for the rearranging means exists. If the rearrangement means does not have the necessary data, the drive signal generating means drives the vertical CCD register and the horizontal CCD register of the solid-state image pickup device,
Input the data into the sorting means. For example, when data of 8 × 8 blocks is required, data for 8 lines is input to the rearrangement means. That is, a plurality of 8 × 8 blocks of data are input to the rearranging means. Then, the data necessary for the encoding means is output from the data input to the rearrangement means. The output analog signal is AD-converted by the AD converter, and the output data of the AD converter is input to the encoder. Therefore, there is no need for the first image storage means for storing the image of the current frame. As a result, the hardware amount of the entire system can be reduced.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of an image input apparatus according to the present invention, FIG. 2 is a diagram explaining the operation of the above embodiment, FIG. 3 is a diagram showing a timing chart of the above embodiment, and FIG. FIG. 7 is a diagram showing a state in which charges are transferred in one stage in the vertical CCD register, FIG. 5 is a diagram showing a state in which a digital signal is stored in the shift register, FIG. 6 is a diagram showing a state in which data is stored in the shift register, FIG. Is a diagram showing a timing chart of driving signal generation for outputting the signal of the next block, FIG. 8 is a diagram showing a timing chart of driving the vertical and horizontal CCD registers by the driving signal generating means, and FIG. 2 is a diagram showing an embodiment, FIG. 10 is a diagram for explaining the operation of the above embodiment, FIG. 11 is a diagram showing a timing chart when the waiting time of the encoding means is reduced,
FIG. 12 is a configuration diagram showing a case of a color image pickup device, FIG. 13 is a diagram showing a third embodiment of the present invention, and FIG. 14 is a plurality of horizontal CCs.
FIG. 15 is a diagram for explaining the operation of the configuration provided with the D register, and FIG. 15 is a diagram showing the configuration provided with the charge switching means.

First Embodiment A first embodiment of the image input apparatus according to the present invention will be described with reference to FIGS. 1 and 2. In this embodiment, the encoding unit 106 performs encoding in a block of 2 pixels in the vertical direction and 2 pixels in the horizontal direction, and the image sensor 102 has a pixel format determined by the image transmission method. For example, H.264. In the case of the CIF format defined by H.261, there are 288 vertical pixels and 325 horizontal pixels. FIG. 1 shows the configuration of the entire system, and FIG. 2 shows the solid-state image sensor 102, rearrangement means 14, and drive signal generation means 109. The present embodiment is characterized in that the rearranging means 14 is provided and the drive signal generating means 109 is controlled by the encoding means 106. Here, 110 is a photoelectric conversion unit, 112 is a charge transfer unit, 116 is a charge detection unit, 118 is an AD conversion unit, 14 is a rearrangement unit,
106 is an encoding means, 6 and 7 are image storage means, 10
Reference numeral 9 is a drive signal generating means. Next, the operation of the entire block will be described. The signal converted into charges in the photoelectric conversion unit 110 is transferred to the charge detection unit 116 by the charge transfer unit 112. At this time, the drive signal generating means 109 is controlled by the encoding means 106, and when the encoding means 106 requests data, it generates a drive signal for transferring the necessary data as the next block. The charge transfer means 112 transfers only the necessary signal charges to the charge detection means 116 by the drive signal. The signal converted into the voltage by the charge detection means 116 is AD
It is converted into a digital signal by the conversion means 118. Then, the rearrangement means 14 inputs the block output to the encoding means 106, which is encoded by the encoding means 106 and transmitted. At this time, the image of the previous frame is stored in the first image storage means 6, and the image signal and the signal output by the rearrangement means 14 are compared for each block and encoded. The encoding means 106 inversely transforms the encoded data and writes the inversely transformed data in the second image storage means 7, as described in the conventional technique. The data in the second image storage means 7 becomes reference data when the next frame is encoded. When the encoding means 106 completes the encoding of the data in the rearrangement means 14, it requests the drive signal generation means 109 to generate a drive signal in order to input new data to the rearrangement means 14.

Next, the driving method of the solid-state image pickup device 102 and the specific configuration of the rearrangement means 14 will be described with reference to FIGS.
Will be described in detail. Here, 120 is a photodiode, 112a is a vertical CCD register, 112b is a horizontal CCD register, 128 is a vertical CCD register drive signal, 130 is a horizontal CCD register drive signal, 132 is a charge reset signal, 136 is an encoding means operation end signal, 1
38 is a block output request signal, 140 is input switching means, 142 and 144 are n-bit shift registers, 14
Reference numeral 6 indicates a data selector. The coordinates of each photodiode are shown in the photodiode 120 shown in FIG. 2, and D (1,1) shown in the vertical CCD register 112a is the signal charge in the photodiode at the coordinates (1,1). It is shown that. As shown in FIG. 3, when the encoding unit 106 finishes encoding the previous frame, the encoding unit operation end signal 136 is sent to the drive signal generation unit 109. Thereby, the drive signal generating means 109
Produces a charge reset signal 132, which causes the photodiode 12
Reset the charge in 0. Then, the set time t
After the lapse of 1, the drive signal generating means 109 generates a read signal, and the signal charges are simultaneously read to the vertical CCD register 112a. The state shown in FIG. 2 is the above state. Next, the drive circuit 109, which is a drive signal generation means, generates a vertical CCD register drive signal 128, and transfers the electric charges by one stage in the vertical CCD register 112a. This state is shown in FIG. 4. In the above state, the horizontal C
The signal charges of the nth row have been transferred to the CD register 112b. Then, by the horizontal CCD register drive signal,
The charges are transferred to the charge detection means 116 and converted into a voltage. The above voltage is converted into a digital signal by the AD conversion means 118. At this time, the input switching means 140 is set to A, and the digital signal is stored in the shift register 142. This state is shown in FIG. Then, charge the vertical CC
One stage is transferred in the D register 112a, and the horizontal CCD register 112b transfers the charges to the charge detection means 116 and converts them into a voltage. Then, it is converted into a digital signal in the AD conversion means 118, and this time the input switching means 140 is set to B.
And the switching data is stored in the shift register 144. This state is shown in FIG. And the data selector 1
The input of 46 is first set to A and two data are output, and then the data is switched to B and two data are output. This enables 2 × 2 block output. The encoding means 106 encodes the block using the above data. Upon completion, the encoding means 106 outputs a block output request signal. As the block output request signal, a signal used in the conventional technique for the encoding means to request the first image storage means to output the next block image may be used. Based on this signal, the drive signal generation means 109 generates a drive signal for outputting the signal of the next block. The timing chart is shown in FIG. This timing chart FIG. 7 is a continuation of the timing chart shown in FIG. The drive signal generation means 109 controls the shift resisters 142 and 144 and the data selector 146 in the same manner as described above, and D (n, 3), D (n, 4), D (n-1, 3),
2 × 2 block output represented by D (n-1, 4) is performed. By repeating this, as shown in FIG. 8, the last block signal D (n, n−) in the shift registers 142 and 144 is obtained.
1), D (n, n), D (n-1, n-1), D (n-
1, n) is output, the drive signal generating means 109 causes the vertical CC in the solid-state image sensor 102 as described above.
It drives the D register and the horizontal CCD register. As a result, the next two rows of data are input to the shift registers 142 and 144. This operation is repeatedly performed by the encoding means 106.
Upon completion of encoding the signals of all pixels of the solid-state image sensor 102, the encoding means 106 outputs an encoding means operation end signal and repeats the operation shown at the timing of FIG. As described above, the encoding means 106 controls the drive signal generating means 109 of the solid-state image pickup device 102 to provide the rearrangement means 14, so that the solid-state image pickup element 102 is provided.
The vertical CCD register 112a can be used like a frame memory, and the third image storage means, which is used in the prior art to absorb the asynchronism between the solid-state image sensor 102 and the encoding means 106, can be used. Therefore, the hardware amount of the entire system can be reduced.
In this embodiment, the case of outputting in 2 × 2 blocks has been described, but the number of vertical and horizontal pixels forming a block can be changed by changing the driving method and rearranging means.

In this embodiment, the case where only the luminance signal is encoded has been described. However, it is also applicable to the case of an image pickup device in which a color filter is laminated on a photodiode and a color signal is obtained by one device. In that case,
The color signal generating means 20 may be provided as shown in FIG. As a result, the vertical CCD register 112a can be used like a frame memory even in a color image sensor, and the hardware amount of the entire system can be reduced.

In this embodiment, the case where the shift register 142 is used as the rearrangement means has been described. However, this may use random access memory (RAM). When the RAM is used, for example, the output of the solid-state image sensor 102 is written in the RAM in the order of addresses. When reading, necessary data may be accessed and block output may be performed. With the above configuration, the configuration of the block to be read can be arbitrarily changed by changing the access method for reading. In addition, a large-capacity RAM is often used in a videophone system that constitutes an encoding means. Therefore, large capacity RAM
If there is a vacant portion, the rearranging means may be configured using that portion. As a result, the present invention can be configured without adding the hardware of the rearrangement means.

Second Embodiment A second embodiment of the image input apparatus according to the present invention will be described with reference to FIG. In the present embodiment, before the encoding means finishes the processing of the frame, it outputs a signal to the drive signal generation means in advance, and the generated drive signal causes the solid-state imaging device 102 to start accumulating the signal charge of the next frame. It is characterized by this. In FIG. 9, 21 is a temporary storage means. Originally, it is desired to output the next frame request signal at a fixed time before the processing of the current frame ends, but the time required for encoding differs depending on the image, which is difficult. In view of this, in the present embodiment, when starting the block processing a certain number n before the last block of the frame, the next frame request signal is output. The above n is, for example, ta is an average of the time required to encode one block, ts is a time at which a signal is desired to be stored in the photodiode, and a time until the stored signal is read and the transfer to the rearrangement means is completed. Is td, the minimum integer that satisfies n> (ts + td) / ta.

Next, the operation of this embodiment will be described with reference to FIG. In the timing chart shown in FIG. 10, n =
Time to encode data for all all stored in the temporary storage 21 at 4 assumes a case has long than the time until the transfer means rearranging accumulates the charge of the next frame to the photodiode . In this case, the temporary storage means 21 outputs B (n-1) at the time t1 when the block of the first part of the next frame is transferred to the rearrangement means.
That is, if the capacity of the temporary storage means 21 is set to a capacity capable of storing image data of 4 blocks, there are 2 rewritable areas, so that data is sequentially input from that portion to B (1). After that, the temporary storage means 2
As soon as there is a vacancy in 1, input the data by rearranging means. In the case of FIG. 10, when the block B (2) is sent from the temporary storage means to the encoding means 106, the rearrangement means sends the block signal B (5) to the temporary storage means. By the above operation, the temporary storage means 21 can always output the data to the encoding means 106, and the encoding means 1
The waiting time of 06 can be eliminated. Next, using the timing chart shown in FIG. 11, the time taken to encode all the data in the temporary storage means 21 is more than the time taken until the charges of the next frame are accumulated in the photodiodes and transferred to the rearrangement means. We describe a case also not short. in this case,
At the time t1 when the blocks in the first part of the next frame are transferred to the rearrangement means, the temporary storage means 21 outputs all the data, and the encoding means 106 is in a waiting state. Therefore, the input to the temporary storage means 21 is immediately started, and the temporary storage means 21 starts to output from B (1). In this case, B is the signal of the first block of the next frame after the encoding of the last block data B (n) in the temporary storage means 21 of the previous frame is completed.
A waiting time of tw occurs before the output of (1) is started. However, this time is compared with the sum of the charge storage time ts of the photodiode and the time td required to complete the transfer to the rearrangement means by reading out the stored signals, and the data of four blocks is encoded by the encoding means 106. Is reduced by the time it takes to encode. That is, the waiting time of the encoding means 106 is shortened, and the frame rate for encoding the entire system can be increased. Next, let us consider concrete numerical values. The current CCITT Recommendation H.264. Two
Think on a 61-compliant videophone. For example, vertical 144
QCIF in which the number of pixels, 176 horizontal pixels, is 1/4
Then, the total number of pixels is divided into 396 blocks by a block of 8 × 8 pixels and encoded, and the frame rate is about 5 frames / sec. That is, an average hand of 0.5 ms is required for one block. Here, when the storage time of the image pickup device is 20 ms, which is often used to obtain a flicker-free image, the storage time needs to be about 40 blocks. This is about 1/10 of the capacity of one frame. This embodiment can be constructed with such a small capacity. In the above calculation, the time for transferring the signals to the rearrangement means for the storage time of 20 ms is as short as several hundreds of μs, so it is ignored.

In the description of this embodiment, n is n> (ts + t
Although the case has been described where the minimum integer that satisfies d) / ta is defined, the above n may take any value depending on the purpose. When n is increased, the memory capacity is increased, but the waiting time of the encoding means 106 is reduced, which is effective in increasing the frame rate. On the other hand, if n is made small, the memory capacity can be made small, but the frame rate becomes slow. In this case, the amount of hardware becomes small, which is effective for cost reduction.

Third Embodiment In the first embodiment, a shift register is used as the rearranging means in order to perform block output. The third embodiment is made possible by adding the horizontal CCD register to the function of the above shift register, and its configuration is shown in FIG. The present embodiment is characterized in that a horizontal CCD register 112c, a charge detector 117, and an output switching means 30 are added as compared with the solid-state image pickup device 102 in the first embodiment. Similar to the first embodiment, the signal charge generated by the photodiode 120 is transferred to the vertical CCD register 11
The data is read out to 2a and simultaneously transferred to the horizontal CCD register 112b for each line. The first line is a horizontal CCD
FIG. 13 shows the case of transfer to the register 112b. Next, from the horizontal CCD register 112b to the horizontal CC
The signal is transferred to the D register 112c, and the signal of the next one line is transferred from the vertical CCD register 112a to the horizontal CCD register 112b. This state is shown in FIG.
Then, the signals are input to the charge detectors 116 and 117 by the horizontal CCD registers 112b and 112c. As a result, a voltage proportional to the input signal charge amount is output to the outputs of the charge detectors 116 and 117. It is switched by the output switching means 30, and the AD conversion means 1
Enter 18 This allows 2 × 2 block output with a simple configuration. As a result, the block output operation can be performed with a small amount of hardware.

In the above description, the horizontal CCD register 112
The case where the charge detector is provided for each of b and 112c has been described. However, as shown in FIG. 15, charge switching means 117 'may be provided between the horizontal CCD registers 112b and 112c and the charge detector 116. The charges transferred by the two horizontal CCD registers in such a configuration are switched and input to the charge detector 116. As a result, a single charge detector can be used.

[0018]

As described above, in the image input apparatus according to the present invention, the drive signal of the solid-state image pickup device for converting the incident light into the image signal is controlled by the encoding means for encoding the image signal, and the solid-state image pickup is performed. By changing the output order of the data transferred from the device by the rearrangement means, the vertical CCD register of the solid-state image pickup device can be used like a frame memory, and a memory for storing the current frame is required. Therefore, the hardware amount of the entire system can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of an image input device according to the present invention.

FIG. 2 is a diagram for explaining the operation of the above embodiment.

FIG. 3 is a diagram showing a timing chart of the embodiment.

FIG. 4 is a diagram showing a state in which charges are transferred in one stage in a vertical CCD register by a drive signal.

FIG. 5 is a diagram showing a state in which a digital signal is stored in a shift register.

FIG. 6 is a diagram showing a state in which data is stored in a shift register.

FIG. 7 is a diagram showing a timing chart of drive signal generation for outputting the signal of the next block.

FIG. 8 is a diagram showing a timing chart in which the drive signal generating means drives vertical and horizontal CCD registers.

FIG. 9 is a diagram showing a second embodiment of the present invention.

FIG. 10 is a diagram for explaining the operation of the above embodiment.

FIG. 11 is a diagram showing a timing chart when the waiting time of the encoding means is reduced.

FIG. 12 is a configuration diagram showing a case of a color image sensor.

FIG. 13 is a diagram showing a third embodiment of the present invention.

FIG. 14 is a diagram for explaining the operation of the configuration provided with a plurality of horizontal CCD registers.

FIG. 15 is a diagram showing a configuration provided with charge switching means.

FIG. 16 is a diagram showing a configuration of a conventional image input device.

FIG. 17 is a diagram for explaining the operation of the above conventional technique.

FIG. 18 is a diagram showing a timing chart for a solid-state image sensor output signal in the above-mentioned conventional technique.

FIG. 19 is a diagram showing a timing chart of signal charge reading by a vertical CCD register and a horizontal CCD.

[Explanation of symbols]

14 rearrangement means 21 temporary storage means 102 solid-state image sensor 106 encoding means 109, 128 drive signal generating means 112a Vertical CCD register 112b, 112c Horizontal CCD register 120 photodiodes 142 and 144 shift registers

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiromi Watanabe 1-280, Higashikoigokubo, Kokubunji, Tokyo 1-280, Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A 1-218182 (JP, A) (58) Survey Areas (Int.Cl. ⁷ , DB name) H04N 5/335

Claims (4)

(57) [Claims] 1. A solid-state image sensor for converting incident light into an image signal, rearrangement means for rearranging an output order of data of the image signal transferred from the solid-state image sensor, and the image after the rearrangement. A coding means for coding the signal, and the coding progress of the predetermined image signal in the coding means.
Depending on the progress, the encoding means may drive the solid-state image sensor.
Signal generation means to request the generation of a drive signal.
An image input device characterized by being . 2. The image input according to claim 1, further comprising storage means provided between the rearranging means and the encoding means for reducing a waiting time of the encoding means. apparatus. 3. A solid-state image sensor for converting incident light into an image signal, and a coding means for coding the image signal transferred from the solid-state image sensor, wherein the solid-state image sensor has the above-mentioned code. It incorporates a means rearranging the output order of the data of the image signal for, in the coded unit
According to the progress of encoding a predetermined image signal, the encoding means
Drive signal to the drive signal generating means of the solid-state image sensor.
An image input device comprising means for requesting the generation of a signal . 4. The image input device according to claim 1, 2 or 3, wherein the image input device is a videophone.