JP3402451B2 - Frame synchronization correction method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization correction device, and more particularly to a frame synchronization correction device in a communication device such as a mobile phone.

[0002]

2. Description of the Related Art Regarding a conventional frame synchronization correction device,
The operation will be described with reference to the block diagram of FIG. 11 and the timing chart of FIG. In a conventional frame synchronization correction device, a known pattern of a received signal (101) such as a control signal that can be received at a fixed frame period (usually called a sync word or a unique word, hereinafter referred to as UW pattern: unique word pattern). Is detected and the value of the reference timer (104) operated by the reference clock (102) is latched by the UW pattern detection pulse (105). UW by this value (108)
Calculate the time when the pattern was received. Then, the time (t
The difference between the value at -1) and the value at time (t) is calculated, and a histogram of the UW pattern reception time is calculated (109) for each UW pattern detection, and the reference frame signal of the transmitter and the reference frame signal of the receiver are calculated. Output the accumulated timing difference of (11
0) Yes.

By setting a timing difference allowable value (threshold value) (113) with respect to the value of this histogram, when the timing correction value detecting section (111) is below a negative timing allowable value (reception When the reference frame signal of the device is shifted rearward of the reference frame signal of the transmitting device), the reference frame signal of the receiving device is corrected forward (112), and when the positive timing allowable value is exceeded (the receiving device If the reference frame signal is shifted forward of the reference frame signal of the transmitter), the reference frame signal of the receiver is corrected backward (112). Actually, when correcting forward, the initial value of the reference timer is +1
However, when correcting backward, the initial value of the reference timer is decremented by -1, the count value of the reference timer (frame length of the receiving device) is increased or decreased, and the frame signal (11
5) is synchronized with the frame signal of the transmitter.

[0004]

However, in such a conventional frame synchronization correcting apparatus, the histogram showing the timing difference is determined by the timing difference allowable value (threshold value).
Since the correction processing is performed at a time when the value exceeds the above, the timing jitter of the frame signal of the receiving device with respect to the frame signal of the transmitting device becomes very large. That is, the followability of the frame signal of the receiving device to the frame signal of the transmitting device decreases.

Further, by constantly receiving the UW pattern, the timing difference between the frame signal of the transmitting device and the frame signal of the receiving device is detected and the frame signal of the receiving device is corrected, so that the line is disconnected. When the UW pattern cannot be received for a long time, it is difficult to maintain the synchronization between the frame signal of the transmitter and the frame signal of the receiver.

The present invention solves the above problems, enhances the followability of the frame signal of the receiving device to the frame signal of the transmitting device, and maintains the synchronization between the frame signal of the transmitting device and the frame signal of the receiving device. To aim.

[0007]

In order to solve the above-mentioned problems, according to the present invention, a known pattern detecting section for detecting a known transmission pattern from a received signal, a reference timer operating with a reference clock, and a known A latch unit that holds the value of the reference timer by the detection pulse from the pattern detection unit, a flip-flop that holds the timer value latched at time (t-1), and a time (t-1) and a time (t). A timing difference calculation unit including an adder that calculates a difference between fixed frames and a timing difference per fixed frame number; a correction value calculation unit that calculates a correction value per frame from the calculated timing difference; A frame signal correction unit that corrects the frame signal by setting and holds the synchronization is provided.

With this configuration, it is possible to calculate the correction value per frame and correct the frame synchronization between transmission and reception.

Further, a known pattern detection section for detecting a known transmission pattern from a received signal, a reference timer operated by a reference clock, and a latch section for holding the value of the reference timer by a detection pulse from the known pattern detection section. And a flip-flop that holds the latched timer value at time (t-1) and the difference between time (t-1) and time (t) is calculated to calculate the fixed frame number or the timing difference per set frame. Output from the timing difference calculation unit by the timing difference calculation unit equipped with an adder, the memory unit that temporarily stores the timing difference per fixed number of frames or the set number of frames, and the known pattern detection presence / absence signal from the known pattern detection unit. Selector unit for selecting either the data of the stored timing difference or the timing difference temporarily stored in the memory unit A correction value calculation unit for calculating a correction value per frame from the calculated timing difference and a structure in which a frame signal correcting section for holding the synchronization to correct the frame signal by setting the correction value.

With this configuration, the timing difference temporarily stored when the known pattern is not detected due to the disconnection of the communication line, the correction value per frame is calculated, and the synchronization between the transmission device and the reception device is calculated. Can hold.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is based on a control signal transmitted in a fixed multiple frame period and capable of detecting synchronous timing. A process of calculating the timing difference, a process of selecting either the direct value or the integrated value of the timing difference according to the operation mode, and a correction value for each frame using the direct value or the integrated value of the timing difference. A process of calculating and a frame synchronization correction method for correcting the frame timing signal using the correction value for each frame, wherein the correction process is performed in units of one frame, and the frame of the receiving device with respect to the frame signal of the transmitting device. It has the effect of minimizing the timing jitter of the signal.

[0012] The invention according to claim 2 of the present invention, claim
In the frame synchronization correction method described in 1,
In the process of calculating the correction value for each
The process of determining whether there is a difference and whether the timing difference is positive or negative.
Of the fixed frame period
Per frame to compensate evenly from the ming difference
A frame having a correction value calculation process for calculating a correction value.
This is a period correction method , and has an effect of minimizing the timing jitter of the frame signal of the receiving device with respect to the frame signal of the transmitting device by performing the correction process in units of one frame.

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

FIG. 1 shows an embodiment of the present invention.
~ It will be described in detail with reference to FIG.

(First Embodiment) In the first embodiment of the present invention, a known pattern detection signal generated by detecting a known pattern inserted in a control signal receivable in a fixed frame period is used. From the timer value latched at the time (t-1) and the timer value latched at the time (t) after the fixed frame period, the fixed timer number per fixed frame is latched. Of the fixed frame number between the time (t-1) and the time (t) between the transmission side frame signal and the reception side frame signal, and the timer value difference is calculated as 1 from the timing difference. A frame synchronization correction device that calculates a correction value per frame, corrects and holds the frame synchronization between transmission and reception for each frame based on the correction value.

FIG. 1 is a block diagram of a frame synchronization correction apparatus according to the first embodiment of the present invention. In FIG.
301 is a received signal. 302 is a reference clock. 303
Is a UW pattern detector, which detects UW from the received signal (301).
When a pattern is detected, a 305 UW detection pulse is generated. 304 is a reference timer, and a reference clock (30
It is counted by 2) and outputs the timer value of 306. 30
Reference numeral 7 denotes a latch unit, which takes in the timer value (306) of the reference timer (304) by the UW detection pulse (305). A timing difference calculation unit 311 calculates the timing difference (312) between the receiving device and the transmitting device from the latched timer value of 308 and the timer value (310) delayed by N frames by the flip-flop of 309.

A selector 314 switches the timing difference of 312 to output a or output b depending on the operation mode of 313. The timing difference at the time of output a is set to the initial timing difference value (315), and the timing difference at the time of output b is
With the timing difference (312) and 318 flip-flops,
By adding the timing difference (317) delayed by N frames, the total timing difference per N frame (31
6) A correction value calculation unit 319 calculates a correction value (320) per frame from the timing difference initial value (315) per N frames or the total timing difference (316). Reference numeral 321 denotes a frame signal correction unit, which generates a frame signal and performs a correction operation by setting a reference clock (302) and a correction value (320).

The operation of the frame synchronization correction apparatus according to the first embodiment of the present invention configured as described above will be described with reference to the timing chart of FIG. 2 and the flow chart of FIG. First, in the operation mode (313) (continuous reception operation) for the receiving device to perform initial frame synchronization pull-in with respect to the transmitting device, the received signal is received twice. At time (t), the timer value when the first UW pattern is received is y (t), and at time (t + 1), the timer value when the second UW pattern is received is y (t + 1). Then, the timing difference (312) between the transmitting and receiving devices in the N frame cycle which is the reception cycle of the UW pattern is calculated as the timing difference initial value (315) y (t ₀ ) = y (t + 1) −y (t). To do. At this time, depending on the operation mode (313),
The selector (314) is assumed to select the output a. Then, the timing difference initial value (315) y per N frames
By using (t ₀ ), the correction value calculation unit (319) calculates the correction value (320) for each frame.

The flow of the correction value calculation processing will be described with reference to FIG. First, it is judged whether or not a timing difference actually exists. If there is no timing difference, the correction value table creation 2 is performed. As a result, the correction value (320) T (n) for each frame is 0 for all N frames.
(No reframe signal correction). On the other hand, if there is a timing difference, the timing difference / integer part of N frames is calculated, the correction value J ₁ without rounding up is calculated, and the positive / negative of the timing difference is determined. Next, the round-up correction value J
₂ and the round-up correction value correction count C ₂ are calculated. When the timing difference is positive, J ₂ = J ₁ +1 and C ₂ = timing difference − (J ₁ × N frame), and when the timing difference is negative, J ₂ = J ₁ −1, C ₂ = − ( Timing difference 1 (J ₁ × N frame)).

After the correction number C ₂ of the round-up correction value is determined, the correction number C _{1 of the non} -round-up correction value is calculated as N frame−C ₂ . Then, the number C _{0 of} times when the correction value without rounding up and the correction value with rounding up are alternately set in N frames.
In order to calculate, the magnitude comparison by C ₁ > C ₂ is performed, and the smaller number is doubled. At this time, the larger correction value is substituted for J ₀ . In this way, when the correction values J ₁ and J ₂ and the correction numbers C ₁ and C ₂ are obtained, the correction value table is created 1
Is processed.

First, the correction value J ₁ without rounding up and the correction value J ₂ with rounding up are substituted into T (n) for the number of alternating repetitions C ₀ , and then J ₀ is substituted for the remaining number of frames. In this way, the correction value table for N frames is completed,
Correction value (320) T (n) from the correction value table for each frame
Is read out and set in the frame signal correction section, the frame signal of the receiving device is corrected and held in synchronization.

Next, the operation after switching the operation mode (313) to the normal transmission / reception operation will be described. After switching the operation mode (313), time (t + 2), (t + 3) ...
The timer values when the UW pattern is received are y (t + 2), y (t + 3). After latching the timer value y (t + 2), the timing difference (312) between the transmitting and receiving devices in the N frame period is calculated as y (t + 2) −y (t + 1). At this time, the selector (314) selects the output b according to the operation mode (313). Here, the total timing difference (317) y (t ₀ ) held in the flip-flop (318)
And the timing difference (312) y (t + 2) −y (t + 1) are added to calculate the total timing difference (316) y (t ₁ ) at the present time. Then, by using the total timing difference (314) y (t1) per N frames, the correction value calculation unit (31
In step 9), the correction value (320) is calculated for each frame.
After latching the timer value y (t + 3), the timing difference (312) between the transmitting and receiving devices in N frame cycles is set to y (t + 3) -y (t +
Calculate as 2).

Here, the total timing difference (317) y (t ₁ ) held in the flip-flop (318) and the timing difference (312) y (t + 3) −y (t + 2) are added. Then, the total timing difference (316) y (t ₂ ) at the present time is calculated. Then, the total timing difference per N frames (314) y (t ₂ )
The correction value calculation unit (319) calculates the correction value (320) for each frame by using. After that, the same operation is performed when the timer values y (t + 4), y (t + 5), y (t + 6) ... The operation of the correction value calculation process is the same as described above.

An example will be described by actually applying numerical values to the flow of correction value calculation processing. It is assumed that the total timing difference (316) is 13 (the unit is the minimum resolution of the timer value: for example, B symbol, B clock, etc.) (N = 24) and the UW pattern is received in the frame cycle. Therefore, J ₁ = 0, C ₁ = 11, J ₂
= 1, C ₂ = 13, J ₀ = J ₂ = 1 and the correction value table is 010101010101010101010111 (when the shaded area in the correction value table creation 1 is used) or 10101010101010
It is created as in 1010101011 (when the shaded area of the correction value table creation 1 is used).

FIG. 4 shows the state of timing jitter when a correction process is performed using this correction value. In the case of FIG. 4, 24
This is an example of the case where a timing difference 14 occurs in the next 24 frame cycles with respect to the frame cycle correction amount 13. In this case, the timing difference (13 + difference 1) is corrected in the next 24 frames and the same processing is performed thereafter. As can be seen from FIG. 4, according to the present invention, it is possible to suppress the timing jitter to be extremely small as compared with the conventional device.

As described above, in the first embodiment of the present invention, the frame synchronization correction apparatus detects the known pattern generated by detecting the known pattern inserted in the control signal receivable at the fixed frame period. The signal latches the timer value of the reference timer that operates with the reference clock, and
From the difference between the latched timer value in 1) and the latched timer value at time (t) after the fixed frame period, the difference in the timer value per fixed frame number is calculated, and the calculated difference is transmitted. A timing difference per fixed number of frames between the time (t-1) and the time (t) of the frame signal and the frame signal on the receiving side, and a correction value per frame to correct this timing difference for each frame. Is calculated and the frame synchronization between transmission and reception is corrected and held. Therefore, the correction process can be performed in units of one frame to minimize the timing jitter of the frame signal of the reception device with respect to the frame signal of the transmission device. .

(Second Embodiment) The second embodiment of the present invention uses a known pattern detection signal generated by detection of a known pattern inserted in a control signal receivable at a fixed frame period. Latch the timer value of the reference timer that operates on the reference clock, and use the timer value and the timing reference value (the timer value when there is no difference between the sending frame signal and the receiving frame signal) to determine the timer value per fixed number of frames. The difference is calculated, the timer value difference is used as the timing difference per fixed number of frames of the transmission side frame signal and the reception side frame signal, the correction value per frame is calculated from the timing difference, and the frame synchronization between transmission and reception is calculated by the correction value. 1
A frame synchronization correction device that corrects and holds each frame.

FIG. 5 is a block diagram of a frame synchronization correction apparatus according to the second embodiment of the present invention. In FIG.
Reference numeral 701 is a received signal. 702 is a reference clock. 703
Is a UW pattern detector, which detects UW from the received signal (701).
When a pattern is detected, a 705 UW detection pulse is generated. 704 is a reference timer, reference clock (702)
And the timer value of 706 is output. Reference numeral 707 denotes a latch unit which takes in the timer value (706) of the reference timer (704) by the UW detection pulse (705). Reference numeral 711 denotes a timing difference calculation unit, which stores the latched timer value of 708 and 723
The timing difference (712) between the receiving device and the transmitting device is calculated from the timing reference value of. A flip-flop 724 delays the timing difference (716) by N frame periods and outputs it as a positive timing difference (725) and a negative timing difference (726).

A selector 727 selects and outputs a positive timing difference (725) of the input a and a negative timing difference (726) of the input b according to the operation mode of 713. 716 is the total timing difference, which is determined by the sum of the timing difference delayed by N frame periods of 717 and the current timing difference. Reference numeral 719 denotes a correction value calculation unit that calculates the correction value per frame (7) from the total timing difference (716) per N frames.
20) is calculated. A frame signal correction unit 721 generates a frame signal and performs a correction operation by setting a reference clock (702) and a correction value (720).

The operation of the frame synchronization correction apparatus according to the second embodiment of the present invention configured as above will be described with reference to the timing chart of FIG. First, the reception signal is received twice in the operation mode (713) (continuous reception operation) for the reception device to perform initial frame synchronization pull-in with respect to the transmission device. At this time, it is assumed that the selector (727) is selecting the input b. At time (t), y is the timer value when the first UW pattern is received.
(t), and the difference between the timing reference value (723) and the timer value y (t) is calculated by the timing difference calculation unit (711). Time (t
In (+1), the timer value when the UW pattern is received for the second time is set to y (t + 1), and the timing difference calculation unit (711) sets the timing reference value (723) and the timer value y (t + 1). Take the difference.

Then, the negative timing difference (726) (-y (t) -y (b
ase)) and the current time (t + 1) timing difference (712) (y
The total timing difference (716) y (t ₀ ) per N frame period is calculated by adding (t + 1) −y (base)).
And the total timing difference per N frames (715) y
The correction value calculation unit (719) calculates the correction value (720) for each frame by using (t ₀ ). The flow of the correction value calculation process is the same as that of the first embodiment shown in FIG. 3, and therefore its explanation is omitted.

Next, the operation after switching the operation mode (713) to the normal transmission / reception operation will be described. After switching the operation mode (313), time (t + 2), (t + 3) ...
The timer values when the UW pattern is received are y (t + 2), y (t + 3). At this time, the reselector (727) selects the input a according to the operation mode (713). After latching the timer value y (t + 2), set the timing difference (712) between the transmitter and receiver in N frame cycles to y (t + 2).
Calculate as -y (base). Here, the total timing difference (725) y (t ₀ ) and the timing difference (712) y (t + 2) − N frame periods before held in the flip-flop (724)
The total timing difference (716) y (t ₁ ) at the present time is calculated by adding y (base).

Then, the correction value calculating unit (719) is used by using the total evening difference (714) y (t ₁ ) per N frames.
At, the correction value (720) is calculated for each frame. After latching the timer value y (t + 3), the timing difference (712) between the transmitting and receiving devices in N frame cycles is set to y (t + 3) −y (base).
Calculate as Here, the total timing difference (725) before N frame cycles held in the flip-flop (724)
By adding y (t ₁ ) and timing difference (712) y (t + 3) −y (base), the total timing difference at the present time (716) y (t ₂ )
To calculate. Then, by using the total timing difference (714) y (t ₁ ) per N frames, the correction value calculation unit (71
In step 9), the correction value (720) for each frame is calculated.
After that, the same operation is performed when the timer values y (t + 4), y (t + 5), y (t + 6) ... The operation of the correction value calculation process is the same as that of the first embodiment shown in FIG.

As described above, in the second embodiment of the present invention, the frame synchronization correction apparatus detects the known pattern generated by detecting the known pattern inserted in the control signal receivable at the fixed frame period. The signal is used to latch the timer value of the reference timer that operates with the reference clock, and the difference between the latched timer value and the timing reference value (the timer value when there is no difference between the transmission-side frame signal and the reception-side frame signal) , A difference between timer values per fixed frame number is calculated, and the calculated difference is used as a timing difference per fixed frame number between the transmission side frame signal and the reception side frame signal, and the timing difference is corrected for each frame. Since the configuration is such that the correction value for each frame is calculated and the frame synchronization between transmission and reception is corrected and held, the correction process is performed on a frame-by-frame basis. , It is possible to suppress the timing jitter of the frame signal of the receiving device with respect to the frame signal of the transmission apparatus to a minimum.

(Third Embodiment) In the third embodiment of the present invention, a control signal can be arbitrarily variably set from the outside with respect to a control signal receivable in a fixed frame period. Is a frame synchronization correction device that makes it possible to set the reception interval of to the set frame period.

FIG. 7 is a block diagram of a frame synchronization correction apparatus according to the third embodiment of the present invention. In FIG.
901 is a received signal. 902 is a reference clock. 903
Is a UW pattern detector, which detects UW from the received signal (901).
When a pattern is detected, a 905 UW detection pulse is generated. 904 is a reference timer, reference clock (902)
And the timer value of 906 is output. Reference numeral 907 denotes a latch unit which fetches the timer value (906) of the reference timer (904) by the UW detection pulse (905). Reference numeral 911 is a timing difference calculation unit, which uses the latched timer value of 908 and 909
The timing difference (912) between the receiving device and the transmitting device is calculated from the timer value (910) delayed by (N × k) frames by the flip-flop of.

Reference numeral 914 is a selector, which is 91 depending on the operation mode of 913.
The timing difference of 2 is switched to output a or output b. The timing difference at the time of output a is set as the timing difference initial value (915), and the timing difference at the time of output b is (N × k) by the timing difference (912) and the flip-flop of 918.
The timing difference (917) delayed by the number of frames is added to obtain the total timing difference (916) per frame (N × k). Reference numeral 919 is a correction value calculation unit, which is (N × k)
A correction value (920) per frame is calculated from the initial timing difference value (915) per frame or the total timing difference (916). 921 is a frame signal correction unit,
A frame signal is generated and a correction operation is performed by setting the reference clock (902) and the correction value (920).

The third embodiment of the present invention is basically based on the configuration shown in the first embodiment, and has a characteristic feature.
Variable frame number register (929) and frame counter (9
By providing 31), the frame period of the received signal can be arbitrarily controlled from the outside by the frame parameter (928).

The operation of the frame synchronization correction apparatus of the third embodiment of the present invention configured as above will be described with reference to the timing chart of FIG. First of all,
The reception frame cycle of the reception signal is set by the frame parameter (928). As a result, data is set in the variable frame number register (929) and the frame counter (931) operated by the frame signal (922) is set to (N
× k) Start the operation at the frame cycle. After that, the basic operation is the same as the operation description shown in the first embodiment.

The frame parameter 2 will be described here. The reception signal is received twice in the operation mode (913) (continuous reception operation) for the reception device to perform initial frame synchronization pull-in with respect to the transmission device. At time (t), the timer value when the first UW pattern is received is set to y (t), and at time (t + 1), the frame period of the received signal is set to 2N, so no correction processing is performed. . At time (t + 2), the timer value when the UW pattern is received for the second time is set to y (t + 2), and the timing difference (912) between the transmitter and the receiver in the 2N frame cycle which is the UW pattern reception cycle is set as the timing difference. An initial value (915) y (t ₀ ) = y (t + 2) −y (t) is calculated. At this time, the selector (914) selects the output a according to the operation mode (913). And the initial value of the timing difference per 2N frame (915)
The correction value calculation unit (919) calculates the correction value (920) for each frame by using y (t ₀ ).

The flow of the correction value calculation processing is the same processing thereafter by setting the N frame shown in FIG. 3 to 2N frames. First, it is judged whether or not a timing difference actually exists. Here, when there is no timing difference,
The correction value table creation process 2 is performed. This gives 1
The correction value (920) T (n) for each frame becomes 0 (that is, no frame signal correction) for 2N frames. On the other hand, when there is a timing difference, the timing difference ÷ the integer part of 2N frames is calculated to calculate the correction value J ₁ without rounding up,
Whether the timing difference is positive or negative is determined. Next, the round-up correction value J ₂ and the round-up correction value correction count C ₂ are calculated.

When the timing difference is positive, J ₂ = J ₁ +1 and C ₂ = timing difference − (J ₁ × 2N frame), and when the timing difference is negative, J ₂ = J ₁ −1, C ₂ = -(Timing difference- (J ₁ × 2N frame)).

After the correction number C ₂ of the round-up correction value is determined, the correction number C _{1 of the non} -round-up correction value is calculated as C ₂ = 2N frame-C ₂ . Then, the number C of times when the correction value without rounding up and the correction value with rounding up are alternately set within the 2N frame
_In order to calculate ₀ , the magnitude comparison by C ₁ > C ₂ is performed, and the smaller number is doubled. At this time, the larger correction value is substituted for J ₀ . In this way, when the correction values J ₁ and J ₂ and the correction numbers C ₁ and C ₂ are obtained, the correction value table is created 1
Is processed.

First, the correction value J ₁ without rounding up and the correction value J ₂ with rounding up are substituted into T (n) for the number of alternating repetitions C ₀ , and then J ₀ is substituted for the remaining number of frames.
In this way, the correction value table for 2N frames is completed, and the correction value (920) T (n) is read from the correction value table for each frame and set in the frame signal correction unit, so that the frame signal of the receiving device is corrected and synchronized. Retained.

Next, the operation after switching the operation mode (913) to the normal transmission / reception operation will be described. Even after switching the operation mode (913), similarly, the received signal is received at the 2N frame cycle, and the timer value when the UW pattern at the time (t + 4), (t + 6) ... Is received is y (t +).
4), y (t + 6) ... After latching the timer value y (t + 4),
The timing difference (912) between the transmitting and receiving devices in the 2N frame period is calculated as y (t + 4) −y (t + 2). At this time, the selector (914) selects the output b according to the operation mode (913).

Here, the total timing difference (917) y (t ₀ ) held in the flip-flop (918) and the timing difference (912) y (t + 4) −y (t + 2) are added. The total timing difference (916) y (t ₁ ) at the present time is calculated by. And the total timing difference per 2N frame (914) y
The correction value calculation unit (919) calculates the correction value (920) for each frame by using (t ₁ ). Timer value y
After latching (t + 6), the timing difference (912) between the transmitting and receiving devices in the 2N frame period is calculated as y (t + 6) −y (t + 4). Here, by adding the total timing difference (917) y (t ₁ ) held in the flip-flop (918) and the timing difference (912) y (t + 6) −y (t + 4), Calculate the total timing difference (916) y (t ₂ ) in.

Then, by using the total timing difference (914) y (t ₂ ) per 2N frame, the correction value calculation unit (9
In step 19), the correction value (920) for each frame is calculated. After that, timer values y (t + 8), y (t + 10), y (t + 12) ...
The same operation is performed when The operation of the correction value calculation process is the same as described above.

As described above, according to the third embodiment of the present invention, the frame synchronization correction apparatus is capable of variably setting the number of frames from the outside with respect to the control signal receivable in the fixed frame period. Since the control signal reception interval is set as the set frame period, the number of frames is arbitrarily set and the control signal reception interval is variable to minimize the correction processing operation and reduce the power consumption of the device. realizable.

(Fourth Embodiment) In the fourth embodiment of the present invention, the known pattern detection which temporarily stores the timing difference per fixed number of frames or the set number of frames and has the information on the presence / absence of detection of the known pattern. It is a frame synchronization correction device capable of reading the timing difference temporarily stored by the presence / absence signal when a known pattern is not detected.

FIG. 9 is a block diagram of a frame synchronization correcting apparatus according to the fourth embodiment of the present invention. In FIG.
1101 is a received signal. 1102 is a reference clock. 11
03 is a UW pattern detection unit, which detects U from the received signal (1101)
When the W pattern is detected, the UW detection pulse 1105 is generated. Reference numeral 1104 is a reference timer, and a reference clock (11
It is counted by 02) and the timer value of 1106 is output. 11
Reference numeral 07 denotes a latch unit which takes in the timer value (1106) of the reference timer (1104) by the UW detection pulse (1105). 1111
Is a timing difference calculation unit, which calculates the timing difference (1112) between the receiving device and the transmitting device from the latched timer value of 1108 and the timing reference value of 1123.

A flip-flop 1124 delays the timing difference (1116) by N frame cycles and outputs it as a positive timing difference (1125) and a negative timing difference (1126). 1127 is a selector for input a depending on the operation mode of 1113
The positive timing difference (1125) and the negative timing difference (1126) of the input b are selected and output. 1116 is the total timing difference, which is determined by the sum of the timing difference delayed by N frame periods of 1117 and the current timing difference.
Reference numeral 1119 denotes a correction value calculation unit, which calculates a correction value per frame (112
0) is calculated. Reference numeral 1121 denotes a frame signal correction unit, which generates and corrects a frame signal by setting a reference clock (1102) and a correction value (1120).

The fourth embodiment of the present invention is basically based on the configuration shown in the second embodiment, and has a characteristic feature.
By providing the memory unit (1133) for storing the total timing difference (1116) per N frames, the timing difference read from the memory even when the communication line disconnection (when the UW pattern is not detected) continues for a long time. From this, the correction value per frame can be calculated.

The operation of the frame synchronization correction apparatus of the fourth embodiment of the present invention configured as above will be described with reference to the timing chart of FIG. The basic operation (state in which the UW pattern can be detected) is the same operation as that described in the second embodiment. In the present embodiment, UW
In the state where the pattern is detected, one or a plurality of timing differences (1116) actually calculated per N frame are stored in the memory as correction history information.
Therefore, if the line between the transmitter and the receiver is in an abnormal state (when the UW pattern is not detected), the known pattern detector (11
The known pattern detection presence / absence signal (1135) output from 03) indicates a non-detection state, and the selector (1128) switches to the memory side (input b). As a result, the correction history information is read from the memory unit, and even when the UW pattern is not detected, correction can be performed with a value extremely close to the actual timing deviation, and the synchronization state between the transmitting and receiving devices is maintained. be able to. After the line status is restored, the selector (11
28) is switched to the input a, and the frame correction and the synchronization processing are performed again in the normal line state. In addition, the correction history information in the memory unit is sequentially updated, and the correction history information is updated to prepare for the line abnormality state.

As described above, in the fourth embodiment of the present invention, the frame synchronization correction apparatus temporarily stores the timing difference per fixed frame number or set frame number,
Since the timing pattern temporarily stored when the known pattern is not detected is read by the known pattern detection presence / absence signal having the information on the presence / absence of the detection of the known pattern, the communication line disconnection (U
Even when the W pattern is not detected) continues for a long time, the correction value per frame can be calculated from the timing difference read from the memory, and synchronization between the transmitter and the receiver can be maintained.

[0068]

As described above, according to the present invention, since the correction process is carried out on a frame-by-frame basis, the timing jitter of the frame signal of the receiving device with respect to the frame signal of the transmitting device can be minimized. To be

Further, since the correction processing operation can be minimized by arbitrarily setting the number of frames and varying the reception interval of the control signal, there is an effect that the power consumption of the apparatus can be reduced.

Also, the communication line is disconnected (when no UW pattern is detected).
Since the correction value per one frame can be calculated from the timing difference read from the memory even when is continued for a long time, it is possible to achieve the effect that the transmitter and the receiver can be kept in synchronization.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a frame synchronization correction device according to a first embodiment of the present invention,

FIG. 2 is a timing chart according to the first embodiment of the present invention,

FIG. 3 is a flowchart according to the first embodiment of the present invention,

FIG. 4 is a diagram showing timing jitter due to a correction process according to the first embodiment of the present invention;

FIG. 5 is a functional block diagram of a frame synchronization correction device according to a second embodiment of the present invention,

FIG. 6 is a timing chart according to the second embodiment of the present invention,

FIG. 7 is a functional block diagram of a frame synchronization correction device according to a third embodiment of the present invention,

FIG. 8 is a timing chart according to a third embodiment of the present invention,

FIG. 9 is a functional block diagram of a frame synchronization correction device according to a fourth embodiment of the present invention,

FIG. 10 is a timing chart according to a fourth embodiment of the present invention,

FIG. 11 is a functional block diagram of a conventional frame synchronization correction device,

FIG. 12 is a timing chart in a conventional frame synchronization correction device.

[Explanation of symbols]

101,301,701,901,1101 Received signal 102,302,702,902,1102 Reference clock 103,303,703,903,1103 UW (known) pattern detector 104,304,704,904,1104 Reference timer 105,305,705,905,1105 UW (known) pattern detection pulse 106,306,706,906,1106 Reference timer 107,907,907,107,907,107,907,107 1108 Latched reference timer timer value 109 UW pattern detection time histogram calculation unit 110 Histogram calculation result 111 Timing correction value detection unit 112 Correction value detection result 113 Timing allowable value 114 Frame signal generation unit 115,322,722,922,1122 Frame signal 311,711,911,1111 Timing Difference calculation unit 312,712,912,1112 Timing difference 309,318,724,909,918,1124 Flip-flop 316,716,916,1116,1134,1136 Total timing difference 314,727,914,1127,1128 Selector 310,317,717,725,726,910,917,1117,1125,1126 Delayed timing difference 319,719,920,1120,119,1320 Correction value 321,721,921,1121 Frey Signal correcting unit 313,713,913,1113 operation mode 723,1123 timing reference value 315,915 timing difference initial value 928 Frame Parameters 929 number of frames variable resistor 930 frame number variable register value 931 frame counter 932 frame counter value 1133 memory unit 1135 known pattern detecting presence signal

Claims (2)

(57) [Claims] 1. A process of calculating a timing difference between a frame timing of a transmitting device and a frame timing of a receiving device based on a control signal transmitted in a fixed multiple frame period and capable of detecting synchronous timing, and a direct value of the timing difference. And a cumulative value according to the operation mode, a step of calculating a correction value for each frame using the direct value of the timing difference or the cumulative value, and a step of using the correction value for each frame. A frame synchronization correction method, which comprises: 2. A method for calculating a correction value for each frame
The process of determining the presence or absence of the timing difference
And a step of determining whether the timing difference is positive or negative,
Corrects evenly from the timing difference per constant frame period
Correction value calculation to calculate the correction value per frame for
The process according to claim 1, further comprising a discharging process.
Lame synchronization correction method.