JP3394895B2 - Semiconductor storage device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask R, for example.
The present invention relates to a semiconductor memory device such as an OM (Read Only Memory) that performs data writing at the stage of forming a memory cell, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, for example, a mask ROM is known as a semiconductor memory device in which data is written at the manufacturing stage.

As such a mask ROM, a type in which data is written by implanting impurity ions is known. Mask RO of this type
In M, the threshold values are different between the MOS transistor into which the impurity ions are not implanted and the MOS transistor into which the impurity ions are implanted, and these two kinds of threshold values correspond to “0” and “1” of information, respectively. .

[0004]

A general method for manufacturing a conventional mask ROM of this type will be described below with reference to FIGS.
This will be described with reference to the sectional process drawing shown in FIG.

First, for example, L on the semiconductor wafer 601.
After forming the element isolation film 602 by using the OCOS method, a sacrificial oxide film 603 is formed (see FIG. 6A).

Next, a resist film is formed on the entire surface of the semiconductor wafer 601, and the resist film is patterned by using a normal photolithography technique to form a gate electrode forming region (that is, a channel) of a transistor into which impurity ions are implanted. A resist pattern 604 having an opening only in the formation region) is obtained. Further, impurity ions are implanted from above the resist pattern 604 to form an impurity introduction region 605 near the surface of the semiconductor wafer 601 (see FIG. 6B). Then, the resist pattern 604 and the sacrificial oxide film 603 are removed.

Subsequently, a gate electrode 606 is formed (see FIG. 6C).

Further, on the entire surface of the semiconductor wafer 601,
An interlayer insulating film 607 is formed (see FIG. 6D).

After forming a contact hole 608 in a desired region of the interlayer insulating film 607, a metal material is deposited on the entire surface to form a metal layer 609 (see FIG. 7A).

Then, the metal layer 609 is patterned by using a normal photolithography technique to form a metal wiring 610 (see FIG. 7B).

Finally, a protective film 611 is deposited on the entire surface, and the mask ROM manufacturing process is completed (see FIG. 7C).

Although the case where the resist pattern 604 is formed on the sacrificial oxide film 603 and the impurity ions are implanted has been described here (see the above step), the impurity ions may be implanted in the subsequent steps. .

FIG. 8A shows a case where impurity ions are implanted after forming the gate electrode 606.

In this case, first, the steps described above are performed, and then a resist pattern 801 is formed on the entire surface of the semiconductor wafer 601. Furthermore, by implanting impurity ions from above the resist pattern 801, an impurity introduction region 802 is formed near the surface of the semiconductor wafer 601. Then, after removing the resist pattern 801 and the sacrificial oxide film 603, the above steps 1 to 5 are performed.

Further, FIG. 8B shows a case where impurity ions are implanted after the interlayer insulating film 607 is formed.

In this case, first, the above steps,
(However, the sacrificial oxide film 603 is not formed), and then a resist pattern 803 is formed on the entire surface of the interlayer insulating film 607.
To form. Further, by implanting impurity ions from above the resist pattern 803, the semiconductor wafer 6
An impurity introduction region 804 is formed in the vicinity of the surface 01. Then, after removing the resist pattern 803, the above-described steps 1 to 3 are performed.

FIG. 8C shows a case where impurity ions are implanted after the metal wiring 610 is formed.

In this case, first, the above steps,
(However, the sacrificial oxide film 603 is not formed), and then a resist pattern 805 is formed on the entire surface of the interlayer insulating film 607.
To form. Further, by implanting impurity ions from above the resist pattern 805, the semiconductor wafer 6
An impurity introduction region 806 is formed in the vicinity of the surface 01. Then, after removing the resist pattern 805, the above steps are performed.

FIG. 8D shows a case where impurity ions are implanted after forming the protective film 611. In this case, first, the above steps 1 to 3 are performed (however, the sacrificial oxide film 603 is not formed), and subsequently, a resist pattern 807 is formed on the entire surface of the protective film 611. Further, impurity ions are implanted from above the resist pattern 807 to form an impurity introduction region 808 near the surface of the semiconductor wafer 601. Then, the resist pattern is removed.

According to each manufacturing method as described above,
Data can be written in the mask ROM at the manufacturing stage by manufacturing a MOS transistor into which impurity ions are not implanted and a MOS transistor into which impurity ions are implanted.

Here, in such a mask ROM, the contents of the data written at the manufacturing stage are not always the same, and a plurality of types are manufactured in parallel, or appropriately changed according to the user's request. It is usually done. Therefore, it is necessary to determine the type of write data by some method.

Conventionally, as a method of discriminating the type of write data, a method of discriminating from the history of a wafer or a method of discriminating using a wiring pattern has been considered.

However, the method of discriminating from the history of the wafer has a drawback that it cannot be used after the chip cutting process.

Further, in the method of discriminating from the wiring pattern, it is necessary to prepare different masks for forming the wiring pattern depending on the type of write data, which leads to an increase in manufacturing cost. There was a flaw.

For this reason, there has been a demand for a technique capable of discriminating the type of write data by a simple method.

[0026]

(1) A first aspect of the present invention relates to a semiconductor memory device in which data writing is performed at the stage of forming memory cells on the surface of a semiconductor substrate. Further, it is characterized in that it has a data identification pattern formed by an etching step for identifying the content of the write data of the memory cell, and the data identification pattern is provided on the surface of the interlayer insulating film.

According to such a structure, the type of write data can be discriminated by the data identification pattern provided on the surface of the interlayer insulating film.

(2) The second invention relates to a semiconductor memory device in which data is written at the stage of forming memory cells on the surface of a semiconductor substrate. A surface of the second pattern forming thin film having a data identification pattern formed by an etching step to identify the content of the write data of the memory cell, and the data identification pattern is formed on the interlayer insulating film. It is characterized in that it is provided in.

According to this structure, the type of write data can be discriminated by the data identification pattern provided on the surface of the second pattern forming thin film.

(3) In the third invention, data writing is performed at the stage of forming the memory cell on the surface of the semiconductor substrate, and a data identification pattern for identifying the content of the write data of the memory cell is formed. For this purpose, an impurity implantation step of simultaneously or continuously performing impurity implantation into a desired channel formation region of a memory cell and impurity implantation into a data identification pattern formation region using one type of mask pattern, and the entire surface of the semiconductor substrate. And a step of forming an etching step as a data identification pattern by etching the semiconductor memory device. Then, a first step of forming an element isolation film on the surface of the semiconductor substrate, and after forming a sacrificial oxide film and a resist film on the semiconductor substrate and the element isolation film, forming a desired channel of a memory cell in the resist film. A second step of opening a region and a portion of the element isolation film corresponding to the data identification pattern forming region, and a step of simultaneously performing impurity implantation into the surface of the semiconductor substrate and impurity implantation into the element isolation region using the resist film as a mask. 3 steps, a fourth step of removing the resist film, a fifth step of simultaneously removing the sacrificial oxide film and forming a data identification pattern by etching the entire surface of the semiconductor substrate, and an element on the surface of the semiconductor substrate. A sixth step of forming an isolation film, a seventh step of forming a first pattern forming thin film on a semiconductor substrate and an element isolation film, and a first pattern An eighth step of forming a resist film on the target thin film and then opening respective portions of the resist film corresponding to desired channel formation regions and data identification pattern formation regions of the memory cells, and a semiconductor substrate using the resist film as a mask A ninth step of continuously performing the impurity implantation into the region on the surface and the impurity implantation into the first pattern forming thin film at different implantation depths, a tenth step of removing the resist film, and a first step. An eleventh step of forming a data identification pattern by etching the entire surface of the pattern forming thin film.

According to such a manufacturing method, the data identification pattern can be formed by a simple process.

(4) According to a fourth aspect of the invention, data writing is performed at the stage of forming a memory cell on the surface of a semiconductor substrate, and a data identification pattern for identifying the content of write data of the memory cell is formed. For this purpose, an impurity implantation step of simultaneously or continuously performing impurity implantation into a desired channel formation region of a memory cell and impurity implantation into a data identification pattern formation region using one type of mask pattern, and the entire surface of the semiconductor substrate. And a step of forming an etching step as a data identification pattern by etching the semiconductor memory device. Then, a twelfth step of forming an element isolation film on the surface of the semiconductor substrate, a thirteenth step of forming an interlayer insulating film on the element isolation film and the memory cell, and after forming a resist film on the interlayer insulating film A fourteenth step of opening portions of the resist film corresponding to desired channel formation regions and data identification pattern formation regions of the memory cells, and impurity implantation into the semiconductor substrate surface and the interlayer insulating film using the resist film as a mask Fifteenth step of continuously performing impurity implantation into the layer at different implantation depths, sixteenth step of removing the resist film, and seventeenth step of forming a data identification pattern by etching the entire surface of the interlayer insulating film. And a process.

According to such a manufacturing method, the data identification pattern can be formed by a simple process.

(5) According to a fifth aspect of the invention, data writing is performed at the stage of forming a memory cell on the surface of a semiconductor substrate, and a data identification pattern for identifying the content of write data of the memory cell is formed. For this purpose, an impurity implantation step of simultaneously or continuously performing impurity implantation into a desired channel formation region of a memory cell and impurity implantation into a data identification pattern formation region using one type of mask pattern, and the entire surface of the semiconductor substrate. And a step of forming an etching step as a data identification pattern by etching the semiconductor memory device. Then, an eighteenth step of forming an element isolation film on the surface of the semiconductor substrate and a first step of forming an interlayer insulating film and a second pattern forming thin film on the element isolation film and on the memory cell
9 steps, and a 20th step of forming a resist film on the second pattern forming thin film and then opening respective portions of the resist film corresponding to desired channel formation regions and data identification pattern formation regions of the memory cells. A 21st step of continuously performing impurity implantation into a region on the semiconductor substrate surface and impurity implantation into the second pattern forming thin film by using the resist film as a mask and changing the implantation depth, and removing the resist film And a twenty-third step of forming a data identification pattern by etching the entire surface of the second pattern forming thin film.

According to such a manufacturing method, the data identification pattern can be formed by a simple process.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings by taking a case where the present invention is applied to a mask ROM as an example. It should be noted that, in the drawings, the size, shape, and arrangement relationship of each constituent component are only schematically shown to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. Please understand that.

First Embodiment Hereinafter, a mask ROM according to a first embodiment of the present invention
And the manufacturing method thereof is demonstrated.

In this embodiment, the data identification pattern is directly formed on the surface of the element isolation film.

FIG. 1 shows a mask RO according to this embodiment.
FIG. 8 is a cross-sectional process diagram that schematically shows the manufacturing process for M.

First, similarly to the conventional case, the element isolation film 102 is formed on the semiconductor wafer 101 by, for example, the LOCOS method, and then the sacrificial oxide film 103 is formed (see FIG. 1A).

Next, a resist film is formed on the entire surface of the sacrificial oxide film 103, and then the resist film is patterned by using a normal photolithography technique.
A resist pattern 104 is formed (see FIG. 1B).

Here, in this patterning, a portion 104a corresponding to a desired channel formation region of the memory cell is formed.
(That is, a portion corresponding to the channel formation region of the transistor for adjusting the threshold value) and a portion 104b corresponding to the data identification pattern formation region are opened. That is, since the data identification pattern is formed on the surface of the device isolation film 102 in this embodiment, the device isolation film 10 is formed.
The resist pattern 104 is formed so that a part of 2 is exposed.

Subsequently, impurity ions such as arsenic As are implanted from above the resist pattern 104 at an energy of 40 keV and a dose amount of 1 × 10 ¹³ ions / cm ² to introduce impurities into the vicinity of the surface of the semiconductor wafer 101. Regions 105 and 106 are formed (see FIG. 1C).
Then, the resist pattern 104 is removed.

Next, the semiconductor wafer 101 is wet-etched using, for example, hydrofluoric acid HF. And thereby, the sacrificial oxide film 103 is removed.

Here, in this embodiment, as described above, a large amount of As ions are implanted into the impurity introduction region 106 of the element isolation film 102 (see the process). Therefore, in the element isolation region 102, the impurity introduction region 106 has a higher etching rate than the other regions. Therefore, when etching is performed to remove the sacrificial oxide film 103, an etching step is generated between the impurity-introduced region 106 and another region, which causes
The data identification pattern 107 is formed (see FIG. 1D).

Thereafter, in the same manner as in the conventional case, after forming the gate electrode 108, the interlayer insulating film 109 is formed on the entire surface of the semiconductor wafer 101, and further, the interlayer insulating film 10 is formed.
After forming the contact hole 110 and the metal wiring 111 in the desired region of 9, the protective film 112 is deposited, and the mask ROM manufacturing process is completed (see FIG. 1E).

The data identification patterns of each chip formed on the same semiconductor wafer 101 may be the same pattern or different patterns for each chip. That is, when the write data of each chip is the same, the data identification pattern is the same, and when there are two or more types of write data, the data identification pattern may be changed accordingly.

As described above, according to the mask ROM of this embodiment, since the data identification pattern 107 is formed on the surface of the element isolation film 102, the type of data written in the memory cell can be easily determined. Can be determined.

Further, according to the manufacturing method of this embodiment, the mask formation and the ion implantation of the data identification pattern 107 are performed in the same step as the mask formation and the ion implantation for the data writing (the above-mentioned). Process,
) And etching sacrificial oxide film 103
Since it is decided to perform the same step as the removal of the above (the above-mentioned step), the number of steps is not increased. Therefore, the data identification pattern 107 can be manufactured at low cost.

Further, according to this embodiment, as described above, it is possible to simultaneously manufacture chips having different write data on the same semiconductor wafer 101, and thus manufacture a large number of mask ROMs of a small number one by one. It is effective when you want to.

Second Embodiment Next, a mask ROM according to a second embodiment of the present invention.
And the manufacturing method thereof is demonstrated.

In this embodiment, the data identification pattern is formed on the surface of the first pattern forming thin film formed between the semiconductor wafer or the element isolation film and the interlayer insulating film. Further, here, an NSG (nitride silicate glass) thin film is used as the first pattern forming thin film.

FIG. 2 shows a mask RO according to this embodiment.
FIG. 8 is a cross-sectional process diagram that schematically shows the manufacturing process for M.

First, an element isolation film 202 is formed on the semiconductor wafer 201 by using, for example, the LOCOS method, and then a gate electrode 203 is formed.

Then, a 100 nm thick NSG thin film 204 is formed on the entire surface of the semiconductor wafer 201 (see FIG. 2A).

Next, a resist film is formed on the entire surface of the semiconductor wafer 201, and then the resist film is patterned by using a normal photolithography technique to form a resist pattern 205 (see FIG. 2B). .

Similar to the first embodiment described above, in this patterning, a portion 205a corresponding to the channel forming region of the transistor for adjusting the threshold and a portion 205b corresponding to the data identification pattern forming region are opened. .

Then, using this resist pattern 205, impurity ion implantation for data writing is performed.
In this ion implantation, for example, phosphorus P is used as the impurity ions, the implantation energy is 400 keV, and the dose is 1
It may be set to × 10 ¹³ ions / cm ² . Thus, the impurity introduction region 206 can be formed on the surface of the semiconductor wafer 201 (see FIG. 2C). At the same time,
The impurity introduction region 206a is also formed by the opening 205b.

Next, using this resist pattern 205, impurity ion implantation for forming a data identification pattern is performed. In this ion implantation, for example, arsenic As is used as the impurity ions and the implantation energy is 30 keV.
The dose amount may be 1 × 10 ¹³ ions / cm ² . As a result, the impurity introduction region 2 is formed on the surface of the NSG thin film 204.
07 can be formed (see FIG. 2C). At the same time, the impurity introduction region 207a is also formed by the opening 205a.

After that, the resist pattern 205 is removed, and the NSG thin film 204 is wet-etched. The etching conditions at this time may be determined so that the NSG thin film 204 is removed to a thickness of about 50 nm, for example.

Here, a large amount of As ions are implanted in the impurity introduction region 207 of the NSG thin film 204 (see the process). Therefore, the impurity introduction region 20
In No. 7, the etching rate is higher than in other regions. Therefore, when wet etching is performed, an etching step is generated between the impurity introduced region 207 and another region, whereby the data identification pattern 208 is formed (see FIG. 2D). At the same time, an etching step is formed in the impurity introduction region 207a, but this step is not used as a data identification pattern.

After that, in the same manner as in the conventional case, after forming the interlayer insulating film 209 on the entire surface of the semiconductor wafer 201, and further forming the contact hole 210 and the metal wiring 211 in a desired region of the interlayer insulating film 209. Protective film 2
12 is deposited, and the mask ROM manufacturing process is completed (see FIG. 2E).

Also in this embodiment, as in the case of the above-described first embodiment, when the write data of each chip is different in the same semiconductor wafer 201, the data identification pattern is set accordingly. You can change it.

As described above, also in the mask ROM according to this embodiment, as in the case of the first embodiment, the data identification pattern 208 is formed, so that the type of data written in the memory cell is determined. It can be easily identified.

Further, in the manufacturing method according to this embodiment, the data identification pattern 2 can be obtained only by adding simple steps.
Since 08 can be obtained, the manufacturing cost is low.

Further, it becomes possible to simultaneously manufacture chips with different write data on the same semiconductor wafer 201, which is effective when it is desired to manufacture a large number of mask ROMs of various kinds in small numbers.

In addition, since the data writing and the data identification pattern are performed in the later steps than in the case of the first embodiment, there are many common steps irrespective of the type of data, and therefore the user It is possible to shorten the period from when the order is placed to the delivery of the finished product.

Third Embodiment Next, a mask ROM according to a third embodiment of the present invention.
And the manufacturing method thereof is demonstrated.

In this embodiment, the data identification pattern is formed on the surface of the interlayer insulating film.

FIG. 3 shows a mask RO according to this embodiment.
FIG. 8 is a cross-sectional process diagram that schematically shows the manufacturing process for M.

First, an element isolation film 302 is formed on the semiconductor wafer 301 by using, for example, the LOCOS method, and then a gate electrode 303 is formed.

Then, an interlayer insulating film 304 is formed on the entire surface of the semiconductor wafer 301 (see FIG. 3A).

Next, after forming a resist film on the entire surface of the semiconductor wafer 301, the resist film is patterned by using a normal photolithography technique to form a resist pattern 305 (see FIG. 3B). .

Similar to each of the above-described embodiments, in this patterning, a portion 305a corresponding to the channel formation region of the transistor for adjusting the threshold and a portion 305b corresponding to the data identification pattern formation region are opened.

Subsequently, using this resist pattern 305, impurity ion implantation for data writing is performed.
In this ion implantation, for example, phosphorus P is used as the impurity ions, the implantation energy is 800 keV, and the dose is 1
It may be set to × 10 ¹³ ions / cm ² . Thus, the impurity introduction region 306 can be formed on the surface of the semiconductor wafer 301 (see FIG. 3C). At the same time,
The impurity introduction region 306a is also formed by the opening 305b.

Next, using this resist pattern 305, impurity ion implantation for forming a data identification pattern is performed. In this ion implantation, for example, arsenic As is used as the impurity ions and the implantation energy is 30 keV.
The dose amount may be 1 × 10 ¹³ ions / cm ² . As a result, the impurity introduction region 3 is formed on the surface of the NSG thin film 304.
07 can be formed (see FIG. 3C). At the same time, the impurity introduction region 307a is also formed by the opening 305a.

After that, the resist pattern 305 is removed, and the interlayer insulating film 304 is wet-etched using hydrofluoric acid or the like.

Here, a large amount of As ions are implanted into the impurity introduction region 307 of the interlayer insulating film 304 (see the process). Therefore, in the data identification pattern formation region, the impurity introduction region 307 has a higher etching rate than other regions. For this reason,
When wet etching is performed, an etching step is generated between the impurity introduction region 307 and another region, whereby the data identification pattern 308 is formed (see FIG. 3D). At the same time, an etching step is formed in the impurity introduction region 307a, but this step is not used as a data identification pattern.

Thereafter, as in the conventional case, after forming the contact hole 309 and the metal wiring 310 in a desired region of the interlayer insulating film 304, the protective film 311 is deposited and the mask ROM manufacturing process is completed. (Fig. 3 (E)
reference).

Also in this embodiment, as in the case of the above-described first embodiment, when the write data of each chip in the same semiconductor wafer 301 is different, the data identification pattern is also adjusted accordingly. You can change it.

As described above, also in this embodiment, the data identification pattern 308 is the same as in the above-described embodiments.
Since the above is formed, the type of data written in the memory cell can be easily determined.

In addition, the point that the data identification pattern 308 can be formed at low cost by simply adding a simple process and that the chips having different write data can be simultaneously manufactured on the same semiconductor wafer 301 are the same as those of the second embodiment. It is similar to the form.

In addition, since the data writing and the data identification pattern are performed in the steps further than in the case of the second embodiment, the period from the user ordering to the delivery of the finished product. Can be further shortened.

Fourth Embodiment Next, a mask ROM according to a fourth embodiment of the present invention.
And the manufacturing method thereof is demonstrated.

In this embodiment, the data identification pattern is formed on the second pattern forming thin film formed on the interlayer insulating film. Further, here, an NSG thin film is used as the second pattern forming thin film.

FIG. 4 shows a mask RO according to this embodiment.
FIG. 8 is a cross-sectional process diagram that schematically shows the manufacturing process for M.

First, an element isolation film 402 and a gate electrode 403 are sequentially formed on the semiconductor wafer 401 by using, for example, the LOCOS method, and the semiconductor wafer 401 is further formed.
An interlayer insulating film 404 is formed on the entire surface of the. Then, a contact hole 405 is formed in a desired region of the interlayer insulating film 404.
And a metal wiring 406 is formed. Then, an NSG thin film 407 is formed on the entire surface of the interlayer insulating film 404 (FIG. 4).
(See (A)).

Next, after forming a resist film on the entire surface of the NSG thin film 407, the resist film is patterned by using a normal photolithography technique.
A resist pattern 408 is formed (see FIG. 4B).

Similar to each of the above-described embodiments, in this patterning, a portion 408a corresponding to the channel forming region of the transistor for adjusting the threshold and a portion 408b corresponding to the region for forming the data identification pattern are opened.

Then, using this resist pattern 408, impurity ion implantation for data writing is performed.
In this ion implantation, for example, phosphorus P is used as the impurity ions, the implantation energy is 800 keV, and the dose is 1
It may be set to × 10 ¹³ ions / cm ² . Thus, the impurity introduction region 409 can be formed on the surface of the semiconductor wafer 401 (see FIG. 4C). At the same time,
The impurity introduction region 409a is also formed by the opening 408b.

Next, using this resist pattern 408, impurity ion implantation for forming a data identification pattern is performed. In this ion implantation, for example, arsenic As is used as the impurity ions and the implantation energy is 30 keV.
The dose amount may be 1 × 10 ¹³ ions / cm ² . As a result, the impurity introduction region 4 is formed on the surface of the NSG thin film 407.
10 can be formed (see FIG. 4C). At the same time, the impurity introduction region 410a is also formed by the opening 408a.

After that, the resist pattern 408 is removed, and the NSG thin film 407 is wet-etched by using hydrofluoric acid or the like.

Here, a large amount of As ions are implanted into the impurity introduction region 410 of the NSG thin film 407 (see process). Therefore, in the NSG film 407, the impurity introduction region 410 has a higher etching rate than the other regions. Therefore, when wet etching is performed, an etching step is generated between the impurity-doped region 410 and another region, whereby the data identification pattern 411 is formed (see FIG. 4D). In addition,
At the same time, an etching step is formed in the impurity introduction region 410a, but this step is not used as a data identification pattern.

Thereafter, the protective film 412 is deposited in the same manner as in the conventional case, and the mask ROM manufacturing process is completed (see FIG. 4E).

Also in this embodiment, as in the case of the above-described first embodiment, when the write data of each chip is different in the same semiconductor wafer 401, the data identification pattern is also adjusted accordingly. You can change it.

As described above, also in this embodiment, as in the case of each of the above-described embodiments, the data identification pattern 407 is formed.
Since the above is formed, the type of data written in the memory cell can be easily determined.

In addition, the point that the data identification pattern 411 can be obtained at a low cost only by adding a simple process and that chips having different write data can be simultaneously manufactured on the same semiconductor wafer 401 are the same as those of the second embodiment. The configuration is the same as that of the third embodiment.

In addition, since the data writing and the data identification pattern are performed in a step further after that in the first to third embodiments, the finished product is delivered after the user places an order. Can be further shortened.

Fifth Embodiment Next, a mask ROM according to a fifth embodiment of the present invention.
And the manufacturing method thereof is demonstrated.

In this embodiment, except that the aspect ratio of the resist pattern is limited and the implantation angle when implanting the impurity ions into the first pattern formation region is inclined, the second embodiment described above is employed. The shape is almost the same.

FIG. 5 shows a mask RO according to this embodiment.
FIG. 8 is a cross-sectional process diagram that schematically shows the manufacturing process for M.

First, similarly to the second embodiment,
An element isolation film 502 and a gate electrode 503 are formed on a semiconductor wafer 501, and the thickness is, for example, 100 n.
m m NSG thin film 504 is formed.

Then, on the entire surface of the semiconductor wafer 501,
A resist pattern 5 in which a portion 505a corresponding to a channel forming region of a transistor for performing threshold adjustment and a portion 505b corresponding to a data identification pattern forming region are opened.
05 is formed (see FIG. 5A).

Here, in this embodiment, the film thickness of the resist pattern 505 is made larger than or equal to the size of the above-mentioned opening 505a. For example, the opening 505
When the dimension of the long side of a is 1.0 μm, the film thickness of the resist pattern 505 is set to 1.0 μm or more. On the other hand, the size of the opening 505b is set larger than the size of the opening 505a. Therefore, in this embodiment, the opening 505 is
The aspect ratio of a becomes larger than the aspect ratio of the opening 505b.

Then, using this resist pattern 505, impurity ion implantation for data writing is performed from the vertical direction.

At this time, the ion implantation conditions may be the same as those in the second embodiment. For example, phosphorus P is used as the impurity ions, the implantation energy is 400 keV, and the dose amount is 1 × 10 ¹³ ions / cm ² . do it. Thus, the impurity introduction region 506 can be formed on the surface of the semiconductor wafer 501 (see FIG. 5B).

Next, using this resist pattern 505, impurity ion implantation for forming a data identification pattern is performed at an angle shallower than vertical.

For example, this impurity ion implantation can be performed at an incident angle of 45 ° with respect to the vertical direction. In this case, since the opening 505a has a large aspect ratio, the impurity ions are irradiated only on the side surface and are not implanted into the surface of the NSG thin film 504. On the other hand, since the opening 505b has a small aspect ratio, impurity ions are implanted into the surface of the NSG film 504. Thereby, on the surface of the NSG thin film 504,
Impurity introduction region 507 can be formed (FIG. 5).
(See (C)).

The conditions of this ion implantation may be the same as those of the second embodiment. For example, arsenic As is used as the impurity ions, the implantation energy is 30 keV, and the dose amount is 1.
It may be set to × 10 ¹³ ions / cm ² .

Then, the resist pattern 505 is removed, and as in the second embodiment, the NSG thin film 504 is removed.
Wet etching is performed.

As a result, an etching step is formed in the impurity introduction region 507, and the data identification pattern 508 is obtained (see FIG. 5D).

At this time, as described above, since the impurity ions are not implanted into the NSG thin film 504 from the opening 505a, the etching step is not formed.

After that, an interlayer insulating film is formed on the entire surface of the semiconductor wafer 501 in the same manner as in the conventional case.
After forming a contact hole and a metal wiring in a desired region of the interlayer insulating film, a protective film is deposited and the mask ROM manufacturing process is completed.

As described above, according to the mask ROM of this embodiment, it is possible to prevent an etching step from being formed in a region other than the region where the data identification pattern 508 is formed.

Further, since the data identification pattern 508 is formed, the type of data written in the memory cell can be easily discriminated, the manufacturing cost is low, and the period from ordering to delivery is shortened. The point that can be done is the same as in the above-described second embodiment.

Here, the film thickness of the resist pattern 505 is set to be greater than or equal to the opening dimension of the opening 505a, and the impurity ion implantation is performed in the vertical direction by 4 times.
Although the incident angle is set to 5 °, it goes without saying that the dimensions and the incident angle can be appropriately changed. That is, as long as the condition that the aspect ratio of the opening 505a is larger than the aspect ratio of the opening 505b is satisfied, the impurity ions are only injected into the opening 505b by appropriately setting the incident angle in the impurity ion implantation for forming the data identification pattern. It can be injected, and the effect of this embodiment can be obtained.

Further, although the description has been given here as a modification of the second embodiment, the same modification can be performed in the third embodiment or the fourth embodiment, and this embodiment is also possible. The same effect as can be obtained.

[0118]

As described in detail above, according to the semiconductor memory device of the present invention, since the data identification pattern is provided, the type of write data can be easily discriminated.

Further, by forming such a data identification pattern for each chip, it becomes possible to simultaneously manufacture chips with different write data on the same semiconductor substrate.

Further, according to the method of manufacturing the semiconductor memory device of the present invention, the semiconductor memory device having the data identification pattern can be manufactured at a low cost in a simple process.

[Brief description of drawings]

FIG. 1 is a sectional process diagram that schematically shows a manufacturing process of a semiconductor memory device according to a first embodiment.

FIG. 2 is a cross-sectional process diagram schematically showing a manufacturing process of the semiconductor memory device according to the second embodiment.

FIG. 3 is a cross-sectional process diagram that schematically shows the manufacturing process of the semiconductor memory device according to the third embodiment.

FIG. 4 is a sectional process diagram that schematically shows a manufacturing process of a semiconductor memory device according to a fourth embodiment.

FIG. 5 is a cross-sectional process diagram that schematically shows the manufacturing process of the semiconductor memory device according to the fifth embodiment.

FIG. 6 is a sectional process diagram that schematically shows a manufacturing process of a conventional semiconductor memory device.

FIG. 7 is a cross-sectional process diagram that schematically shows a manufacturing process of a conventional semiconductor memory device.

FIG. 8 is a sectional process diagram that schematically shows a manufacturing process of a conventional semiconductor memory device.

[Explanation of symbols]

101 semiconductor wafer 102 element isolation film 103 sacrificial oxide film 104a Gate electrode formation region 104b Data identification pattern forming area 105, 106 impurity introduction region 107 data identification pattern 108 gate electrode 109 interlayer insulating film 110 contact holes 111 metal wiring 112 Protective film

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Claims (8)

(57) [Claims] 1. A semiconductor memory device in which data is written in a step of forming a memory cell on a surface of a semiconductor substrate, wherein a data identification pattern formed by an etching step for identifying a content of write data of the memory cell. have a,
The data identification pattern is provided on the surface of the interlayer insulating film.
A semiconductor memory device characterized by being provided. 2. A memory cell is formed on the surface of a semiconductor substrate.
In the semiconductor memory device writing data in that stage, e in order to identify the contents of the write data of the memory cell
Has a data identification pattern formed by
A semiconductor memory device, wherein the data identification pattern is provided on a surface of a second pattern forming thin film formed on an interlayer insulating film. 3. One kind of data writing pattern is formed in order to write data at the stage of forming a memory cell on the surface of a semiconductor substrate and to form a data identification pattern for identifying the content of write data of the memory cell. An impurity injection step of simultaneously or continuously performing impurity injection into a desired channel formation region of the memory cell and impurity injection into a data identification pattern formation region using a mask pattern, and etching the entire surface of the semiconductor substrate first step of forming the method of manufacturing a semiconductor memory device and a etching process for forming the etching step as the data identification pattern, the device isolation layer on a semiconductor substrate surface by
And a sacrificial oxide film on the semiconductor substrate and the device isolation film.
After forming the resist film, the resist film
The desired channel formation region of the memory cell and
Corresponds to the data identification pattern formation area of the device isolation film
A second step of opening the respective portions to be exposed, and the resist film as a mask to the surface of the semiconductor substrate.
And the impurity implantation into the element isolation region are the same.
By performing a third step sometimes performed, a fourth step of removing the resist film, and etching the entire surface of the semiconductor substrate,
Removal of the sacrificial oxide film and formation of the data identification pattern
And a sixth step of forming an element isolation film on the surface of the semiconductor substrate.
And a first pattern on the semiconductor substrate and on the device isolation film.
A seventh step of forming a thin film for forming a pattern, and forming a resist film on the first thin film for forming a pattern.
Then, in this resist film,
Channel formation region and the data identification pattern formation region
Eighth step of opening respective portions corresponding to the regions, and using the resist film as a mask, to the surface of the semiconductor substrate
Implantation of impurities into the region and the first pattern forming thin film
Impurity implantation into the substrate is performed continuously by changing the implantation depth.
9 steps, a 10th step of removing the resist film, and an etching process on the entire surface of the first pattern forming thin film.
To form the data identification pattern by
1. A method of manufacturing a semiconductor memory device , comprising: one step . In wherein said eighth step, open the resist film as the aspect ratio of the portion corresponding to the channel formation region is higher than the aspect ratio of the portion corresponding to the data identification pattern formation region, 4. The method of manufacturing a semiconductor memory device according to claim 3 , wherein in the ninth step, impurities are implanted into the first pattern forming thin film at an angle shallower than vertical. 5. A memory cell is formed on the surface of a semiconductor substrate.
Data writing at the stage of
Data identification pattern for identifying the contents of write data
Using one kind of mask pattern to form
Impurity implantation into desired channel formation region of memory cell
And simultaneously injecting impurities into the data identification pattern formation region
Or a step of continuously implanting impurities and the semiconductor substrate
Data is identified by etching the entire surface of the
Etching as a pattern Etching to form steps
A method of manufacturing a semiconductor memory device, comprising: a step of forming an element isolation film on a surface of the semiconductor substrate; and a step of forming an interlayer insulating film on the element isolation film and on the memory cell. A fourteenth step of forming a resist film on the interlayer insulating film, and then opening portions of the resist film corresponding to the desired channel formation region and the data identification pattern formation region of the memory cell, respectively. A fifteenth step of continuously implanting impurities into the surface of the semiconductor substrate and implanting impurities into the interlayer insulating film at different implantation depths using the resist film as a mask; and removing the resist film. 16th step of: and etching the entire surface of the interlayer insulating film,
17. A method of manufacturing a semiconductor memory device, comprising: a seventeenth step of forming the data identification pattern. In wherein said fourteenth step, open the resist film as the aspect ratio of the portion corresponding to the channel formation region is higher than the aspect ratio of the portion corresponding to the data identification pattern formation region, and, wherein in the fifteenth step, claim, characterized in that an impurity implanted in the interlayer insulating film at a shallow angle than the vertical 5
A method for manufacturing a semiconductor memory device according to claim 1. 7. A memory cell is formed on the surface of a semiconductor substrate.
Data writing at the stage of
Data identification pattern for identifying the contents of write data
Using one kind of mask pattern to form
Impurity implantation into desired channel formation region of memory cell
And simultaneously injecting impurities into the data identification pattern formation region
Or a step of continuously implanting impurities and the semiconductor substrate
Data is identified by etching the entire surface of the
Etching as a pattern Etching to form steps
18. A method of manufacturing a semiconductor memory device, comprising the steps of: forming an element isolation film on a surface of the semiconductor substrate; forming an interlayer insulating film and a second pattern on the element isolation film and the memory cell. Nineteenth step of forming an application thin film, and after forming a resist film on the second pattern forming thin film, a desired channel formation region of the memory cell and a data identification pattern formation region of the resist film are formed. A twentieth step of opening corresponding portions, an impurity implantation into a region on the semiconductor substrate surface and an impurity implantation into the second thin film for pattern formation using the resist film as a mask, and adjusting an implantation depth. 21st step which is continuously performed by changing, 22nd step of removing the resist film, and etching of the entire surface of the second pattern forming thin film More, the second to form the data identification pattern
A method of manufacturing a semiconductor memory device, comprising: 3 steps. In wherein said twentieth step, open the resist film as the aspect ratio of the portion corresponding to the channel formation region is higher than the aspect ratio of the portion corresponding to the data identification pattern formation region, 8. The method of manufacturing a semiconductor memory device according to claim 7 , wherein in the 21st step, impurities are implanted into the second pattern forming thin film at an angle shallower than vertical.