JP3394308B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is a charge coupled device to transfer the signal charges (hereinafter, CCD) Ri engaged <br/> the solid-state imaging equipment using, in particular, transfer and high-sensitivity high-speed multi-stage, low dark current, high-definition solid-state imaging device and the low smear noise is required, internal drive circuit, image signal processing circuit, a / D conversion circuit and the like, in a suitable CCD structure in the solid-state imaging device provided with various circuits other than the CCD <br/> related.

[0002]

2. Description of the Related Art As the performance of a solid-state image pickup device is improved, increasing the frequency of a charge transfer driving pulse has become important as a method for improving the performance. For example, Frame Interline Transfer
In an ansfer (hereinafter referred to as FIT) type CCD solid-state imaging device, smear noise is reduced by about 30 d by increasing the driving frequency of the vertical CCD from about 30 kHz to 1 MHz.
B can be reduced. In order to drive the transfer electrode at such a high frequency, it is usually necessary to sufficiently lower the electric resistance of the transfer electrode formed of polycrystalline silicon. A technique for forming an Al wiring as a shunt wiring is disclosed in, for example, Japanese Patent Laid-Open No. 56-87379 (Japanese Patent Publication No. 1-30306).

However, in this conventional example, since the electrical connection between the Al shunt wiring and the transfer electrode is made on the transfer channel region, Al penetrates into the polycrystalline silicon which is the material forming the transfer electrode, As a result, there is a problem that the work function of the transfer electrode changes and the transfer efficiency deteriorates. A conventional example of a solid-state image pickup device devised to solve this problem is disclosed in Japanese Patent Laid-Open No. 3-165572, and will be described below as an example.

FIG. 2 shows a sectional view of a conventional example of a solid-state image pickup device. 2A and 2B, a first insulating film 201 is formed on the surface of the semiconductor substrate 200 by oxidation, and a transfer electrode 202 made of polycrystalline silicon of the first layer is formed on the first insulating film 201.
However, the transfer electrode 2 made of polycrystalline silicon of the first layer
A second transfer electrode 203 made of polycrystalline silicon is formed through an insulating film 206 formed by oxidizing 02. Reference numeral 207 is an insulating film formed by oxidizing the transfer electrode 203 made of polycrystalline silicon of the second layer, and 204 is a polycrystalline silicon film of the third layer. Here, the first-layer polycrystalline silicon transfer electrode 202 and the third-layer polycrystalline silicon film 204 are electrically connected by a first contact hole 210. Further, FIG. 2 (a)
Then, the Al wiring film 2 is formed on the third-layer polycrystalline silicon film 204 with the insulating film 208 made of, for example, PSG interposed therebetween.
05 is formed, and the third-layer polycrystalline silicon film 2 is formed.
04 and the Al wiring film 205 form the second contact hole 2
2B, the insulating film 208 made of, for example, PSG is omitted in FIG.
An Al wiring film 205 is formed immediately above the third-layer polycrystalline silicon film 204 so that the whole is electrically connected. In FIG. 2, the contact hole between the Al wiring film 205 and the transfer electrode 203 made of polycrystalline silicon of the second layer is omitted.

[0005]

In the first conventional example shown in FIG. 2 (a), the transfer caused by arranging the connection portion between the transfer electrode made of polycrystalline silicon and the Al wiring on the transfer channel region. The deterioration of efficiency is caused by the transfer electrode 202 made of polycrystalline silicon of the first layer, the transfer electrode 203 made of polycrystalline silicon of the second layer, and the Al wiring film 20.
5, the third-layer polycrystalline silicon film 204 is provided as a connection layer via the insulating film 208, and the Al wiring film 205 is directly connected to the first-layer polycrystalline silicon transfer electrode 202.
This is prevented by not contacting with. Therefore, the third-layer polycrystalline silicon film 20 serving as the connection layer is formed.
4 and the third layer polycrystalline silicon film 20
Due to the patterning of the second contact hole 209 for connection between the Al 4 and the Al wiring film 205, there arises a problem that the number of masks for two sheets increases and the number of processing steps associated therewith increases.

In the second conventional example shown in FIG. 2B, the Al wiring film 205 is formed immediately above the third-layer polycrystalline silicon film 204 without an inter-layer insulating film. Therefore, the number of masks does not increase, but on the other hand, as described in Japanese Patent Laid-Open No. 3-165572, which discloses this conventional example, the fluctuation of the work function and the fluctuation of the threshold voltage are suppressed. There is a problem that the prevention effect is weaker than that of the first conventional example.

An object of the present invention is to prevent the change in the work function of the transfer electrode itself or to suppress the change in the work function of the transfer electrode while suppressing the increase in the number of masks to a minimum and preventing the process from becoming complicated. Is to prevent the influence of the above from reaching the transfer channel area.

[0008]

The above objects are (1) at least in a region where the wiring is in contact, the uppermost layer of the transfer electrode is formed of a conductive diffusion / reaction preventing film, or (2)
At least in a region where the wiring contacts, a layer made of a conductive diffusion / reaction preventing film is provided between the uppermost portion of the transfer electrode and the gate insulating film, or (3) at least a region where the wiring contacts, A diffusion / reaction prevention layer is provided between the top of the transfer electrode and the gate insulation film to form an insulating diffusion / reaction prevention layer and to electrically connect the layers above and below the diffusion / reaction prevention film. This is achieved by partially removing the film or connecting the layers above and below the diffusion / reaction preventing film in a self-aligned manner at the side wall of the transfer electrode.

[0009]

By using a conductive diffusion / reaction preventing film as the uppermost layer of the transfer electrode with which the wiring is in contact, diffusion / reaction between the wiring and the transfer electrode material is prevented, resulting in a threshold voltage. It is possible to prevent the transfer efficiency from deteriorating due to the change of. In addition, since this conductive diffusion / reaction preventing film is a part of the material forming the transfer electrodes and can be processed by using the mask for patterning the transfer electrodes, the number of masks does not increase. In addition, conductive diffusion and
Even when the reaction preventive film is arranged, the number of masks required for patterning for disposing the conductive diffusion / reaction preventive film only in that region is increased.

Further, by providing a conductive diffusion / reaction prevention film or an insulative diffusion / reaction prevention film between the portion in contact with the wiring and the gate insulating film, at least the diffusion / reaction prevention film is formed.
The transfer electrode material under the reaction preventive film is
The reaction with the wiring does not occur, so that the deterioration of the transfer efficiency due to the change of the threshold voltage can be prevented. Moreover, since this conductive diffusion / reaction preventing film can be processed by using a mask for patterning the transfer electrodes as a part of the material forming the transfer electrodes, the number of masks does not increase. Furthermore, even if the conductive diffusion / reaction prevention film is placed only in the area where the wiring contacts, the number of masks required for patterning to place the conductive diffusion / reaction prevention film only in that area is increased. Mu. On the other hand, in the case of an insulating diffusion / reaction prevention film, if part of the diffusion / reaction prevention film is to be removed in order to connect the layers above and below the diffusion / reaction prevention film, a mask for patterning this removal area The number of masks does not increase if the number of masks is increased by one, and if the upper and lower layers are connected in a self-aligned manner on the sidewalls of the transfer electrodes.

As described above, by adopting the three means, the change itself of the work function of the transfer electrode is prevented while suppressing an increase in the number of masks to prevent the process from becoming complicated, or It is possible to prevent the influence of the change in the work function of the transfer electrode from affecting the transfer channel region.

[0012]

【Example】

<Embodiment 1> A sectional view of the first embodiment of the present invention is shown in FIG. FIG. 1 shows a superposed electrode structure in which the uppermost layer of the transfer electrode is formed of a conductive diffusion / reaction prevention film,
FIG. 6 is a cross-sectional view of an example in which a contact between a wiring and a transfer electrode is arranged on a transfer channel region.

A description will be given below with reference to FIG. A second conductivity type transfer channel diffusion layer 190 (eg, an n type diffusion layer formed by diffusing arsenic) is formed in the first conductivity type semiconductor substrate 100 (eg, p type silicon substrate). An insulating film 101 serving as a gate insulating film is formed thereon, for example, a silicon oxide film, and a plurality of transfer electrodes for driving the CCD are arranged via the insulating film 101. The transfer electrode is a first-layer transfer electrode composed of, for example, a first electrode material film 102 made of polycrystalline silicon and a first conductive diffusion / reaction prevention film 120 made of W, for example. And a second electrode material film 103 made of the same material and a second conductive diffusion / reaction prevention film 12
1 and the transfer electrode of the second layer, and the transfer electrode of the second layer is arranged so as to overlap the transfer electrode of the first layer. A first interlayer insulating film 106 made of, for example, a silicon oxide film is provided between the first-layer transfer electrode and the second-layer transfer electrode, and the first-layer and second-layer transfer electrodes are made of, for example, Al. A second interlayer insulating film 104 made of, for example, a silicon oxide film is formed between the wiring 105 and the wiring 105.

Further, the transfer electrode of the first layer or the second layer and the wiring are connected by a contact hole formed by dry etching or wet etching, and this contact hole is formed on the transfer channel diffusion layer. It is located in. However, in FIG. 1, for simplification, the connection region between the transfer electrode and the wiring is shown only for the central transfer electrode in FIG. 1 (this is the same in the subsequent figures).

Specifically, the wiring 105 is the contact hole 1 formed on the transfer channel diffusion layer 190.
It is connected to the transfer electrode of the first layer in the center of FIG. The first conductive diffusion / reaction preventing film 1 is formed on the portion where the wiring 105 contacts the first-layer transfer electrode.
20 are formed. In this embodiment, by providing the first conductive diffusion / reaction prevention film 120 on the uppermost layer of the transfer electrode, the diffusion / reaction between the material forming the wiring 105 and the first electrode material film 102 is performed. Is prevented and the work function of the first electrode material film 102 does not change.

This effect works in the same manner not only in the case where the transfer electrode of the first layer in the center of FIG. 1 but also the other transfer electrodes in FIG. The same applies to the embodiment of). Therefore, even if the contact hole 110 is arranged directly above the transfer channel diffusion layer 190, the threshold voltage of the CCD does not change and the transfer efficiency does not deteriorate. Further, in forming the transfer electrode structure as shown in FIG. 1, the first electrode material film 102 and the first conductive diffusion / reaction prevention film 120, and the second electrode material film 103 and the second electrode material film 103 Conductive diffusion / reaction prevention film 1
Since 21 can be simultaneously processed by masks for patterning the transfer electrodes of the first layer and the transfer electrodes of the second layer, respectively, the number of masks does not increase.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer without increasing the number of process steps and without deteriorating the transfer efficiency. can do.

In addition to the above materials, an Al alloy material such as Al-Si is used for the wiring 105, and doped silicon or amorphous silicon is used for the first and second electrode material films 102 and 103. It is possible. These are materials that are frequently used in a normal silicon process, and Al and Al alloy-based materials have low resistance as wirings, and thus are suitable materials for driving a CCD at high speed. When these materials are used, Ti, Mo or W, as well as W, can be used as a conductive diffusion / reaction preventing film.
Materials often used in the silicon process such as Ti and Mo silicides or composite films thereof can be used.

Further, when a high melting point metal material such as W is used for the wiring 105 and a high temperature heat treatment is performed while directly contacting the electrode material film made of polycrystalline silicon, doped silicon or amorphous silicon, the silicidation reaction occurs. In this case, a silicide of W, Ti, Mo can be used as a conductive diffusion / reaction preventing film. On the other hand, a polycide electrode structure is known as an electrode structure in which a silicide material is stacked on a silicon material. Since the purpose of the polycide electrode is to reduce the resistance of the electrode and prevent signal propagation delay, it is desirable that the film thickness of the silicide material that is responsible for lowering the resistance of the electrode is as thick and low as possible. In the example structure, the wiring 105 plays a role of lowering the resistance, and therefore the conductive diffusion / reaction preventing films 120 and 121 in the uppermost layer of the electrode are necessary and sufficient in thickness to prevent the diffusion / reaction (eg, About 50
(about nm), and it does not need to have a particularly low resistance as compared with the first and second electrode material films 102 and 103.

As a structure for preventing diffusion / reaction between the wiring and the electrode material film, a structure in which a barrier metal is laid under the wiring is known. This structure prevents the diffusion and reaction between the wiring material and the electrode material or the silicon substrate by depositing the barrier metal and the wiring material in this order after forming the contact hole and patterning them with the same wiring mask at the same time. However, for example, TiN is used as the barrier metal. In this structure, when the contact hole becomes smaller, the step coverage when the barrier metal is deposited deteriorates, so that the ability as a diffusion / reaction prevention film decreases, and in order to compensate the deterioration of the step coverage, If the metal film thickness is increased, peeling may occur due to the internal stress of the barrier metal. On the other hand, in the structure of this embodiment, since the conductive diffusion / reaction prevention film is deposited on the substantially flat electrode material film, the step coverage is not deteriorated and even for a small contact hole. diffusion·
It effectively functions as a reaction prevention film. In addition, therefore, it is not necessary to increase the film thickness to compensate for the step coverage deterioration.

<Embodiment 2> Next, a sectional view of a second embodiment of the present invention is shown in FIG. FIG. 3 is a cross-sectional view of an embodiment having a superposed electrode structure in which a conductive diffusion / reaction preventing film is sandwiched in the middle portion of the transfer electrode and a contact between the wiring and the transfer electrode is arranged on the transfer channel region. .

The structure of this embodiment basically conforms to the structure of the first embodiment shown in FIG.
The difference is that the reaction prevention film is sandwiched not as the uppermost layer of the transfer electrode but as an intermediate layer. More specifically, referring to FIG. 3, the first-layer transfer electrode includes a first electrode material film 302 made of, for example, polycrystalline silicon and a first conductive diffusion / reaction prevention film 320 made of, for example, W. For example, a second electrode material film 312 made of polycrystalline silicon is laminated in this order from the bottom, and this is the same for the transfer electrode of the second layer, for example, the same as the transfer electrode of the first layer. It is composed of a third electrode material film 303 made of a material, a second conductive diffusion / reaction prevention film 321 and a fourth electrode material film 313.

Reference numeral 300 denotes a first conductivity type semiconductor substrate (for example, p type semiconductor substrate), and 390 denotes a second conductivity type transfer channel diffusion layer (for example, n type diffusion layer formed by diffusing arsenic). Reference numeral 301 denotes an insulating film made of, for example, a silicon oxide film, 306 and 304 denote first and second interlayer insulating films made of, for example, a silicon oxide film, 305 denotes a wiring made of, for example, Al, and the wiring 305 is a dry wiring. It is connected to the transfer electrode of the first layer in the center of FIG. 3 on the transfer channel diffusion layer 390 through the contact hole 310 formed by etching or wet etching. A first conductive diffusion / reaction preventing film 320 is sandwiched between the transfer electrodes of the first layer and sandwiched in the middle of the transfer electrodes.

In this embodiment, the material for forming the wiring 305 and the first electrode material film 30 are provided by providing the first conductive diffusion / reaction preventing film 320 on the intermediate layer of the transfer electrode.
The first electrode material film 30 is prevented from diffusing and reacting with the second electrode material film 30.
The work function change of 2 does not occur. Therefore, even if the contact hole 310 is arranged immediately above the transfer channel diffusion layer 390, the threshold voltage of the CCD does not change and the transfer efficiency does not deteriorate. Further, as compared with the first embodiment, since the conductive diffusion / reaction preventing film is sandwiched as the intermediate layer of the transfer electrode, the conductive diffusion / reaction during the process is prevented.
Since the exposed area of the reaction prevention film is small, it is possible to suppress the invasion of the element forming the conductive diffusion / reaction prevention film into the silicon substrate. Further, in forming the transfer electrode structure as shown in FIG. 3, the first electrode material film 302, the first conductive diffusion / reaction prevention film 320, the second electrode material film 312, and the third electrode material film 312 are formed. Electrode material film 303, second conductive diffusion / reaction prevention film 321 and fourth electrode material film 3
Since 13 can be simultaneously processed by the masks for patterning the transfer electrodes of the first layer and the transfer electrodes of the second layer, respectively, the number of masks does not increase. As described above, by adopting the structure of this embodiment, it is possible to suppress the increase in the number of process steps and form the contact between the transfer electrode and the wiring on the transfer channel diffusion layer without causing the deterioration of the transfer efficiency. it can.

As in the first embodiment, the wiring 305 is made of Al alloy material other than Al, and the first to fourth electrode material films 302, 312, 303, 313 are made of polycrystalline silicon. Alternatively, it is possible to use doped silicon or amorphous silicon, in which case
First and second conductive diffusion / reaction prevention films 320, 3
21 includes Ti, Mo or W, Ti, M in addition to W
O silicide or a composite film thereof can be used.

<Third Embodiment> Next, FIG. 4 shows a sectional view of a third embodiment of the present invention. FIG. 4 is a cross-sectional view of an embodiment having a superposed electrode structure in which an insulating diffusion / reaction preventing film is sandwiched in the middle of the transfer electrode and a contact between the wiring and the transfer electrode is arranged on the transfer channel region. .

The structure of this embodiment basically conforms to the structure of the second embodiment shown in FIG. 3, but the diffusion / reaction preventing film sandwiched between transfer electrodes is insulative. The third embodiment is different from the second embodiment in that a connection portion is provided for electrically connecting the electrode material films above and below the insulating prevention film.

More specifically, referring to FIG. 4, the transfer electrode of the first layer is composed of a first electrode material film 402 made of, for example, polycrystalline silicon and a first insulating diffusion / reaction made of, for example, a silicon oxide film. And a second electrode material film 412 made of, for example, polycrystalline silicon are laminated in this order from the bottom, and the transfer electrode of the second layer is also made of, for example, the first layer. A third electrode material film 403 made of the same material as the transfer electrode and a second insulating diffusion / reaction prevention film 4
27 and a fourth electrode material film 413.
Then, the first electrode material film 402 and the second electrode material film 4
In order to electrically connect 12 and the third electrode material film 403 and the fourth electrode material film 413, the first and second insulating diffusion / reaction prevention films 425 and 427 have connecting portions. Four
26 and 428 are formed on the first and second insulating diffusion / reaction preventing films 425 and 427 by dry etching or wet etching of a silicon oxide film, for example.

Reference numeral 400 denotes a first conductivity type semiconductor substrate (for example, p type semiconductor substrate), 490 denotes a second conductivity type transfer channel diffusion layer (for example, n type diffusion layer formed by diffusing arsenic), Reference numeral 401 denotes an insulating film made of, for example, a silicon oxide film, 406 and 404 denote first and second interlayer insulating films made of, for example, a silicon oxide film, 405 denotes a wiring made of Al, and the wiring 405 is a dry wiring. It is connected to the transfer electrode of the first layer in the center of FIG. 4 on the transfer channel diffusion layer 490 through the contact hole 410 formed by etching or wet etching.
A first insulating diffusion / reaction prevention film 425 is formed under the portion where the wiring 405 contacts the first-layer transfer electrode.
Is sandwiched between the transfer electrodes. Further, the connection portion 426 is arranged so as not to overlap the contact hole 410.

In this embodiment, a first insulating diffusion / reaction preventing film 425 is provided on the intermediate layer of the transfer electrode, and the connecting portion 426 is arranged so as to be offset from immediately below the contact hole 410. Therefore, the diffusion / reaction between the material forming the wiring 405 and the first electrode material film 402 is prevented, and the work function of the first electrode material film 402 does not change.
Therefore, even if the contact hole 410 is arranged directly above the transfer channel diffusion layer 490, the threshold voltage of the CCD does not change and the transfer efficiency does not deteriorate. Also, as in a normal silicon process, the wiring 405 is made of Al or an Al alloy-based material, and the first to fourth electrode material films 402, 4 are formed.
When polycrystalline silicon, doped silicon, or amorphous silicon is used for 12, 403, 413, the first and second insulating diffusion / reaction prevention films 425, 42
For 7, a silicon oxide film, a silicon nitride film, or a composite film thereof can be used. These are materials that have a sufficient track record in the silicon process and do not increase the intrusion of contaminant impurities into the silicon substrate.

Further, in forming the transfer electrode structure as shown in FIG. 4, the first electrode material film 402, the first insulating diffusion / reaction prevention film 425 and the second electrode material film 4 are formed.
12, the third electrode material film 403, the second insulating diffusion / reaction prevention film 427, and the fourth electrode material film 413.
Can be simultaneously processed by the masks for patterning the transfer electrodes of the first layer and the transfer electrodes of the second layer, respectively, so that the number of masks can be increased by only one for patterning the connection portions 426 and 428. The number of mask increases is smaller than that in the conventional example shown in FIG.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer while suppressing the increase in the number of process steps and without causing the deterioration of the transfer efficiency. can do.

<Embodiment 4> Next, a sectional view of a fourth embodiment of the present invention is shown in FIG. FIG. 5 shows a superposed electrode structure in which the electrical connection between the electrode material films above and below the insulating diffusion / reaction prevention film sandwiched in the middle of the transfer electrode is self-aligned by the spacer formed on the transfer electrode sidewall. FIG. 3 is a cross-sectional view of an example in which the contact between the wiring and the transfer electrode is arranged on the transfer channel region, in addition to the above.

The structure of this embodiment is basically similar to the structure of the third embodiment shown in FIG.
Rather than making holes in this protective film to electrically connect the electrode material films above and below the reaction preventive film, conductive spacers formed on the sidewalls of the transfer electrodes connect in a self-aligned manner without using a mask. Is different from the third embodiment.

More specifically, referring to FIG. 5, a first electrode material film 502 and a second electrode material film 512, and a third electrode material film 503 and a fourth electrode material film 513 made of, for example, polycrystalline silicon. In order to electrically connect the transfer electrodes to the first and second transfer electrodes, conductive spacers 53 are formed on the side walls of the transfer electrodes.
0,531 is, for example, polycrystalline silicon having a thickness of 100 nm-5.
It is formed without using a mask by performing anisotropic etching on silicon after depositing and doping by low pressure CVD to about 00 nm.

Reference numeral 500 denotes a first conductivity type semiconductor substrate (eg, p type semiconductor substrate), and 590 denotes a second conductivity type transfer channel diffusion layer (eg, n type diffusion layer formed by diffusing arsenic). Reference numeral 501 is an insulating film made of, for example, a silicon oxide film, 520 and 521 are first and second insulating diffusion / reaction preventing films made of, for example, a silicon oxide film, and 506 and 504 are, for example, silicon oxide films. The first and second interlayer insulating films made of a film, 505 represents a wiring made of, for example, Al, and the wiring 505 is formed in the transfer channel diffusion layer 590 through the contact hole 510 formed by dry etching or wet etching. It is connected to the transfer electrode of the first layer in the center of FIG. 5 above. A first insulating diffusion / reaction preventing film 520 is sandwiched between intermediate portions of the transfer electrodes below the portion where the wiring 505 contacts the first-layer transfer electrodes.

In the present embodiment, as in the case of the third embodiment, the contact hole 510 is arranged immediately above the transfer channel diffusion layer 590 by the action of the insulating diffusion / reaction preventing films 520 and 521. Also, the threshold voltage of the CCD does not change, and the transfer efficiency does not deteriorate. Then, as in a normal silicon process, the wiring 505 is made of Al or A.
The first to fourth electrode material films 50 are made of an alloy material.
When polycrystalline silicon, doped silicon, or amorphous silicon is used for 2, 512, 503, and 513, the first and second insulating diffusion / reaction preventing films 52 are provided.
As in the third embodiment, a silicon oxide film, a silicon nitride film, or a composite film thereof can be used for 0,521.

In forming the transfer electrode structure as shown in FIG. 5, the first electrode material film 502, the first insulating diffusion / reaction prevention film 520, and the second electrode material film 51 are formed.
2, and the third electrode material film 503, the second insulating diffusion / reaction prevention film 521, and the fourth electrode material film 513,
The transfer electrodes of the first layer and the transfer electrodes of the second layer can be simultaneously processed by masks for patterning, respectively. Further, the conductive spacers 530 and 531 for connecting the electrode material films above and below the diffusion / reaction preventing film do not require a mask for forming them. Therefore, the required number of masks does not increase, and the number of masks can be reduced by one as compared with the third embodiment.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer without increasing the number of process steps and without deteriorating the transfer efficiency. can do.

<Embodiment 5> Next, sectional views of a fifth embodiment of the present invention are shown in FIGS. 6 to 9 are
FIG. 4 is a cross-sectional view of an example having a single-layer electrode structure in which a diffusion / reaction preventing film is provided on a transfer electrode and a contact between a wiring and a transfer electrode is arranged on a transfer channel region.

The structure of FIGS. 6 to 9 of this embodiment basically conforms to the structure of the first embodiment shown in FIG. 1 to the fourth embodiment shown in FIG. 5, respectively. The difference is that the transfer electrode has a single-layer electrode structure formed by cutting and separating a single layer.

The following is a description with reference to the drawings. The plurality of transfer electrodes that drive the CCD are formed by stacking an electrode material film 602 made of, for example, polycrystalline silicon and a conductive diffusion / reaction prevention film 620 made of, for example, W in this order. The uppermost layer is a conductive diffusion / reaction prevention film. Moreover, since all the transfer electrodes are formed by cutting and separating the single electrode layer composed of these two films, the transfer electrodes are arranged with a gap therebetween, and the transfer electrodes do not overlap each other.

FIG. 7 shows an example in which a conductive diffusion / reaction preventing film 720 is sandwiched between intermediate layers of a single-layer transfer electrode, and FIG. 8 shows an intermediate layer of a single-layer transfer electrode. This is an example in which an insulating diffusion / reaction prevention film 825 is sandwiched between the electrodes and the electrode material films above and below the diffusion / reaction prevention film 825 are electrically connected to each other by a connecting portion 826 formed by wet or dry etching. In FIG. 9, an insulating diffusion / reaction prevention film 925 is sandwiched in the intermediate layer of the transfer electrode having a single layer structure, and a conductive spacer 916 is formed instead of forming a hole in the diffusion / reaction prevention film 925. Is an example in which the upper and lower electrode material films are electrically connected to each other by forming on the side wall of the transfer electrode in a self-aligned manner without a mask.

Reference numerals 600, 700, 800 and 900 denote semiconductor substrates of the first conductivity type (for example, p-type semiconductor substrate),
Reference numerals 690, 790, 890, and 990 denote transfer channel diffusion layers of the second conductivity type (for example, an n-type diffusion layer formed by diffusing arsenic), and 601, 701, 801, and 901 denote insulating films made of, for example, a silicon oxide film. , 702, 802, 902
Is, for example, a first electrode material film made of polycrystalline silicon,
Numerals 712, 812, 912 are second electrode material films made of, for example, polycrystalline silicon, 720 is a conductive diffusion / reaction prevention film made of W, and 825, 925 are insulating films made of, for example, silicon oxide film. A diffusion / reaction prevention film
Reference numerals 604, 704, 804, and 904 denote interlayer insulating films made of, for example, a silicon oxide film, and 605, 705, 805, 9
Reference numeral 05 represents a wiring made of Al, for example, and wiring 605,
Reference numerals 705, 805, 905 denote contact holes 610 formed by dry etching or wet etching, respectively.
It is connected to the transfer electrode at the center of each figure on the transfer channel diffusion layer via 710, 810 and 910. Further, the connection portion 826 is arranged so as not to overlap the contact hole 810. Further, reference numeral 916 is a conductive spacer formed by, for example, depositing and doping polycrystalline silicon by low pressure CVD to about 100 nm to 500 nm, and then performing anisotropic etching on silicon.

In this embodiment, by providing a diffusion / reaction prevention film on the transfer electrode, the material forming the wiring and the electrode below the diffusion / reaction prevention film are formed as in the first to fourth embodiments. Diffusion and reaction with the material film are prevented. Therefore,
Even if the contact hole is arranged right above the transfer channel diffusion layer, the threshold voltage of the CCD does not change and the transfer efficiency does not deteriorate.

Further, when forming the transfer electrode structure as shown in FIGS. 6 and 7, the electrode material film and the diffusion / reaction preventing film can be processed simultaneously by the mask for patterning the transfer electrode, so that the number of masks is reduced. Does not increase. In FIG. 8, one mask is required to process the connecting portion 826, but even if this is added, the increase in the number of masks is one less than in the conventional example shown in FIG. In FIG. 9, since a mask is not necessary for forming the conductive spacers for connecting the electrode material layers above and below the insulating diffusion / reaction prevention film, the number of masks does not increase.

Further, in this embodiment, since the transfer electrodes are formed by cutting and separating a single layer, there is no overlap between the transfer electrodes. Therefore, it is possible to prevent short circuit between electrodes at the overlapping portion between the transfer electrodes and short circuit between electrodes due to etching residue at the step portion due to the lower transfer electrodes when processing the transfer electrodes of the second and subsequent layers. Further, since there is no step due to the overlap of the transfer electrodes, it is easy to flatten the base of the wiring, and therefore, it is possible to prevent both the planarization process from becoming complicated and the wiring from breaking.

Further, in the embodiment shown in FIG. 9, since the conductive spacers 916 for connecting the upper and lower electrode material films can reduce the gap between the transfer electrodes,
It is possible to realize a transfer electrode interval smaller than the minimum processing size in the process used and further prevent deterioration of transfer efficiency.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer while suppressing the increase in the number of process steps and without causing the deterioration of the transfer efficiency. can do.

As in the first embodiment, the wiring A
It is also possible to use an l-alloy-based material, and doped silicon or amorphous silicon as the electrode material film. In this case, in addition to W, Ti, Mo or W is used as the conductive diffusion / reaction prevention film. , Ti, Mo silicide, or a composite film thereof can be used as the insulating diffusion / reaction preventing film in addition to the silicon oxide film, a silicon nitride film or a composite film thereof.

<Embodiment 6> Next, sectional views of a sixth embodiment of the present invention are shown in FIGS. 10 to 12 show a single-layer electrode structure, in which the contact between the wiring and the transfer electrode is arranged on the transfer channel region, and the diffusion / reaction preventing film is provided only in the region where the wiring contacts the transfer electrode. It is sectional drawing of an Example.

The structure of each drawing of this embodiment is basically the same as that shown in FIG. 6 of the fifth embodiment, FIG. 11 is the structure of FIG. 7, and FIG. 12 is the structure of FIG. The structures are the same, but the difference is that the diffusion / reaction preventing film is provided only in the region where the wiring and the transfer electrode are in contact with each other or under the region.

The following is a description with reference to the drawings. In FIG. 10, the transfer electrode is an electrode material film 100 made of, for example, polycrystalline silicon.
Conductive diffusion / reaction prevention film 10 made of 2 and W, for example
And a wiring 10 made of, for example, Al.
A conductive diffusion / reaction prevention film 1020 is formed only in the portion where 05 contacts the transfer electrode. Therefore, in the other transfer electrodes which are not in contact with the wiring 1005 in FIG. 10, a diffusion / reaction preventing film is not provided on the upper layer of the electrode material film 1002.

In FIG. 11, a conductive diffusion / reaction prevention film 1120 is sandwiched between the intermediate layers of the transfer electrodes, and the diffusion / reaction prevention film 1120 is formed only under the region where the wiring contacts the transfer electrodes. Here is an example.

FIG. 12 shows an example in which an insulating diffusion / reaction prevention film 1220 is sandwiched between intermediate layers of transfer electrodes, and the diffusion / reaction prevention film 1220 is formed only under the region where the wiring contacts the transfer electrodes. Is. Further, in FIG. 12, the electrical connection of the electrode material films above and below the diffusion / reaction prevention film 1220 is
This is automatically realized by limiting the insulating diffusion / reaction preventing film 1220 to below the region where the wiring contacts.

In addition, 1000, 1100 and 1200 are semiconductor substrates of the first conductivity type (for example, p-type semiconductor substrate).
001, 1101, 1201 are insulating films made of, for example, a silicon oxide film, 1090, 1190, 1290 are transfer channel diffusion layers of the second conductivity type (for example, n-type diffusion layers formed by diffusing arsenic) 1102, 1202. Is, for example, a first electrode material film made of polycrystalline silicon,
Reference numeral 1212 denotes a second electrode material film made of, for example, polycrystalline silicon, 1120 denotes a conductive diffusion / reaction prevention film made of, for example, W, and 1220 an insulating diffusion / reaction prevention film made of, for example, a silicon oxide film. To 1004,110
4, 1204 are interlayer insulating films made of, for example, a silicon oxide film, 1005, 1105, 1205 are wirings made of, for example, Al, and 1010, 1110, 1210 are contact holes formed by dry etching or wet etching, for example, on the silicon oxide film. Indicates.

In the present embodiment, similarly to the fifth embodiment, the threshold voltage of the CCD does not change and the transfer efficiency does not deteriorate even if the contact hole is arranged immediately above the transfer channel diffusion layer. Further, in forming the transfer electrode structure as in this embodiment, the number of masks is increased by only one for patterning the diffusion / reaction preventing film. This is less than in the conventional example shown in FIG.

Further, in FIGS. 10 and 11, since the conductive diffusion / reaction preventing film is provided only in the region in contact with the wiring or under the region, the conductive diffusion / reaction is prevented during the process. The exposed area of the prevention film is small, and it is possible to suppress the intrusion of the element forming the conductive diffusion / reaction prevention film into the silicon substrate.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer while suppressing the increase in the number of process steps and without causing the deterioration of the transfer efficiency. can do.

As in the fifth embodiment, the wiring A
1 or Al alloy-based material, and when polycrystalline silicon, doped silicon, or amorphous silicon is used as the electrode material film, W, Ti, Mo, or their silicides or those are used as the conductive diffusion / reaction preventing film. And a silicon oxide film, a silicon nitride film, or a composite film thereof can be used as the insulating diffusion / reaction preventing film.

<Embodiment 7> Next, FIG. 13 shows a sectional view of a seventh embodiment of the present invention. FIG. 13 shows a single-layer electrode structure,
After forming the uppermost layer of the transfer electrode with a conductive diffusion / reaction prevention film and arranging the contact between the wiring and the transfer electrode on the transfer channel region, and after covering the conductive diffusion / reaction prevention film with an insulating film It is sectional drawing of the Example which patterned the transfer electrode.

The structure of this embodiment is basically similar to the structure shown in FIG. 6 of the fifth embodiment, except that an insulating film is formed on the conductive diffusion / reaction preventing film of the transfer electrode uppermost layer. The points provided are different.

Referring to FIG. 13, the transfer electrode is composed of, for example, an electrode material film 1302 made of polycrystalline silicon and W, for example.
And a conductive diffusion / reaction prevention film 1320 made of, for example, are laminated in this order from the bottom, and a second insulating film 1315 made of, for example, a silicon oxide film is further laminated thereon. Is patterned with a mask pattern for forming transfer electrodes.

In this embodiment, by providing a conductive diffusion / reaction preventing film 1320 on the uppermost layer of the transfer electrode, the transfer channel diffusion layer 139 is formed as in the fifth embodiment shown in FIG.
Even if the contact hole 1310 is arranged directly above 0, the transfer efficiency does not deteriorate.

Further, in this embodiment, since the second insulating film 1315 is provided on the conductive diffusion / reaction prevention film 1320, the exposed area of the conductive diffusion / reaction prevention film 1320 is small and the conductivity is reduced. It is possible to suppress the invasion of the element forming the film for preventing the diffusion / reaction of the property into the silicon substrate. Furthermore, since the electrode material film 1302, the conductive diffusion / reaction prevention film 1320, and the second insulating film can be processed simultaneously by the mask for patterning the transfer electrode, the number of masks does not increase.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer without suppressing the increase in the number of process steps and causing the deterioration of the transfer efficiency. can do.

The structure of this embodiment is such that, as shown in FIGS. 7 to 9 of the fifth embodiment, a conductive or insulating diffusion / reaction preventing film is sandwiched between transfer electrodes, or It goes without saying that the structure in which the diffusion / reaction preventing film is provided only in the region where the wiring contacts the transfer electrode as in the sixth embodiment shown in FIGS. 10 to 12 can be applied.

<Embodiment 8> Next, FIG. 14 shows a sectional view of an eighth embodiment of the present invention. FIG. 14 shows a single-layer electrode structure,
After forming the uppermost layer of the transfer electrode with a conductive diffusion / reaction prevention film and arranging the contact between the wiring and the transfer electrode on the transfer channel region, and after covering the conductive diffusion / reaction prevention film with an insulating film It is sectional drawing of the Example which patterned the transfer electrode and provided the electrically conductive spacer in the self-alignment on the transfer electrode side wall.

The structure of this embodiment basically conforms to the structure of the seventh embodiment shown in FIG. 13, except that a conductive spacer is provided on the side wall of the transfer electrode in a self-aligning manner.

Referring to FIG. 14, the transfer electrode is composed of, for example, an electrode material film 1402 made of polycrystalline silicon and W, for example.
And a conductive diffusion / reaction prevention film 1420 are laminated in this order from the bottom, and a second insulating film 1415 made of, for example, a silicon oxide film is further laminated thereon, and, for example, a multi-layer is formed on the side wall. A conductive spacer 1416 made of crystalline silicon is formed as a part of the transfer electrode.

In this embodiment, a conductive diffusion / reaction preventing film 1420 is provided on the uppermost layer of the transfer electrode, so that a contact hole 1410 is formed immediately above the transfer channel diffusion layer 1490 as in the seventh embodiment. Even if they are arranged, the transfer efficiency does not deteriorate. The advantage of the single-layer electrode structure is described in the fifth embodiment, and the advantage of providing the second insulating film 1415 on the conductive diffusion / reaction prevention film 1420 is described in the seventh embodiment. That's right.

In forming the transfer electrode structure as shown in FIG. 14, the first electrode material film 1402, the conductive diffusion / reaction prevention film 1420 and the second insulating film 1415 are used for patterning the transfer electrode. Can be processed simultaneously with a mask. In addition, the conductive spacer 1416 does not require a mask for its formation. That is, for example, polycrystalline silicon is deposited and doped by low pressure CVD to about 100 nm to 500 nm, and anisotropic etching is performed on silicon to form conductive spacers on the sidewalls of the transfer electrodes in a self-aligned manner. Therefore, the required number of masks does not increase.

Further, since the conductive spacer 1416 can reduce the gap between the transfer electrodes,
It is possible to prevent the transfer efficiency from deteriorating by narrowing the transfer electrode interval without reducing the minimum processing size in the process used.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer without suppressing the increase in the number of process steps and without causing the deterioration of the transfer efficiency. can do.

<Embodiment 9> Next, a sectional view of a ninth embodiment of the present invention is shown in FIG. FIG. 15 shows a single-layer electrode structure,
The uppermost layer of the transfer electrode is composed of a conductive diffusion / reaction prevention film, the contact between the wiring and the transfer electrode is arranged on the transfer channel region, and the conductive diffusion / reaction prevention film is covered with an insulating film. FIG. 9 is a cross-sectional view of an example in which a transfer electrode is processed after a spacer is provided in a side wall of the insulating film in a self-aligning manner after the insulating film is patterned. The structure of this embodiment basically conforms to the structure of the seventh embodiment shown in FIG. 13, except that the sidewall of the second insulating film covering the conductive diffusion / reaction preventing film is self-assembled. The spacers are provided in a consistent manner, and the electrode material film and the conductive diffusion / reaction preventing film are patterned by using the second insulating film and the spacers on the side walls thereof as a mask.

Referring to FIG. 15, the transfer electrode is composed of, for example, an electrode material film 1502 made of polycrystalline silicon and W, for example.
And a second insulating film 1515 made of, for example, a silicon oxide film and a spacer 1516 are formed thereon. The transfer electrode is patterned using the second insulating film 1515 and the spacer 1516 as a mask.

In this embodiment, a conductive diffusion / reaction preventing film 1520 is provided on the uppermost layer of the transfer electrode, so that a contact hole 1510 is formed immediately above the transfer channel diffusion layer 1590 as in the seventh embodiment. Even if they are arranged, the transfer efficiency does not deteriorate. The advantage of the single-layer electrode structure is described in the fifth embodiment, and the advantage of providing the second insulating film 1515 on the conductive diffusion / reaction prevention film 1520 is described in the seventh embodiment. That's right.

In forming the transfer electrode structure as shown in FIG. 15, first, only the second insulating film 1515 is patterned, and then, for example, a silicon oxide film is formed to a thickness of 50 nm to 500 nm.
The spacer 1516 is formed on the sidewall of the second insulating film 1515 in a self-aligned manner without a mask by depositing the silicon oxide film by about 1 nm by low pressure CVD and performing anisotropic etching on the silicon oxide film. After that, the conductive diffusion / reaction prevention film 1520 and the electrode material film 1502 may be patterned using the second insulating film 1515 and the spacer 1516 as a mask. Therefore, the required number of masks does not increase.

Further, since the spacer 1516 can narrow the gap between the transfer electrodes, it is possible to prevent the deterioration of the transfer efficiency by narrowing the transfer electrode gap without reducing the minimum processing dimension in the process used. You can Moreover, in the eighth embodiment shown in FIG. 14, the first insulating film 1401 in the portion covered by the conductive spacer 1416 is exposed once during the patterning of the electrode material film 1402. Spacer 15 in the example
The first insulating film 1501 of the electrode portion formed using 16 as a mask is still covered with the electrode material film 1502 and is not exposed. Therefore, in the structure of this embodiment, the first insulating film 1501 is prevented from being contaminated or damaged, and there is little possibility that problems such as deterioration of breakdown voltage will occur.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer without increasing the number of process steps and without deteriorating the transfer efficiency. can do.

The structure of this embodiment is such that, as shown in FIGS. 7 to 9 of the fifth embodiment, a conductive or insulating diffusion / reaction preventing film is sandwiched between transfer electrodes. It goes without saying that the structure in which the diffusion / reaction preventing film is provided only in the region where the wiring contacts the transfer electrode as in the sixth embodiment shown in FIGS. 10 to 12 can be applied.

<Embodiment 10> Next, a sectional view of a tenth embodiment of the present invention is shown in FIG. FIG. 16 shows a single-layer electrode structure in which the uppermost layer of the transfer electrode is formed of a conductive diffusion / reaction prevention film, and the contact between the wiring and the transfer electrode is arranged on the transfer channel region, and the conductive diffusion / reaction prevention film is formed. FIG. 6 is a cross-sectional view of an example in which the transfer electrode is processed after the upper portion of the reaction preventive film is covered with an insulating film and the side wall of the conductive diffusion / reaction preventive film is covered with a spacer formed in a self-aligned manner.

The structure of this embodiment is basically similar to the structure of the ninth embodiment shown in FIG. 15, but in FIG. 15, the spacer 15 limited to the side wall of the second insulating film 1515 is used.
16 differs from the present embodiment in that it extends to the side wall of the conductive diffusion / reaction prevention film.

Referring to FIG. 16, the transfer electrode is composed of, for example, an electrode material film 1602 made of polycrystalline silicon and W, for example.
And a conductive diffusion / reaction prevention film 1620 made of, for example, and a second insulating film 1615 made of, for example, a silicon oxide film is formed thereon. The spacer 1616 made of, for example, a silicon oxide film is used as the second insulating film 1
Not only the side wall of 615 but also the conductive diffusion / reaction prevention film 1
The electrode material film 1602 covers the side wall of 620 and is patterned using the spacer 1616 and the second insulating film 1615 as a mask.

In this embodiment, a conductive diffusion / reaction preventing film 1620 is provided on the uppermost layer of the transfer electrode, so that a contact hole 1610 is formed immediately above the transfer channel diffusion layer 1690 as in the tenth embodiment. Even if they are arranged, the transfer efficiency does not deteriorate. The advantage of the single-layer electrode structure is described in the fifth embodiment, and the advantage of providing the second insulating film 1615 on the conductive diffusion / reaction prevention film 1620 is described in the seventh embodiment. That's right.

In forming the transfer electrode structure as shown in FIG. 16, first, only the second insulating film 1615 and the conductive diffusion / reaction preventing film 1620 are patterned, and then, for example, a silicon oxide film of about 100 nm to 500 nm is formed. The spacers 1 are deposited on the sidewalls of the second insulating film 1615 and the conductive diffusion / reaction prevention film 1620 by depositing by low pressure CVD and anisotropically etching the silicon oxide film.
616 is formed in a self-aligned manner without a mask. After that, the electrode material film 1602 may be patterned using the second insulating film 1615 and the spacer 1616 as a mask. Therefore, the required number of masks does not increase.

Further, the advantage of reducing the gap between the transfer electrodes by the spacer 1616 and the advantage of protecting the gate insulating film of the electrode portion projected by the spacer 1616 are as described in the ninth embodiment.

Moreover, in the structure of this embodiment, the spacer 1
When an insulating material is used for 616, there is an advantage that the parasitic capacitance between the opposing transfer electrodes is smaller than that of the structure of the ninth embodiment shown in FIG. This is because in the structure of the twelfth embodiment, the electrode material film 1502 and the conductive diffusion / reaction prevention film 1520 face the adjacent transfer electrodes at the same distance, but in the present embodiment, This is because the diffusion / reaction prevention film 1620 has a facing distance that is twice as large as the width of the spacer 1616 as compared with the electrode material film 1602, and as a result, the capacitance between the facing transfer electrodes decreases. Needless to say, this works for driving the transfer electrodes at high speed.

As described above, by adopting the structure of this embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer without increasing the number of process steps and without deteriorating the transfer efficiency. In addition, a transfer electrode structure suitable for higher speed driving can be formed.

<Embodiment 11> Next, a sectional view of an eleventh embodiment of the present invention is shown in FIG. FIG. 17 shows a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of a conductive diffusion / reaction prevention film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and An embodiment in which the reaction prevention film is covered with an electrode material film and an insulating film, and then the transfer electrode is patterned, and a spacer is provided in a self-aligning manner on the side wall of the insulating film, the electrode material film, and the conductive diffusion / reaction prevention film. FIG.

The structure of this embodiment basically conforms to the structure of the tenth embodiment shown in FIG. 16, but a conductive diffusion / reaction preventing film is provided as an intermediate layer of the transfer electrode. The difference is.

Referring to FIG. 17, the transfer electrode comprises a first electrode material film 1702 made of, for example, polycrystalline silicon, a conductive diffusion / reaction prevention film 1720 made of, for example, W, and a second electrode made of, for example, polycrystalline silicon. Electrode material film 171
2 and a second insulating film 1715 made of, for example, a silicon oxide film is formed thereon. A spacer 1716 made of, for example, a silicon oxide film is provided on the sidewalls of the conductive diffusion / reaction prevention film 1720, the second electrode material film 1712, and the second insulating film 1715.

This embodiment has the same effects as the tenth embodiment, but since the conductive diffusion / reaction preventing film is provided as the intermediate layer of the transfer electrode, the conductive diffusion / reaction is prevented. It is possible to further suppress the intrusion of the element forming the protective film into the silicon substrate.

13 to 17, 1300, 1
400, 1500, 1600, 1700 are semiconductor substrates of the first conductivity type (for example, p-type semiconductor substrate) 1390, 149
Reference numerals 0, 1590, 1690, and 1790 denote transfer channel diffusion layers of the second conductivity type (for example, n-type diffusion layers formed by diffusing arsenic) 1301, 1401, 1501, 1601,
Reference numeral 1701 denotes a first insulating film made of, for example, a silicon oxide film, 1304, 1404, 1504, 1604, and 1704 denote interlayer insulating films made of, for example, a silicon oxide film.
5, 1405, 1505, 1605, 1705 are wirings made of, for example, Al, 1310, 1410, 1510,
Reference numerals 1610 and 1710 denote contact holes formed by dry etching or wet etching with respect to, for example, a silicon oxide film.

Further, wirings 1305, 1405, 150
Electrode material films 1302, 1402, 150 are formed of Al or Al alloy-based material as 5, 1605, 1705.
2, 1602 and the first electrode material film 1702 and the second electrode material film 1712 when polycrystalline silicon, doped silicon or amorphous silicon is used, conductive diffusion / reaction prevention films 1320, 1420, 152
0, 1620, 1720 is W, Ti, Mo or a silicide thereof or a composite film thereof, and second insulating films 1315, 1415, 1515, 1615, 17
As the material 15, a silicon oxide film, a silicon nitride film, or a composite film thereof can be used. As the conductive spacer 1416, polycrystalline silicon, doped silicon, or amorphous silicon may be used, or W, Ti, or Mo silicide may be used.
Further, as the spacers 1516, 1616, 1716, a silicon oxide film, a silicon nitride film, polycrystalline silicon, doped silicon, or amorphous silicon may be used (however, the spacers 1616 and 171).
When polycrystalline silicon, doped silicon, amorphous silicon, or a conductive material such as W, Ti, or Mo silicide is used for 6, the effect of reducing the parasitic capacitance between the transfer electrodes facing each other decreases.

<Embodiment 12> Next, sectional views of a twelfth embodiment of the present invention are shown in FIGS. 18 to 22 show a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction prevention film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and By the thin connection layer formed on the side wall of the
It is an example showing a method of manufacturing a structure in which electrode material films above and below an insulating diffusion / reaction preventing film are connected.

FIG. 18 shows a semiconductor substrate 180 of the first conductivity type.
A transfer channel diffusion layer 1890 of the second conductivity type is formed in the semiconductor layer 0, and a first insulation film 1801 serving as a gate insulation film is formed on the surface of the semiconductor substrate 1800 of the first conductivity type by, for example, thermal oxidation to a thickness of about 10 nm to 200 nm. After that, a first electrode material film 1802 is formed by depositing and doping polycrystalline silicon by about 20 nm to 200 nm by, for example, a low pressure CVD method, and an insulating diffusion / reaction preventing film 1825 is formed thereon, for example. A silicon oxide film is deposited to a thickness of about 10 nm to 100 nm by a low pressure CVD method, and a second electrode material film 1812 is formed on the second electrode material film 1812 by, for example, a low pressure CVD method to form polycrystalline silicon in a thickness of 50 nm to 300 n.
The second insulating film 1815 is formed by depositing and doping for about m, and further, a second insulating film 1815 is formed by depositing a silicon oxide film by about 50 nm to 300 nm by, for example, a low pressure CVD method.

Next, using the mask for patterning the transfer electrode, the second insulating film 1815, the second electrode material film 1812, the insulating diffusion / reaction preventing film 1825, and the first electrode material film. 1802 is etched (FIG. 19).

Further, a third electrode material film 1817 for connecting the first electrode material film 1802 and the second electrode material film 1812 is deposited by, for example, low pressure CVD method to deposit polycrystalline silicon to a thickness of about 50 nm to 200 nm. It is formed by doping, and a third insulating film 1818 is formed thereon.
With a silicon oxide film of 50 n by, for example, a low pressure CVD method.
It is formed by depositing about m to 300 nm (FIG. 20).
The third insulating film 1818 serves as a spacer and serves as a mask when the third electrode material film 1817 is etched.

Then, for example, anisotropic dry etching is performed on the silicon oxide film to form the insulating spacer 1816 in the side wall portion in a self-aligned manner, and the insulating spacer 1816 is used as a mask for the third electrode material. The film 1817 is etched (FIG. 21).

Finally, as the inter-layer insulation film 1804, for example, PSG is formed by the atmospheric pressure CVD method at 200 nm to 700 n.
After depositing about m, the contact hole 1810 is opened by, for example, dry etching with respect to the silicon oxide film, and the wiring 1805 is completed by depositing Al for about 200 nm to 1000 nm by sputtering and patterning (FIG. 22).

In this embodiment, by providing an insulating diffusion / reaction preventing film 1825 on the intermediate layer of the transfer electrode, the contact hole 18 is formed immediately above the transfer channel diffusion layer 1890.
Even if 10 is arranged, the transfer efficiency does not deteriorate. The advantage of the single-layer electrode structure is as described in the fifth embodiment. Further, compared with the case where the upper and lower electrode layers are connected by the conductive spacers as shown in FIG. 9 of the fifth embodiment, in this embodiment, the distance between the transfer electrode sidewalls is equal to the width of the insulating spacer 1816. There is an area where is large. As a result, if the same comparison is made with the minimum distance between the adjacent transfer electrodes, the parasitic capacitance generated between the opposing side walls of the transfer electrodes becomes smaller than that in the fifth embodiment, and it is more suitable for high-speed driving of the transfer electrodes. It becomes a structure.

Further, as described above, the only masks required are those for patterning the transfer electrodes, and the number of masks does not increase.

As described above, by adopting the manufacturing method of the present embodiment, the contact between the transfer electrode and the wiring is formed on the transfer channel diffusion layer while suppressing the increase in the number of process steps and without deteriorating the transfer efficiency. In addition, the parasitic capacitance between the transfer electrodes can be reduced.

The first to third electrode material films 180
2, 1812 and 1817 may be doped silicon or amorphous silicon, and the insulating diffusion / reaction preventing film 1825, the second insulating film 1815 and the third insulating film 1818 are formed of a silicon nitride film or a silicon oxide film and a silicon nitride film. It may be a composite film with a film. Further, it is also possible to use W, Ti, Mo or a silicide thereof or a composite film thereof for the third electrode material film 1817. In this case,
Light that obliquely enters the transfer electrode sidewall can be prevented from entering, and smear noise can be suppressed.

As a conventional example in which a conductor film is formed so as to cover a transfer electrode having a single-layer structure made of polycrystalline silicon, there is JP-A-4-302151. In this conventional example,
For example, the W film is selectively grown on the transfer electrode having a single layer structure made of polycrystalline silicon, and therefore the entire transfer electrode including the side wall portion of the transfer electrode is covered with the W film. On the other hand, in the manufacturing method of the present embodiment, only the side wall portion of the transfer electrode, which is effective in preventing the entrance of obliquely incident light, can be covered with the light-shielding material, and smears are sufficiently suppressed, while being compared with the above-mentioned conventional example. This has the advantage that the exposed area of the light-shielding material is small.

<Embodiment 13> Next, sectional views of a thirteenth embodiment of the present invention are shown in FIGS. 23 to 25 show a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction prevention film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and 2 is an embodiment showing a method of manufacturing a structure in which the electrode material films above and below the insulating diffusion / reaction preventing film are connected by the two connecting layers formed on the side wall of the device in a self-aligned manner.

This embodiment is basically shown in FIGS.
According to the twelfth embodiment shown in FIG. 2, however, in the twelfth embodiment, a connection layer for connecting the electrode material films above and below the insulating diffusion / reaction prevention film is formed at one time. In contrast to this, the present embodiment is different in that it is formed twice.

The following is a description with reference to the drawings. FIG. 23 shows a structure similar to that of FIG. 19 of the twelfth embodiment, except that the third electrode material film 23
17 is made of polycrystalline silicon 2 by, for example, a low pressure CVD method.
It is formed by depositing and doping about 0 nm to 100 nm.

Next, a fourth electrode material film 2319 is formed, for example, by depositing and doping polycrystalline silicon by about 20 nm to 100 nm by a low pressure CVD method, and a third insulating film 2318 is further formed thereon, for example. A silicon oxide film of 50 nm to 30 is formed by the low pressure CVD method.
It is formed by depositing about 0 nm (FIG. 24).

Then, for example, anisotropic dry etching is performed on the silicon oxide film to form an insulating spacer 2316 from the third insulating film 2318, and using the insulating spacer 2316 as a mask, the third and fourth electrode material films 2 are formed.
317 and 2319 are etched. Further, the interlayer insulating film 2304 is formed by, for example, PSG using an atmospheric pressure CVD method to form 20
After depositing about 0 nm to 700 nm, the contact hole 2310 is opened by, for example, dry etching with respect to the silicon oxide film, and the wiring 2305 is formed by, for example, A.
l is deposited by sputtering to a thickness of about 200 nm to 1000 nm and patterned to complete (FIG. 25).

In this embodiment, the connection layer for connecting the electrode material films above and below the insulating diffusion / reaction preventing film is formed in two steps. By adopting such a manufacturing method, the film thickness of the third electrode material film 2317 at the first time can be made sufficiently small, and thereby ion implantation can be performed from above the third electrode material film 2317 without trouble. Become. Finally, the fourth electrode material film 2319 is overlaid and formed so that the thickness of the electrode in the portion where the electrode gap is sandwiched can be set to a required value. At this time, the third electrode material film 2
It is desirable that the sum of the film thicknesses of 317 and the fourth electrode material film 2319 is set to a value that can reduce the capacitance of the transfer electrodes facing each other and that an appropriate fringe electric field can reach the transfer channel region below the electrode gap. .

Incidentally, the third and fourth electrode material films 231.
7, 2319 may be doped silicon or amorphous silicon, and the third and fourth electrode material films 23
It is also possible to use W, Ti, Mo or a silicide thereof or a composite film thereof for 17, 2319. In this case, it is possible to prevent the obliquely incident light from entering the transfer electrode side wall and suppress smear noise. . The materials for the other parts are in accordance with the description for the corresponding parts in the twelfth embodiment.

Reference numeral 2300 is a semiconductor substrate of the first conductivity type, and 2301 is a first insulating film serving as a gate insulating film.
Reference numeral 390 denotes a second conductivity type transfer channel diffusion layer 2302.
Is a first electrode material film, 2325 is an insulating diffusion / reaction prevention film, 2312 is a second electrode material film, 2315.
Indicates a second insulating film.

<Embodiment 14> Next, sectional views of a fourteenth embodiment of the present invention are shown in FIGS. 26 to 28 show a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction preventing film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and 2 is an example showing a method for manufacturing a structure in which electrode material films above and below an insulating diffusion / reaction prevention film are connected by a connection layer formed in a self-aligning manner on the side wall of The case where the spacer for forming is formed of the same material as the connection layer is shown.

This embodiment is basically shown in FIGS.
2 is similar to the twelfth embodiment shown in FIG. 2 except that the spacer 1816 in the twelfth embodiment is formed of an electrode material film instead of an insulating film.

The following is a description with reference to the drawings. FIG. 26 shows a structure corresponding to that of FIG. 19 of the twelfth embodiment, which has a third electrode material film 26.
17 is made of polycrystalline silicon 2 by, for example, a low pressure CVD method.
It is formed by depositing and doping about 0 nm to 100 nm.

Next, a fourth electrode material film 2619 is formed by depositing and doping polycrystalline silicon to a thickness of about 50 nm to 300 nm by, for example, the low pressure CVD method (FIG. 25). At this time, the material of the fourth electrode material film 2619 is the same as that of the third electrode material film 2617.

Then, the fourth electrode material film 2619 is formed by, for example, anisotropic dry etching on polycrystalline silicon.
A spacer 2616 is formed from the above, and the third electrode material film 2617 is also etched as it is. Further, the interlayer insulating film 2
604, for example, PSG, 200n by atmospheric pressure CVD method
After depositing about m to 700 nm, the contact hole 2610 is opened by, for example, dry etching with respect to a silicon oxide film, and the wiring 2605 is completed by depositing Al for about 200 nm to 1000 nm by sputtering and patterning (FIG. 28).

In this embodiment, in order to form the third electrode material film 2617 which is a connection layer for connecting the electrode material films above and below the insulating diffusion / reaction preventing film and the connection layer in a self-aligned manner. And the spacer 2616 are formed of the same material. Thereby, the formation of the spacer 2616 and the etching of the third electrode material film 2617, that is, the formation of the transfer electrode can be performed without changing the etching target in the same process, and thus the process is simplified as compared with the twelfth embodiment. it can. However, the effect of reducing the parasitic capacitance between the transfer electrodes is smaller than that in the twelfth embodiment.

The third and fourth electrode material films 261
7, 2619 may be doped silicon or amorphous silicon, and the third and fourth electrode material films 26
It is also possible to use W, Ti, Mo or a silicide thereof or a composite film thereof for 17, 2619. In this case, it is possible to prevent the obliquely incident light from entering the transfer electrode side wall and suppress smear noise. . For the materials of the other parts, the description of the corresponding parts in the twelfth embodiment is applied.

Further, 2600 is a semiconductor substrate of the first conductivity type, and 2601 is a first insulating film serving as a gate insulating film.
Reference numeral 690 denotes a second conductivity type transfer channel diffusion layer, 2602.
Is a first electrode material film, 2625 is an insulating diffusion / reaction prevention film, 2612 is a second electrode material film, 2615.
Indicates a second insulating film.

<Embodiment 15> Next, sectional views of the fifteenth embodiment of the present invention are shown in FIGS. 29 to 33 show a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction prevention film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and Is a working example of a structure in which the electrode material films above and below the insulating diffusion / reaction preventing film are connected by a connection layer formed in a self-aligning manner on the side wall of The case where the lower gate insulating film is not exposed during the formation of the transfer electrode is shown.

FIG. 29 shows a semiconductor substrate 290 of the first conductivity type.
0, a second conductivity type transfer channel diffusion layer 2990 is formed, and a first insulation film 2901 serving as a gate insulation film is formed on the surface of the first conductivity type semiconductor substrate 2900, for example, by thermal oxidation to a thickness of about 10 nm to 200 nm. After that, a first electrode material film 2902 is formed by depositing and doping polycrystalline silicon by about 20 nm to 200 nm by, for example, a low pressure CVD method, and an insulating diffusion / reaction preventing film 2925 having an insulating property is formed thereon, for example. A silicon oxide film is deposited to a thickness of about 10 nm to 100 nm by a low pressure CVD method, and a second electrode material film 2912 is formed on the second electrode material film 2912 by, for example, a low pressure CVD method to form polycrystalline silicon in a thickness of 50 nm to 300 n.
The second insulating film 2915 is formed by depositing and doping for about m, and further, a second insulating film 2915 is formed by depositing a silicon oxide film by about 50 nm to 300 nm by, for example, a low pressure CVD method.

Next, the second insulating film 2915, the second electrode material film 2912, and the insulating diffusion / reaction prevention film 2925 are etched using a mask for patterning the transfer electrodes (FIG. 30). .

Further, a third electrode material film 2919 for connecting the first electrode material film 2902 and the second electrode material film 2912 is deposited, for example, by low pressure CVD with polycrystalline silicon deposited to a thickness of about 50 nm to 300 nm. It is formed by doping (FIG. 31).

Then, for example, anisotropic dry etching is performed on polycrystalline silicon to form conductive spacers 2916 on the side wall portions in a self-aligned manner, and the conductive spacers 2916 are used as a mask for the first electrode. The material film 2902 is etched (FIG. 32).

Finally, as the interlayer insulating film 2904, for example, PSG is formed by the atmospheric pressure CVD method at 200 nm to 700 n.
After depositing about m, the contact hole 2910 is opened by, for example, dry etching with respect to the silicon oxide film, and the wiring 2905 is completed by depositing Al for about 200 nm to 1000 nm by sputtering and patterning (FIG. 33).

In this embodiment, by providing an insulating diffusion / reaction preventing film 2925 in the intermediate layer of the transfer electrode, the contact hole 29 is formed immediately above the transfer channel diffusion layer 2990.
Even if 10 is arranged, the transfer efficiency does not deteriorate. The advantage of the single-layer electrode structure is as described in the fifth embodiment. Further, the advantage of reducing the gap between the transfer electrodes by the spacer 2916 is as described in the ninth embodiment.

Moreover, in the twelfth to fourteenth embodiments, the first insulating film serving as the gate insulating film is exposed once at the time of patterning the electrode material film in the portion where the spacer is formed. In this embodiment, the first insulating film 2901 serving as the gate insulating film of the electrode portion formed by using the spacer 2916 as a mask is still covered with the electrode material film 2902 and is not exposed. For this reason, in the structure of the present embodiment, the contamination and damage of the first insulating film 2901 are suppressed, and there is little possibility that problems such as deterioration of breakdown voltage will occur.

Further, as shown in the description of FIGS. 30 to 32, the only masks required are those for patterning the transfer electrodes, and the number of masks does not increase.

As described above, by adopting the manufacturing method of the present embodiment, the contact between the transfer electrode and the wiring is made on the transfer channel diffusion layer without suppressing the increase in the number of process steps and without causing the deterioration of the transfer efficiency. It is possible to suppress the deterioration of the gate insulating film formed at the end of the transfer electrode.

The first to third electrode material films 290
2, 2912 and 2919 may be doped silicon or amorphous silicon, and the insulating diffusion / reaction preventing film 2925 and the second insulating film 2915 may be a silicon nitride film or a composite film of a silicon oxide film and a silicon nitride film. . In addition, W, Ti,
It is also possible to use Mo or a silicide thereof or a composite film thereof, and in this case, it is possible to prevent intrusion of light obliquely incident on the side wall of the transfer electrode and suppress smear noise.

<Embodiment 16> Next, sectional views of a sixteenth embodiment of the present invention are shown in FIGS. 34 to 36 show a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction preventing film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and Is a working example of a structure in which the electrode material films above and below the insulating diffusion / reaction preventing film are connected by a connection layer formed in a self-aligning manner on the side wall of Another example is shown in which the gate insulating film is not exposed during the formation of the transfer electrode.

This embodiment is basically the same as that shown in FIGS.
According to the fifteenth embodiment shown in FIG. 3, a conductive spacer is used to connect the electrode material film above and below the insulating diffusion / reaction prevention film in the fifteenth embodiment. In contrast to this, in the present embodiment, the electrode material film for connection is not processed into a spacer, but an insulating spacer is formed thereon to form a transfer electrode.

The following is a description with reference to the drawings. In FIG. 34, a third electrode material film 3417 is formed by depositing / doping polycrystalline silicon to a thickness of about 20 nm to 100 nm by, for example, a low pressure CVD method in the structure corresponding to that of FIG. 30 of the fifteenth embodiment. , A third insulating film 3419,
For example, it is just formed by depositing a silicon oxide film of about 50 nm to 300 nm by the low pressure CVD method.

Next, a spacer 3416 is formed from the third insulating film 3419 by, for example, anisotropic dry etching with respect to a silicon oxide film, and the first and third electrode material films 3402 and 3417 are etched using the spacer 3416 as a mask. (FIG. 35).

Further, the interlayer insulating film 3404 is formed, for example, with P
After SG is deposited to a thickness of about 200 nm to 700 nm by the atmospheric pressure CVD method, a contact hole 3410 is formed by dry etching with respect to, for example, a silicon oxide film, and a wiring 3405 is formed by sputtering, for example, Al.
It is completed by depositing and patterning about 00 nm to 1000 nm (FIG. 36).

In this embodiment, when the minimum distance between adjacent transfer electrodes is the same, the upper and lower electrode layers are connected by a conductive spacer as in the fifteenth embodiment shown in FIGS. 29 to 33. Insulating spacer 341 compared to the case of
There is a region in which the distance between the transfer electrode sidewalls is increased by the width of 6. As a result, the parasitic capacitance generated between the opposite side walls of the transfer electrode becomes smaller than that in the fifteenth embodiment, and the structure is more suitable for high-speed driving of the transfer electrode.

The third electrode material film 3417 may be doped silicon or amorphous silicon, and the third electrode material film 3417 may be made of W, Ti, Mo or a silicide thereof or a composite film thereof. In this case, therefore, it is possible to prevent the light obliquely incident on the side wall of the transfer electrode from entering and suppress smear noise. The materials for the other parts are in accordance with the description of the corresponding parts in the fifteenth embodiment.

Further, 3400 is a first conductivity type semiconductor substrate, and 3401 is a first insulating film serving as a gate insulating film.
Reference numeral 490 denotes a second conductivity type transfer channel diffusion layer 3402.
Is a first electrode material film, 3425 is an insulating diffusion / reaction prevention film, 3412 is a second electrode material film, 3415.
Indicates a second insulating film.

<Embodiment 17> Next, FIG. 37 shows a sectional view of a seventeenth embodiment of the present invention. FIG. 37 shows a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction preventing film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and at the side wall of the transfer electrode. A manufacturing method of a structure in which the electrode material films above and below the insulating diffusion / reaction prevention film are connected by the connection layer formed in a self-aligning manner. An example in which a melting point metal silicide is used is shown.

The structure of this embodiment is basically similar to the structure of the sixteenth embodiment shown in FIGS. 34 to 36, but a silicon-based material is used for the first electrode material film. The difference is that refractory metal is used for the second electrode material film and refractory metal silicide is used for the third electrode material film.

Specifically, the first conductivity type semiconductor substrate 37.
00, a second conductivity type transfer channel diffusion layer 3790 is formed, and further, a plurality of transfer electrodes for driving the CCD are arranged through a first insulating film 3701 which is a gate insulating film, This transfer electrode is the first electrode material film 3
702, an insulating diffusion / reaction preventing film 3725, a second electrode material film 3712, a second insulating film 3715, a third electrode material film 3717, and an insulating spacer 3716. An interlayer insulating film 3704 is formed between the transfer electrode and the wiring 3705. Also, the wiring 370
Reference numeral 5 is connected to the transfer electrode in the center of FIG. 37 through a contact hole 3710 arranged on the transfer channel diffusion layer 3790.

Then, here, the first electrode material film 370 is formed.
2 is, for example, 20% polycrystalline silicon by a low pressure CVD method.
The insulating diffusion / reaction prevention film is formed by, for example, low-voltage CV by depositing / doping of about 200 nm to 200 nm.
Silicon oxide film 10 nm to 100 nm by D method
The third electrode material film 3717 is formed by depositing W to a thickness of about 50 nm to 300 nm by, for example, a low pressure CVD method.
Is used to form a W silicide film by a low pressure CVD method.
and a wiring 370.
5 is formed by depositing Al, for example, by sputtering to a thickness of about 200 nm to 1000 nm.

In this embodiment, the second electrode material film 3712 is used.
For example, a refractory metal such as W is used for the first electrode material film because this material itself serves as a diffusion / reaction prevention film.
The work function change of 3702 is prevented. Further, since the refractory metal such as W and the silicon-based material are not in direct contact with each other, it is possible to suppress the silicidation reaction of the refractory metal due to the heat treatment when the heat treatment at a high temperature is required. be able to.

<Embodiment 18> Next, sectional views of an eighteenth embodiment of the present invention are shown in FIGS. 38 to 40 show a single-layer electrode structure, in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction preventing film to arrange the contact between the wiring and the transfer electrode on the transfer channel region, and In the manufacturing method of the structure in which the electrode material film above and below the insulating diffusion / reaction prevention film is connected by the connection layer formed in the side wall of the self-alignment, in particular, the connection layer is made of a light-shielding material, An example is shown in which the minimum distance between the connection layers between adjacent transfer electrodes is defined in relation to the wavelength of incident light.

In this embodiment, FIG. 38A shows the twelfth embodiment shown in FIG. 22, FIG. 39A shows the fifteenth embodiment shown in FIG.
FIG. 40 (a) conforms to FIG. 36 of the sixteenth embodiment, respectively, but differs in the following two points.

(1) A connection layer for connecting the upper and lower electrode layers of the insulating diffusion / reaction preventing film in the middle of the transfer electrode, that is, the third electrode material film 3817 in FIG. 38 and the conductive spacer in FIG. 39. 3916, and the third electrode material film 4 of FIG.
017 is composed of a light-shielding material.

(2) In FIGS. 38 to 40, the minimum interval w of this connection layer is λ / 2n (λ is the wavelength of incident light, and n
Is the refractive index of the material embedded in the region sandwiched by the connection layers. In FIGS.
(Indicating the refractive index of 04, 3904, 4004)) or less.

Here, each figure (a) is a sectional view in a direction parallel to the signal charge transfer direction, and each figure (b) is a sectional view perpendicular to the signal charge transfer direction.

In this embodiment, by forming a connection layer for connecting the upper and lower electrode layers of the insulating diffusion / reaction preventing film of a light-shielding material on the side wall of the transfer electrode, the light incident from the side is formed. In particular, in each figure (b), the wiring 3805, 390
5,4005 and first conductivity type semiconductor substrates 3800,39
Interlayer insulating films 3804 and 3 sandwiched between 00 and 4000
It is possible to prevent the light transmitted inside the 904 and 4004 from entering the CCD. Also in this case, light can enter the CCD through the gaps between the transfer electrodes, but such a leak of light can be prevented by setting the minimum gap between the connection layers formed of the light-shielding material to λ / 2n or less. Can be suppressed. Because λ / 2n is the geometrical optical cutoff wavelength in the optical waveguide, light having a wavelength of λ or more is attenuated when passing through the gap sandwiched by the light-shielding material, which has an interval of λ / 2n or less. Because it does.

As the light-shielding material for forming the connection layer, W, Ti, Mo, a silicide thereof, or a composite film thereof can be used.

As a conventional example in which light is prevented from entering through the interelectrode gap by setting the interelectrode gap of the single-layer structure transfer electrode to λ / 2n or less, Japanese Patent Laid-Open No. 4-99381 is disclosed. is there. In this conventional example, no particular consideration is given to the specific transfer electrode material and the use position of the material in the transfer electrode, and only the use of polycrystalline silicon as the transfer electrode material is described. . On the other hand, in the present embodiment, for example, the light-shielding material such as W, Ti, Mo or the silicide thereof or the composite film thereof is used only in the side wall portion of the transfer electrode, so that the light entering through the inter-electrode gap can be prevented. It has an advantage that not only the attenuation but also the light transmitted from the side wall of the transfer electrode to the inside of the transfer electrode and entering the inside of the transfer channel can be suppressed.
Further, by locally using the light-shielding material,
It also has the effect of reducing the exposed area of the light-shielding material.

The numbers in FIGS. 38 to 40 are respectively
3890, 3990 and 4090 are transfer channel diffusion layers of the second conductivity type, 3801, 3901 and 4001 are first insulating films, 3802, 3902 and 4002 are first electrode material films, and 3825, 3925 and 4025 are Insulating diffusion
3812, 3912, 4012 are second electrode material films, 3815, 3915, 4015 are second insulating films, 3816, 4016 are spacers, 381
Reference numerals 0, 3910 and 4010 indicate contact holes.

<Embodiment 19> Next, sectional views of a nineteenth embodiment of the present invention are shown in FIGS. 41 to 49 show a single-layer electrode structure in which the intermediate layer of the transfer electrode is formed of an insulating diffusion / reaction preventing film including a silicon nitride film, and the contact between the wiring and the transfer electrode is arranged on the transfer channel region. In addition, it is an embodiment showing a manufacturing method in which the gate insulating film thickness can be changed on the device according to each device in order to obtain the optimum gate insulating film thickness for realizing the necessary electric characteristics.

FIG. 41 shows a semiconductor substrate 410 of the first conductivity type.
On the surface of the first insulating film 4101 to be a gate insulating film.
Of 10 nm to 200 nm is formed by, for example, thermal oxidation, and then the first electrode material film 4102 is formed of polycrystalline silicon of 20 nm to 200 nm by, for example, a low pressure CVD method.
It is formed by depositing / doping to a thickness of about nm, and an insulating diffusion / reaction preventing film 4125 containing a silicon nitride film is formed thereon by depositing a silicon nitride film of about 10 nm to 100 nm by, for example, a low pressure CVD method. is there.

Next, a resist 4191 is formed by patterning so as to cover the portion where the first insulating film 4101 is to be left as it is (FIG. 42).

Next, by dry etching, for example, an insulating diffusion / reaction preventing film 412 containing a silicon nitride film is formed.
5 and the first electrode material film 4102 are etched using the resist 4191 as a mask (FIG. 43). In this way, the first area 4195 and the second area 4196 are defined.

Further, the first insulating film 4101 is formed by, for example, wet etching using the resist 4191 as a mask, or after removing the resist 4191 and using the insulating diffusion / reaction preventing film 4125 containing a silicon nitride film as a mask. Removed, first conductivity type semiconductor substrate 4100
The surface of is exposed (FIG. 44).

Next, the exposed semiconductor substrate 4 of the first conductivity type
A second insulating film 4192 is formed on the surface of 100 by, for example, thermal oxidation to a thickness of about 10 nm to 200 nm to form a first region 4195 having the first insulating film 4101 and a second insulating film formed thereon. A second region 4196 is created (Fig. 4
5). At this time, the first region 4195 is covered with the insulating diffusion / reaction preventing film 4125 containing a silicon nitride film, and thus is affected by thermal oxidation or the like when forming the second insulating film 4192. The film thickness does not change.
In addition, the first insulating film 4101 is the second insulating film 4192.
Insulating diffusion / reaction prevention film 4125 containing a silicon nitride film in a process such as resist formation, resist removal, dry or wet etching performed until the formation of
Since it is covered with, it is not directly exposed to the resist, etching solution, etching plasma, etc., and damage due to etching and contamination with impurities can be prevented. This can prevent a decrease in withstand voltage and an increase in surface level of the first insulating film 4101.

Although this figure shows the case where the thickness of the second insulating film 4192 is made smaller than that of the first insulating film 4101, the second insulating film 4192 is made to have the second insulating film 4192 conversely according to the required element characteristics. The thickness of the insulating film 4192 can be increased.
It is also possible to change the film type between the first insulating film 4101 and the second insulating film 4192. For example, the first insulating film is a composite film of a silicon nitride film and a silicon oxide film, and the second insulating film is The insulating film may be a silicon oxide film only.

Next, the first area 4195 and the second area 4
Second electrode material film 4112 forming the gate electrode at 196
Of polycrystalline silicon by, for example, a low pressure CVD method.
It is formed by depositing and doping about m to 300 nm (FIG. 46).

Then, in the first region 4195, the second electrode material film 4112 and the insulating diffusion / reaction preventing film 4125 containing a silicon nitride film are formed, and in the second region 4196.
Then, after patterning only the second electrode material film 4112, a third electrode material film 4117 for connecting the first electrode material film 4102 and the second electrode material film 4112 is formed in the first region 4195. For example, it is formed by depositing and doping polycrystalline silicon with a thickness of about 50 nm to 200 nm by a low pressure CVD method, and further, a spacer 4116.
With a silicon oxide film of 50 n by, for example, a low pressure CVD method.
After depositing about m to 300 nm, it is formed by performing anisotropic dry etching on the silicon oxide film. Next, using the spacer 4116 as a mask, the third electrode material film 4117 and the first electrode material film 4102 are etched and cut in the first region 4195, and the third electrode material film 4117 is cut in the second region 4196. Are cut by etching (FIG. 47).

Finally, as the interlayer insulating film 4104, for example, PSG is formed by the atmospheric pressure CVD method at 200 nm to 700 n.
After depositing about m, the contact hole 4110 is opened by dry etching with respect to, for example, a silicon oxide film, and the wiring 4105 is deposited by sputtering, for example, about 200 nm to 1000 nm of Al and patterned, as shown in FIG. Incidentally. 41 to 48, the diffusion layer in the semiconductor substrate 4100 is omitted.

As described above, by using the manufacturing method of this embodiment, different film thicknesses and film types can be formed on one element without deterioration of film quality such as reduction of withstand voltage of insulating film and increase of surface level. The gate insulating film can be formed.

Next, FIG. 49 shows a sectional view of an embodiment in which the film thickness of the gate insulating film is changed between the pixel portion including the CCD and the peripheral circuit portion including the MOS element.

In FIG. 49, the CCD is displayed in the first area 4195.
A peripheral portion including a MOS element is formed in the second region 4196 of the pixel portion including the above, and the first region 4195 shows a cross section perpendicular to the signal charge transfer direction. In the pixel portion, the second conductivity type light receiving and accumulating portion 4185 is formed in the first conductivity type semiconductor substrate 4100, and the signal charges photoelectrically converted here are transferred to the second conductivity type transfer channel diffusion layer. 4190 after being read into the first electrode material film 41.
02 and an insulating diffusion / reaction preventing film 4125 including a silicon nitride film, a second electrode material film 4112, and a third electrode material film 4117.
It is driven and transferred via 101. On the other hand, in the peripheral circuit part, the second conductivity type source / drain diffusion layer 4180 is formed in the first conductivity type semiconductor substrate 4100.
Second electrode material film 4112 and third electrode material film 4117
And a second insulating film 4192 composed of
Configure an S transistor. The signal charges sent from the pixel portion are subjected to processing such as amplification and calculation by various circuits made of this MOS transistor.

In FIG. 49, in order to improve the performance of the MOS transistor in the peripheral circuit portion, the second insulating film 4192, which is the gate insulating film of the second region 4196, is omitted from the first region 419.
The film thickness is smaller than that of the first insulating film 4101 which is the gate insulating film of No. 5, and by using the manufacturing method shown in FIGS. 41 to 48, a high-performance MOS can be obtained without adversely affecting the CCD of the pixel portion. The transistor can be formed in the peripheral circuit portion.

In the solid-state image pickup device using CCD, C
As a conventional example of a structure in which the gate insulating film thickness of the drive pulse generating circuit section is thinner than that of the CD section, there is JP-A-1-103861. In this conventional example, only an example in which photoetching is performed without covering the gate insulating film with another material in order to change the gate insulating film thickness depending on the location is described.
On the other hand, in the manufacturing method of this embodiment, since the remaining gate insulating film is covered with the insulating diffusion / reaction preventing film 4125 containing the silicon nitride film, the resist used in photoetching and the resist removing process are not removed. Therefore, there is an advantage that the gate insulating film does not come into direct contact with the cleaning liquid for preventing the deterioration of breakdown voltage of the gate insulating film and the intrusion of impurities into the substrate.

<Embodiment 20> Next, sectional views of a twentieth embodiment of the present invention are shown in FIGS. 50 to 53 show an embodiment in which the contact position is shifted from the center of the transfer electrode in the same direction as the transfer electrode when the contact between the wiring and the transfer electrode is arranged on the transfer channel region. FIG. 51 shows a cross-sectional view and an electric potential distribution of the transfer channel in an example in which the position of the contact is almost at the center of the transfer electrode, and FIGS.

First, in FIGS. 50 and 52, transfer channel diffusion layers 5190 and 5390 of the second conductivity type are formed in the semiconductor substrates 5100 and 5300 of the first conductivity type.
Further, transfer electrodes 5102 and 5302 for driving the CCD are arranged through insulating films 5101 and 5301 which are gate insulating films. In addition, conductive diffusion / reaction prevention films 5120 and 53 are formed on top of the transfer electrodes 5102 and 5302.
20 is provided, and further, the interlayer insulating film 5104,
Contact holes 5110 and 5310 formed in 5304
The wirings 5105 and 5305 are connected through the wirings 5105 and 5305, and the wirings 5105 and 5305 connect the transfer electrodes 5102 and 5302 with C.
A pulse voltage for driving the CD is applied.

Here, in FIG. 50, the position of the contact hole 5110 for connecting the wiring 5105 for supplying the drive voltage to the transfer electrode 5102 is approximately at the center of the transfer electrode.

On the other hand, in FIG. 52 showing the present invention, the position of the contact hole 5310 for connecting the wiring 5305 for supplying the drive voltage to the transfer electrode 5302 is on the transfer electrode in the same direction as the charge transfer direction. It is characterized by shifting. By doing so, fluctuations in the potential distribution in the transfer channel (potential peaks and valleys) that may occur due to irradiation damage due to etching when the contact hole 5310 is formed affect the gate insulating film, and charge transfer efficiency is reduced. It is possible to prevent adverse effects.

Next, this will be described with reference to FIGS. 51 and 53. Of these two drawings, the uppermost drawing shows a cross section parallel to the charge transfer direction of the CCD. Transfer electrodes 5150, 5151, 5152, 515
3 and transfer electrodes 5350, 5351, 5352, 535
By applying an appropriate pulse voltage to 3, the charge is transferred. In addition, a wiring 51 for applying a voltage to the transfer electrode
05, 5305 are connected to the transfer electrodes 5150, 5151, 5152, 5153 and the transfer electrodes 5350, 5351, 5352, 5353 via contact holes 5110, 5310 formed in the interlayer insulating films 5104, 5304. 51 and 53, the graphs of (a), (b), and (c) show transfer electrodes 5150, 5151, 5152, and 51.
53 and transfer electrodes 5350, 5351, 5352, 53
The potential distribution in the transfer channel when various voltages are applied to 53 is shown. Here, the case where the charge to be transferred is an electron has been described as an example, but the same can be considered when the charge is a hole by reversing the direction of the potential.

FIG. 51 shows the case where a contact hole is provided in the center of the transfer electrode, and the peaks or valleys of the potential generated under the contact hole are present in the center of the transfer electrode. In FIG. 51 (a), a positive voltage is applied to the transfer electrode 5151 to generate a potential well, and the charge 5156 is stored therein. At this time, a local potential valley 5155 is generated at a position below the contact hole 5110. Next, a positive voltage is applied to the transfer electrode 5152 to further set the voltage of the transfer electrode 5151 to 5150.
51B, the charges move from the transfer electrode 5151 to the well of the potential below the transfer electrode 5152 to become the charges 5159, as shown in FIG. At this time, the transfer electrode 5
The potential valley 5155 at the center of 151 is the transfer electrode 515.
Since it is not affected by the fringe electric field from 2, it remains as it is, and the charge accumulated in the potential valley 5155 also remains. This causes the transfer efficiency to deteriorate.
The same is true in the case where there are peaks instead of potential valleys in the region under the contact hole 5110, and as shown in FIG. 51C, since there is no influence of the fringe electric field, the peaks should be moved by the potential peaks 5157. A part of the electric charge is blocked, which causes deterioration of the transfer efficiency of the electric charge 5158.

On the other hand, in FIG. 53, the contact hole 53
10 shows a state in which the transfer electrode is displaced from the central portion of the transfer electrode, and the peaks or valleys of the potential exist below the end portion of the transfer electrode on the charge transfer direction side. First, FIG. 53A shows a state in which a positive voltage is applied to the transfer electrode 5351 to generate a potential well, and the charge 5356 is stored therein. At this time, the potential valley 5355 is the contact hole 5
It occurs below the position 310, that is, below the end of the transfer electrode on the charge transfer direction side. Next, when a positive voltage is applied to the transfer electrode 5352 so that the voltage of the transfer electrode 5351 is the same as that of the transfer electrode 5350, charge is transferred from the transfer electrode 5351 to a potential below the transfer electrode 5352 as shown in FIG. To the well, and the charge becomes 5359. At this time, the potential valley 5355 at the end of the transfer electrode 5351 is
The charges that have been crushed by the fringe electric field from 52 and accumulated in the potential valley 5355 also move to below the transfer electrode 5352, and the transfer efficiency does not deteriorate. The same is true when there are peaks instead of valleys in the potential in the region under the contact hole 5310, and as shown in FIG. 53 (c), the influence of the fringe electric field also influences and blocks the peaks 5357. The charges also move below the transfer electrode 5352, and the transfer efficiency of the charges 5358 does not deteriorate.

Further, although the case where the contact hole is displaced in the same direction as the charge transfer direction has been described in the present embodiment, the case where the contact hole is displaced in the opposite direction to the charge transfer direction is similarly performed from the adjacent electrode. The fringe electric field crushes the peaks and valleys of the potential that can occur under the contact hole, so that the deterioration of the transfer efficiency is suppressed.

As described above, when the contact between the wiring and the transfer electrode is arranged on the transfer channel region, the position of the contact is displaced from the center of the transfer electrode in the same direction as or in the opposite direction to that of the transfer electrode. It is possible to prevent the potential distribution variation that may occur in the lower transfer channel from adversely affecting the charge transfer efficiency, and it becomes possible to drive at high speed. Although the present embodiment has been described by taking a single-layer structure electrode as an example, it is needless to say that the effect of the present embodiment is not limited to the single-layer structure electrode, and a superposed electrode structure can be similarly applied.

<Embodiment 21> Next, plan views of the twenty-first embodiment of the present invention are shown in FIGS. 54 to 55 show a single-layer electrode structure, in which the contact between the wiring and the transfer electrode is arranged on the transfer channel region.
FIG. 54 is a plan view of an embodiment in which the length of the portion where the transfer electrodes face each other with a narrow gap in the pixel of the one-pixel two-electrode configuration is greatly reduced, and FIG. 54 is a plan view of the pixel portion of the conventional example, FIG. 55 shows a plan view of a pixel portion of the present invention.

FIG. 54 shows a pixel portion having a one-pixel two-electrode structure including a vertical CCD having a single-layer electrode structure. 55
Reference numeral 61 denotes a light receiving / accumulating portion that photoelectrically converts incident light to generate a signal charge, and the signal charge generated here is transferred by a vertical CCD including a transfer electrode 5502 and a transfer channel region 5590. The transfer electrode 5502 has two electrodes arranged for each pixel, and is the most general pixel configuration in which signal charges are transferred by four-phase driving. Also, 55
Reference numeral 05 denotes a light-shielding film formed above the transfer electrode.
In this conventional example, there is a region 5560 where the transfer electrodes face each other at the same value as the narrow interval Sc on the transfer channel region 5590 at the portion where the transfer electrodes of the vertical CCD are connected in the horizontal direction. Assuming an image sensor with 300,000 7 μm square pixels integrated, the total extension of this region 5560 is approximately 1
This is a factor that increases the probability that a short circuit will occur between the transfer electrodes.

On the other hand, FIG. 55 shows an embodiment of the present invention and shows a pixel portion of a one-pixel two-electrode structure including a vertical CCD having a single-layer electrode structure as in FIG. 54. One of the two electrodes is formed so as to be isolated, and there is no part that connects the isolated transfer electrodes 5603 between adjacent vertical CCDs. Therefore, in FIG.
556 in which the transfer electrodes face each other at a narrow interval.
The fact that there are no zeros and the transfer electrodes face each other with a narrow gap is that the transfer channel region 569 that essentially requires it.
Limited to above 0. As a result, in FIG. 54, the region 5 where the transfer electrodes faced each other with a narrow gap over a long distance.
Since 560 is eliminated, the probability of a short circuit between the transfer electrodes occurring is greatly reduced as compared with the structure of FIG.

In order to apply a voltage to the isolated transfer electrode 5603, a contact hole 5610 is formed on the transfer channel region of the isolated transfer electrode 5603 by using the light shielding film 5605 as a wiring. It is possible to supply power. At this time, as described above in the present invention, by providing the transfer electrode with the diffusion / reaction preventing film, it is possible to supply power to the isolated transfer electrode 5603 without degrading the transfer efficiency. However, since the light-shielding film is also used as wiring, in order to apply an independent voltage to each transfer electrode, the light-shielding film 5 as shown at 5655 in FIG.
It is necessary to separate a part of 605 to provide a gap, and this gap serves as a passage for light leakage, which causes smear noise to increase. In order to prevent this, as shown in FIG. 55, it is desirable to dispose the gap 5655 of the light shielding film outside the gap between the transfer electrodes on the transfer channel region 5690. In addition, the gap 565 of the light shielding film
By setting the interval of 5 to be λ / 2n or less (n is the refractive index of the insulating film embedded in the gap of the light-shielding film, λ is the wavelength of incident light), the light leaked from the gap 5655 of the light-shielding film itself is suppressed. It is also possible to do so.

As described above, in the single-layer electrode structure, one transfer electrode in a pixel having two electrodes and one pixel is formed in an isolated form, and power is supplied to the electrode from the wiring also serving as the light shielding film. This can significantly reduce the possibility of short circuit between the transfer electrodes. At this time, by providing a diffusion / reaction preventing film on the isolated transfer electrode, the transfer efficiency is not deteriorated even if the contact hole is arranged on the transfer channel region and the connection with the wiring is made.

The position of the gap of the light-shielding film 5605 which also serves as the wiring is not limited to the position shown in FIG. 55, but other than immediately above the gap of the transfer electrode in order to prevent smear noise due to light leakage. Position is good, especially light-shielding film 5
By adopting a pattern / arrangement that causes less overlap with transfer electrodes that are not supplied with power from 605, it is possible to reduce parasitic capacitance and perform higher-speed driving.

Further, as a conventional example in which one transfer electrode in a pixel of two-pixel constitution of one pixel is formed in an isolated form, and power is supplied to the electrode from a wiring which also serves as a light shielding film,
There is JP-A-63-182857. In this conventional example, two metal wirings, which serve as both power supply to an isolated transfer electrode and light shielding, are provided directly above a CCD having a single-layer electrode structure for transferring charges in parallel in the same direction as the CCD with a narrow gap. Therefore, the gap between the metal wirings also exists on the gap between the transfer electrodes of the CCD having the single-layer electrode structure. On the other hand, in the present embodiment, since the gap of the wiring also serving as the light shield provided on the CCD is in the direction perpendicular to the charge transfer direction, it can be disposed outside the gap between the transfer electrodes, and therefore, can be arranged. It has an advantage that smear can be prevented more effectively.

<Embodiment 22> Next, sectional views of a twenty-second embodiment of the present invention are shown in FIGS. 56 to 59 show a single-layer electrode structure in which a contact between a wiring and a transfer electrode is arranged on a transfer channel region and an impurity for forming a potential barrier is obliquely formed under one end of the transfer electrode. It is an embodiment showing a manufacturing method for realizing a two-phase drive CCD in a self-aligned manner by implanting ions. Further, this embodiment is a two-phase driving CCD using oblique ion implantation in the conventional example disclosed in Japanese Patent Laid-Open No. 3-60158.
This is an example in which the manufacturing method of is applied to the fifteenth embodiment of the present invention.

The manufacturing method of this embodiment is basically the same as that shown in FIG.
Or according to the manufacturing method of the fifteenth embodiment shown in FIG. 33, except that the impurity ions for forming the potential barrier are formed obliquely from above the film corresponding to the first electrode material film 2902 in FIG. The difference is that the driving is done.

This will be specifically described with reference to the drawings. FIG. 56 shows a structure corresponding to FIG. 30 of the fifteenth embodiment. Next, impurities forming the diffusion layer of the first conductivity type are added to the first electrode material film.
Diagonal ion implantation is performed from above 5702 to introduce it into the transfer channel diffusion layer of the second conductivity type and activate it to form a diffusion layer 5761 serving as a potential barrier against signal charges (FIG. 57).
At this time, the oblique ion implantation 5760 is inclined and implanted so that the introduced impurities are offset to the same side as the signal charge transfer direction shown in FIG.

Further, a conductive spacer 5716 is formed, and the first electrode material film is cut and separated using this as a mask (FIG. 58). At this time, the angle of the oblique ion implantation 5760, the dose amount, the heat treatment amount for activation, and the like are controlled to arrange the diffusion layer 5761 serving as a potential barrier under the first electrode material film 5702 that has been cut and separated. be able to.

Finally, after depositing an interlayer insulating film 5704 and opening a contact hole 5710, a wiring 5705 is deposited and patterned to obtain a structure shown in FIG.

In this embodiment, by providing an insulating diffusion / reaction preventing film 5725 on the intermediate layer of the transfer electrode, as in the fifteenth embodiment, a contact hole 5710 is formed directly above the transfer channel diffusion layer 5790. Does not cause the transfer efficiency to deteriorate. The advantage of the single-layer electrode structure is as described in the fifth embodiment. In addition, the spacer 57
The advantage of reducing the gap between the transfer electrodes by 16 is as described in the ninth embodiment.

Moreover, as shown in FIG. 57, with the first electrode material film 5702 exposed, the first conductivity type impurities are obliquely ion-implanted to form a region at the end of the transfer electrode and below the electrode. It is possible to reliably form a diffusion layer that serves as a potential barrier, and since this diffusion layer is formed in a completely self-aligned manner with respect to the transfer electrode, as in the case where impurities are introduced using a mask, There is no possibility that the diffusion layer, which serves as a potential barrier, intrudes into the gap portion of the transfer electrode or below the adjacent electrode due to the misalignment between the transfer electrode and the implantation mask, thereby causing the deterioration of the transfer efficiency. Therefore, according to the manufacturing method of the present embodiment, the two-phase driving C having good transfer characteristics
The CD can be easily realized.

Reference numeral 5700 is a first conductivity type semiconductor substrate, 5701 is a first insulating film, 5712 is a second electrode material film, and 5715 is a second insulating film.

<Embodiment 23> Next, sectional views of a twenty-third embodiment of the present invention are shown in FIGS. 60 to 61 show a single-layer electrode structure in which a contact between a wiring and a transfer electrode is arranged on a transfer channel region and an impurity for forming a potential barrier is obliquely formed under one end of the transfer electrode. Two-phase drive CCD by ion implantation
It is another embodiment showing a manufacturing method for realizing.

The manufacturing method of this embodiment is basically the same as that shown in FIG.
34 to 36, but according to the manufacturing method of the sixteenth embodiment, the impurity ions for forming the potential barrier are obliquely formed on the film corresponding to the first electrode material film 3402 of FIG. The difference is that the driving is done.

A specific description will be given with reference to the drawings. FIG. 60 shows a structure corresponding to that of FIG. 34 of the sixteenth embodiment, but a diffusion layer of the first conductivity type is formed before depositing and forming the third electrode material film 6117 and the third insulating film 6119. Impurities to be implanted are obliquely ion-implanted from above the first electrode material film 6102 and introduced into the transfer channel diffusion layer of the second conductivity type to be activated to form a diffusion layer 6161 serving as a potential barrier against signal charges. The points are different.

Further, a spacer 6116 is formed from the third insulating film 6119, and using this as a mask, the first and third electrode material films 6102 and 6117 are cut and separated. At this time, as in the twenty-second embodiment, the diffusion layer 6 serving as a potential barrier is formed.
161 can be arranged below the first electrode material film 6102 that has been cut and separated. Finally, after depositing the interlayer insulating film 6104 and opening the contact hole 6110, the wiring 6
FIG. 61 is obtained by depositing and patterning 105.

In this embodiment, as in the twenty-second embodiment,
A diffusion layer serving as a potential barrier can be reliably formed at the end of the transfer electrode and in the region below the electrode, and since this diffusion layer is formed completely self-aligned with the transfer electrode,
The transfer efficiency is not deteriorated due to the misalignment between the transfer electrode and the implantation mask. Therefore, according to the manufacturing method of the present embodiment, it is possible to easily realize the two-phase driving CCD having good transfer characteristics. Further, since there is a region in which the interval between the transfer electrodes facing each other is widened by the width of the spacer 6116, the parasitic capacitance between the transfer electrodes is reduced, and the transfer electrode structure suitable for high speed driving is obtained.

6100 is a semiconductor substrate of the first conductivity type, 6190 is a transfer channel diffusion layer of the second conductivity type,
101 is a first insulating film, 6125 is an insulating diffusion / reaction preventing film, 6112 is a second electrode material film, 611
Reference numeral 5 indicates a second insulating film.

<Embodiment 24> Next, a plan view of a twenty-fourth embodiment of the present invention is shown in FIG.

FIG. 62 shows a single-layer electrode structure in which the contact between the wiring and the transfer electrode is arranged on the transfer channel region, and the signal charge in a certain row of the pixel matrix is sent to the horizontal CCD within the horizontal scanning period. A known driving method (this is disclosed in, for example, Japanese Patent Laid-Open No. 58-210663 (Japanese Patent Publication No. 63-38865)), a circuit for realizing a solid-state imaging device using a so-called Charge Sweep Device (CSD). The configuration is shown.

In this embodiment, for example, by using the electrode structure of the fifth embodiment of the present invention, the wiring and the transfer electrode are formed on the transfer channel region without increasing the number of masks under the single-layer electrode structure. By providing the contact holes, the high speed driving required for CSD can be performed by a simple process.

The following is a description with reference to the drawings. Transfer electrode 6200
Includes a diffusion / reaction preventing film and constitutes a unit pixel of one pixel and two electrodes together with the light receiving and accumulating portion 6201. The read signal charges are sequentially transferred through the transfer channel region 6202 by the vertical CCD constituted by the transfer electrode 6200 and sent to the horizontal CCD 6206. Here, the transfer electrodes forming the vertical CCD have a structure in which the electrodes do not overlap each other and are composed of one layer. Further, in the present embodiment, a certain specific row is selected and the signal charge is read out and the vertical C
A series of operations of transferring with a CD and sending it to the horizontal CCD 6206 is performed within the horizontal scanning period. Horizontal CCD 6206
Signal charges sent to the NTSC, PAL and HDT
It is transferred at a constant timing according to each TV system such as V, and is amplified by the output amplifier 6208. Vertical CC
The transfer electrode 6200 forming D is composed of a vertical drive pulse power supply circuit having a wiring for correctly applying a drive voltage pulse from the outside to the transfer electrode and having a row selection means, or is built in the element. Further, the horizontal drive circuit 6203 composed of a vertical drive pulse generation circuit having a row selection means, and the horizontal CCD 6206 has a horizontal drive whose main component is a wiring for correctly applying a drive voltage pulse from the outside to the transfer electrodes. It is driven by a horizontal drive circuit 6207 composed of a pulse drive circuit or a horizontal drive pulse generation circuit built in the element.

In the CSD method, in order to send the signal charges of a certain specific row to the horizontal CCD 6206 within the horizontal scanning period, it is necessary to transfer charges at a high speed in the vertical CCDs. The wiring 6211 also serving as the transfer electrode 62
00 through a contact hole 6210, and by using a low-resistance metal material such as Al or Al alloy-based material for the wiring 6211, the effective resistance of the transfer electrode can be significantly reduced. Therefore, the high speed driving required for the CSD method can be performed. Moreover, the transfer channel region 620 is not deteriorated without deteriorating the transfer efficiency of signal charges.
Since it is possible to arrange the contact hole 6210 on the second electrode, it is not necessary to arrange the contact hole in the transfer electrode (for example, the transfer electrode in the area shown by 6220 in FIG. 62) connecting the adjacent vertical CCDs, and It is also possible to narrow the width of the transfer electrode in this region to about the minimum processing size of the process used. As a result, as compared with a structure in which a contact hole is arranged on a transfer electrode in a portion where adjacent vertical CCDs are connected, as in the conventional example disclosed in JP-A-1-98258, the pixel opening There is an advantage that the reduction can be suppressed.

Therefore, with the structure of this embodiment, it is possible to realize a high-performance solid-state image pickup device using the CSD method, which has the feature that pixel independent reading is possible in principle and the saturation charge amount is large, by a simple process. You can

By using the shift register for the circuit for driving the transfer electrode, a vertical drive circuit which is simple and suitable for being built in the element can be constructed.

Further, in this embodiment, the single-layer electrode structure as in the fifth embodiment has been described as an example, but the transfer electrode structure of other embodiments may be used, and of course, the superposed electrode structure may be used. It goes without saying that it does not matter.

Further, in FIG. 62, the contact hole 62
Although 10 is arranged on all the transfer electrodes, contact holes 62 are provided within a range capable of high-speed driving required for CSD.
It is also possible to thin out 10 numbers.

The position of the gap between the wirings 6211 also serving as the light-shielding film is not limited to the position shown in FIG. 62, but in order to suppress smear noise due to light leakage, the transfer electrode 6200 is provided. It is desirable to be at a position other than just above the gap. Further, by setting the gap between the wirings 6211 also serving as the light shielding film to be λ / 2n or less (n is the refractive index of the insulating film embedded in the gap between the wirings, λ is the wavelength of incident light). It goes without saying that light can be suppressed from entering through the gap.

<Twenty-fifth Embodiment> A plan view of a twenty-fifth embodiment of the present invention is shown in FIG. FIG. 63 shows another example of the circuit configuration for realizing a solid-state imaging device using a CSD in which a contact between a wiring and a transfer electrode is arranged on a transfer channel region in a single-layer electrode structure.

This embodiment is basically similar to the twenty-fourth embodiment shown in FIG. 62, but the technical report of the Television Society (February 27, 1985), pages 31 to 31 Similar to the conventional example disclosed on page 36, the difference is that the transfer electrode has a one-pixel-one-electrode configuration.

Since this embodiment has a one-pixel one-electrode structure, as shown in, for example, the conventional example shown in FIG. 54 and FIG. 62 of the twenty-fourth embodiment, at very narrow intervals over a long distance. The transfer electrodes do not face each other. Therefore, the parasitic capacitance between the electrodes facing each other is eliminated, high-speed driving can be performed with less power consumption, and the probability of occurrence of a defect such as a short circuit between transfer electrodes is reduced.

Therefore, with the structure of this embodiment, a high-performance and low-power-consumption solid-state image pickup device using the CSD method, which is in principle capable of independent pixel readout and has a large saturation charge amount, is a simple process. Can be realized with high yield.

In the above-mentioned conventional example, the contact between the Al wiring and the transfer electrode is arranged on the transfer channel region and CS
Although the high-speed driving required for D has been realized, no special consideration is given to the influence on the charge transfer by disposing the contact between the Al wiring and the transfer electrode on the transfer channel region. Then, in order to improve the transfer efficiency, the drive method is devised to perform additional sweeping operations a plurality of times. On the other hand, in this embodiment, since the contact between the wiring and the transfer electrode can be arranged on the transfer channel region without adversely affecting the potential distribution inside the transfer channel, the driving method becomes complicated to improve the transfer efficiency. It has the advantage that it can be prevented.

Further, 6300 is a transfer electrode including a diffusion / reaction preventing film, 6301 is a light receiving and accumulating portion, 6302 is a transfer channel region, and 6303 is for applying a driving voltage pulse from the outside correctly to the transfer electrode. A vertical drive pulse feeding circuit having wiring as a component and having row selecting means, or a vertical drive circuit having a vertical drive pulse generating circuit having a row selecting means built in the element and 6306 is a horizontal CCD. 6307, a horizontal drive pulse feeding circuit having a wiring for correctly applying an external drive voltage pulse to the transfer electrode as a main component or a horizontal drive circuit including a horizontal drive pulse generating circuit incorporated in the element. Is an output amplifier, 6310 is a contact hole, and 6311 is a wiring also serving as a light shielding film.

<Twenty-sixth Embodiment> A plan view of a twenty-sixth embodiment of the present invention is shown in FIG. FIG. 64 shows another example of the circuit configuration for realizing a solid-state imaging device using a CSD in which a contact between a wiring and a transfer electrode is arranged on a transfer channel region in a single-layer electrode structure.

This embodiment is basically similar to the twenty-fifth embodiment shown in FIG. 63, but the adjacent vertical CCDs are
There is no transfer electrode layer connecting the electrodes, the transfer electrode 6400 including the diffusion / reaction prevention film is completely isolated from all the adjacent transfer electrodes, and the power supply to the transfer electrode also serves as a light shielding film. The difference is that it is performed only from 6411.

By constructing the transfer electrodes in this way, the parasitic capacitance of the transfer electrodes for connecting the adjacent vertical CCDs is eliminated, and higher speed driving becomes possible.
Further, since all the transfer electrodes have the same shape, unevenness is less likely to occur in the potential distribution in the transfer channel region, and deterioration of transfer efficiency is suppressed.

Therefore, with the structure of this embodiment, it is possible to realize a high-performance and low-power-consumption solid-state image pickup device using the CSD method with a simple process and a high yield.

Reference numeral 6401 denotes a light receiving / accumulating unit, and 6402
Is a transfer channel region, 6403 is a vertical drive pulse power supply circuit having a line for correctly applying an external drive voltage pulse to a transfer electrode as a constituent element, and having a row selection means, or built in an element, Further, a vertical drive circuit composed of a vertical drive pulse generation circuit having a row selection means, 6406 is a horizontal CCD, and 6407 is a horizontal drive circuit whose main component is a wire for correctly applying a drive voltage pulse from the outside to the transfer electrodes. Reference numeral 6408 denotes an output amplifier, and 6410 denotes a contact hole, which is a horizontal drive circuit including a drive pulse power supply circuit or a horizontal drive pulse generation circuit built in the element.

Further, it is also possible to apply to the twenty-fourth embodiment the structure as in this embodiment in which each transfer electrode is isolated and power is supplied only from the wiring also serving as the light shielding film. At this time, it is not necessary to limit the position of the wiring portion (6220 portion of FIG. 62) connecting the adjacent vertical CCDs by the wiring 6211 also serving as the light shielding film to the position shown in FIG. The two wirings 6211 at the portion 6220 are arranged so that the lengths of the wirings also serving as the light shielding film facing each other become small.
The intervals may be widened.

Furthermore, the structure shown in this embodiment in which each transfer electrode is isolated and power is supplied only from the wiring also serving as the light shielding film can be applied not only to the single-layer electrode structure but also to the superposed electrode structure. Furthermore, element configurations other than CSD (for example, interline elements, FIT elements, etc.)
Needless to say, the present invention can be applied to a one-pixel n-electrode structure (n ≧ 2).

<Twenty-seventh Embodiment> Next, plan views of a twenty-seventh embodiment of the present invention are shown in FIGS. 65 to 66 show a method of manufacturing a single-layer electrode structure in which each transfer electrode is completely isolated and formed as shown in FIG. 64, for example.

In this embodiment, the transfer electrode 6500 first forms a narrow gap 6501 on the transfer channel region 6502 (FIG. 65), and then the separation region 6503 of the adjacent vertical CCDs.
66 to form an opening on the light receiving and accumulating portion (FIG. 66). The manufacturing method of the conventional example disclosed in Japanese Patent Laid-Open No. 4-207076 is formed by completely isolating each transfer electrode. This is applied to the layer electrode structure.

By adopting such a manufacturing method, in the stage of FIG. 65, the pattern to be patterned becomes only the narrow gaps 6501 on the transfer channel which are arranged at equal intervals, and the resolution improving method such as the phase shift method can be easily performed. It will be applicable. Further, generally, in a resist pattern formed by photolithography, a radius of a minimum dimension is rounded at the corners of the pattern. However, by adopting the manufacturing method as in this embodiment, the pattern shown in FIGS. Either patterning results in a mask pattern having no corners in the pixel, so that this rounding can be prevented. As a result,
The narrow gap 6501 on the transfer channel is defined by the transfer electrode 6500.
Has a constant value in any part of the transfer electrode 6500.
Gap 650 on the transfer channel as it approaches the corners of
The interval of 1 does not become large. This effectively works to keep the areas of the opening and the transfer channel region 6502 as large as possible.

Therefore, a high-performance solid-state image pickup device can be easily realized by the manufacturing method of this embodiment.

Needless to say, the present invention can be applied to element structures other than CSD (for example, interline type elements, FIT type elements, etc.) and one pixel n-electrode structure (n ≧ 2).

<Embodiment 28> Next, a plan view of a twenty-eighth embodiment of the present invention is shown in FIG. FIG. 67 shows a single-layer electrode structure in which a contact between a wiring and a transfer electrode is arranged on a transfer channel region, a temporary storage region for signal charges is provided, and signal charges read from a pixel matrix are arranged within a vertical blanking period. The driving method is configured to transfer to this temporary storage area. For example, International Solid State Circuits Conference 1990, Digest of Technical Papers, pages 214 to 215 (International Solid-State Circuits C).
onference 1990, Digest of Technical Papers, p
p. 214-215), there is shown an embodiment of a circuit configuration based on a so-called FIT method, which is similar to the driving method of the conventional example disclosed in JP-A 214-215).

In this embodiment, similar to the twenty-fourth embodiment, for example, the electrode structure of the fifth embodiment of the present invention is used,
By providing a contact hole between the wiring and the transfer electrode on the transfer channel region without increasing the number of masks under the single-layer electrode structure, the high speed driving required for FIT can be performed by a simple process.

The following is a description with reference to the drawings. Transfer electrode 6700
Includes a diffusion / reaction prevention film, and constitutes a unit pixel of one pixel and two electrodes together with the light receiving and accumulating portion 6701. The read signal charges are sequentially transferred through the transfer channel area 6702 by the vertical CCD constituted by the transfer electrode 6700 and sent to the temporary storage area 6709. here,
The signal charge is transferred by the vertical CCD to temporarily store the area 6709.
The operation to send to is done within the vertical blanking period. The signal charge transferred to the temporary storage area 6709 is sent to the horizontal CCD 6706, transferred to the output amplifier 6708 at a constant timing according to each TV system such as NTSC, PAL, HDTV, etc., and amplified. The transfer electrode 6700 constituting the vertical CCD is a vertical drive pulse generating circuit built in a vertical drive pulse power supply circuit or an element whose main component is a wiring for correctly applying a drive voltage pulse from the outside to the transfer electrode. The horizontal drive circuit 6703 and the horizontal CCD 6706 have a horizontal drive pulse power supply circuit whose main component is a wiring for correctly applying an external drive voltage pulse to the transfer electrode or a horizontal drive incorporated in the element. It is driven by a horizontal drive circuit 6707 including a pulse generation circuit.

In the FIT system, in order to send the signal charge to the temporary storage area 6709 within the vertical blanking period, the vertical CC
Although it is necessary to transfer charges at D at a high speed, in this embodiment, the wiring 6711 also serving as a light-shielding film is connected to the transfer electrode 6700 through the contact hole 6711, and the wiring 6711 is connected to, for example, Al or an Al alloy. By using a low resistance metal material such as a system material, the effective resistance of the transfer electrode can be significantly reduced, and high-speed driving required for the FIT system can be performed. Moreover, since the contact hole 6710 can be arranged on the transfer channel region 6702 without deteriorating the transfer efficiency of the signal charges, it becomes easy to secure the opening.

Therefore, with the structure of this embodiment, a high-performance solid-state image pickup device using the FIT system, which has the feature that smear noise can be suppressed without lowering the sensitivity, can be realized by a simple process.

In this embodiment, the single-layer electrode structure as in the fifth embodiment has been described as an example. However, the transfer electrode structure of other embodiments may be used and, of course, the overlapping electrode structure may be used. It goes without saying that it does not matter.

Further, in FIG. 67, the contact hole 671
Although 0 is arranged on all the transfer electrodes, contact holes 67 are provided within a range capable of high-speed driving required for FIT.
It is also possible to thin out 10 numbers.

The position of the gap between the wirings 6711 also serving as the light-shielding film is not limited to the position shown in FIG. 67, but in order to suppress smear noise due to light leak, It is desirable to be at a position other than just above the gap. Further, the gap between the wires 6711 also serving as the light-shielding film is set to λ / 2n or less (n is the refractive index of the insulating film embedded in the gap between the wires, and λ is the wavelength of incident light). It goes without saying that light can be suppressed from entering through the gap.

Further, as in the twenty-sixth embodiment, the structure in which the transfer electrodes are completely isolated and the power is supplied only from the wiring also serving as the light-shielding film can be applied to this embodiment, and the parasitic capacitance can be applied. Can be reduced and higher speed driving can be performed.

<Twenty-Ninth Embodiment> A plan view of a twenty-ninth embodiment of the present invention is shown in FIG. FIG. 68 shows another example of the circuit configuration for realizing a solid-state imaging device using the FIT method, which has a single-layer electrode structure, in which the contact between the wiring and the transfer electrode is arranged on the transfer channel region. .

This embodiment is basically similar to the twenty-eighth embodiment shown in FIG. 67, but from, for example, International Solid State Circuits Conference 1990, Digest of Technical Papers, page 214. Page 215 (International Sol
id-State Circuits Conference 1990, Digestof T
echnical Papers, pp. 214-215), the difference is that the wiring 6811 also serving as a light-shielding film is arranged not in the horizontal direction but in the vertical direction, as in the configuration of the conventional example.

In the twenty-eighth embodiment shown in FIG. 67,
The wiring 6711 also serving as a light-shielding film on the wiring 6711 has a gap on the transfer electrode 6700, and this gap had to be narrowed to prevent light from leaking in. However, in this embodiment, the light-shielding film is used. By vertically arranging the wiring 6811 also serving as the wiring, it is possible to cover the transfer electrode 6800 with the wiring 6811 also serving as the light shielding film without a gap. For this reason,
A defect such as a short circuit between the wirings 6711 separated by a gap does not occur in this embodiment.

Therefore, with the structure of this embodiment, a high-performance solid-state image pickup device using the FIT system can be realized with a simple process and a high yield.

Reference numeral 6801 denotes a light receiving / accumulating unit, and 6802
Is a transfer channel region, and 6803 is a vertical drive pulse power supply circuit whose main constituent element is a wiring for correctly applying a drive voltage pulse from the outside to a transfer electrode or a vertical drive pulse generation circuit built in the element. A drive circuit, 6806 is a horizontal CCD, and 6807 is a horizontal drive pulse generation circuit built in a horizontal drive pulse power supply circuit or element whose main component is a wiring for correctly applying a drive voltage pulse from the outside to the transfer electrodes. Reference numeral 6808 denotes an output amplifier, 6809 denotes a temporary storage area, and 6810 denotes a contact hole.

Further, in the present embodiment, the single-layer electrode structure as in the fifth embodiment has been described as an example, but the transfer electrode structure of other embodiments may be used and, of course, the superposed electrode structure. It goes without saying that it does not matter.

Although FIG. 68 shows the contact hole arrangement (arrangement for every four transfer electrodes) in the case of four-phase drive, two-phase drive (arrangement for every two transfer electrodes) and three-phase drive are provided as necessary. (Arrangement of every three transfer electrodes) is also possible.

Further, in FIG. 68, the drive voltage of the transfer electrode 6800 is supplied from the side of the wiring 6811 also serving as the light shielding film, but in addition to this, the drive voltage is also supplied from the side of the transfer electrode 6800. However, this makes it possible to drive at a higher speed.

<Embodiment 30> Next, plan views of a thirtieth embodiment of the present invention are shown in FIGS. 69 to 70. 69 to 70 show another example of a circuit configuration for realizing a solid-state image sensor using a FIT, in which a contact between a wiring and a transfer electrode is arranged on a transfer channel region in a single-layer electrode structure. ing.

This embodiment basically complies with the twenty-eighth embodiment shown in FIG. 67, except that each pixel has one pixel and one electrode structure.

Since this embodiment has a one-pixel one-electrode structure, for example, as shown in FIG. 67 of the twenty-eighth embodiment,
Transfer electrodes 6900 with very close spacing over long distances
Never face each other. Therefore, the parasitic capacitance between the electrodes facing each other is eliminated, high-speed driving can be performed with less power consumption, and the probability of occurrence of a defect such as a short circuit between transfer electrodes is reduced.

Next, a method of driving the device of this embodiment will be described with reference to FIG. FIG. 70 schematically shows an FIT type image pickup device. Reference numeral 6901 denotes a light receiving / accumulating unit, 6920 denotes a vertical CCD, 6909 denotes a temporary storage area, 6906 denotes a horizontal CCD, and 6908 denotes an output amplifier. . Further, 1 to 8 represent row numbers of pixels.

First, in the case of pixel mixed reading, the following is performed.

By using four-phase driving and multiple readings, in the first field, rows 1 and 2, 3 and 4, 5 and 6, 7 and 8 are mixed and read into the temporary storage area 6909 by multiple readings. Forward. 1 for the first reading of multiple readings
And rows 2, 5, and 6 are mixed and read out and transferred, and rows 3 and 4, 7 and 8 are mixed and read out and transferred at the second time. In the second field, by shifting this by one line and performing the same operation, it is possible to read out a signal required for interlaced scanning in two fields. Temporary storage area 690
Since the signals transferred to 9 are not arranged in the order of the rows, for example, after the output amplifier 6908 is output, A / D conversion is performed and the signal is taken into the memory and converted into the original order. Of course, the order may be changed before the output amplifier 6908.

Next, the pixel independent reading is as follows.

Using n-phase driving (n is 2, 3, or 4) and multiple readings, multiple readings of n times are performed, and 1 / n of all rows are read at a time and temporarily read. Storage area
All pixels are independently read out n times while transferring to 6909. The n-th multiple reading is driven so that the (m + kn) th row (k is a positive integer) is read at the m-th reading (m is an integer from 1 to n). Since the signals do not line up in row order, for example, output amplifier 69
After the output from 08, A / D conversion is performed and the result is taken into the memory, and the original order is converted. Of course, the order may be changed before the output amplifier 6908.

As described above, with the structure of this embodiment, a high-performance solid-state image pickup device using the FIT system can be realized with a simple process and a high yield.

6902 designates a transfer channel area.
Reference numeral 903 denotes a vertical drive pulse feeding circuit having a wiring for correctly applying a drive voltage pulse from the outside to the transfer electrode as a main component or a vertical drive circuit including a vertical drive pulse generating circuit incorporated in the element. Horizontal CCD
Reference numeral 6907 denotes a horizontal drive pulse feeding circuit whose main constituent element is a wiring for correctly applying a drive voltage pulse from the outside to the transfer electrodes, or a horizontal drive circuit including a horizontal drive pulse generation circuit built in the element, Reference numeral 6910 indicates a contact hole, and reference numeral 6911 indicates a wiring which also serves as a light shielding film.

Further, as in the twenty-sixth embodiment, the structure in which the transfer electrodes are completely isolated and power is supplied only from the wiring also serving as the light-shielding film can be applied to this embodiment, and the parasitic capacitance can be applied. Can be reduced and higher speed driving can be performed.

Of the effects of the first to thirtieth embodiments described above, the portion related to the CCD is the semiconductor substrate or the diffusion layer in the semiconductor substrate described in these embodiments in order to realize the effect. It is not limited to the structure. For example, the first conductivity type semiconductor substrate may be replaced with the first conductivity type well in the second conductivity type semiconductor substrate, and a more complicated diffusion layer structure may be used. Further, the gate insulating film formed on the semiconductor substrate is not limited to the silicon oxide film, but may be a silicon nitride film or a composite film thereof, and they may be mixed in the same element.

[0258]

By using the structure and method of the present invention, the contact to the transfer electrode can be arranged on the transfer channel without adversely affecting the charge transfer of the CCD, and the wiring material has low resistance. It is possible to use an Al-based material. The increase in the number of masks at this time is 0 or 1. The process is less complicated. Therefore, by using the structure and method of the present invention, it is possible to easily form the transfer electrodes of the CCD which can be driven at a very high speed, and it is possible to make a high-performance CCD image pickup device at a low cost and a high yield. it can.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 shows Al wiring and C using a connection layer of polycrystalline silicon.
FIG. 10 is a plan view of a conventional example of a solid-state image pickup device which is in contact with a transfer electrode of a CD.

FIG. 3 is a sectional view of a second embodiment of the present invention.

FIG. 4 is a sectional view of a third embodiment of the present invention.

FIG. 5 is a sectional view of a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a fifth embodiment of the present invention.

FIG. 7 is a sectional view of a fifth embodiment of the present invention.

FIG. 8 is a sectional view of a fifth embodiment of the present invention.

FIG. 9 is a sectional view of a fifth embodiment of the present invention.

FIG. 10 is a sectional view of a sixth embodiment of the present invention.

FIG. 11 is a sectional view of a sixth embodiment of the present invention.

FIG. 12 is a sectional view of a sixth embodiment of the present invention.

FIG. 13 is a sectional view of a seventh embodiment of the present invention.

FIG. 14 is a sectional view of an eighth embodiment of the present invention.

FIG. 15 is a sectional view of a ninth embodiment of the present invention.

FIG. 16 is a sectional view of a tenth embodiment of the present invention.

FIG. 17 is a sectional view of an eleventh embodiment of the present invention.

FIG. 18 is a sectional view of a twelfth embodiment of the present invention.

FIG. 19 is a sectional view of a twelfth embodiment of the present invention.

FIG. 20 is a sectional view of a twelfth embodiment of the present invention.

FIG. 21 is a sectional view of a twelfth embodiment of the present invention.

FIG. 22 is a sectional view of a twelfth embodiment of the present invention.

FIG. 23 is a sectional view of a thirteenth embodiment of the present invention.

FIG. 24 is a sectional view of a thirteenth embodiment of the present invention.

FIG. 25 is a sectional view of a thirteenth embodiment of the present invention.

FIG. 26 is a sectional view of a fourteenth embodiment of the present invention.

FIG. 27 is a sectional view of a fourteenth embodiment of the present invention.

FIG. 28 is a sectional view of a fourteenth embodiment of the present invention.

FIG. 29 is a sectional view of a fifteenth embodiment of the present invention.

FIG. 30 is a sectional view of the fifteenth embodiment of the present invention.

FIG. 31 is a sectional view of a fifteenth embodiment of the present invention.

FIG. 32 is a sectional view of the fifteenth embodiment of the present invention.

FIG. 33 is a sectional view of the fifteenth embodiment of the present invention.

FIG. 34 is a sectional view of a sixteenth embodiment of the present invention.

FIG. 35 is a sectional view of a sixteenth embodiment of the present invention.

FIG. 36 is a sectional view of a sixteenth embodiment of the present invention.

FIG. 37 is a sectional view of a seventeenth embodiment of the present invention.

FIG. 38 is a sectional view of an eighteenth embodiment of the present invention.

FIG. 39 is a sectional view of an eighteenth embodiment of the present invention.

FIG. 40 is a sectional view of an eighteenth embodiment of the present invention.

FIG. 41 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 42 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 43 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 44 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 45 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 46 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 47 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 48 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 49 is a sectional view of a nineteenth embodiment of the present invention.

FIG. 50 is a cross-sectional view of an example in which the position of the contact between the transfer electrode and the wiring is arranged in the center of the transfer electrode.

FIG. 51 is an explanatory diagram showing a potential change in a transfer channel in an example in which a contact position between a transfer electrode and a wiring is arranged in a central portion of the transfer electrode.

FIG. 52 is a sectional view of a twentieth embodiment of the present invention.

FIG. 53 is an explanatory diagram showing potential changes in the transfer channel according to the twentieth embodiment of the present invention.

FIG. 54 is a plan view of a conventional example of a pixel portion having a one-pixel / two-electrode structure including a vertical CCD having a single-layer electrode structure.

FIG. 55 is a plan view of a twenty-first embodiment of the present invention.

FIG. 56 is a sectional view of a twenty-second embodiment of the present invention.

FIG. 57 is a sectional view of a twenty-second embodiment of the present invention.

FIG. 58 is a sectional view of a twenty-second embodiment of the present invention.

FIG. 59 is a sectional view of a twenty-second embodiment of the present invention.

FIG. 60 is a sectional view of a twenty-third embodiment of the present invention.

FIG. 61 is a sectional view of a twenty-third embodiment of the present invention.

FIG. 62 is a plan view of the twenty-fourth embodiment of the present invention.

FIG. 63 is a plan view of a twenty-fifth embodiment of the present invention.

FIG. 64 is a plan view of a twenty-sixth embodiment of the present invention.

FIG. 65 is a plan view of a twenty-sixth embodiment of the present invention.

FIG. 66 is a plan view of a twenty-seventh embodiment of the present invention.

FIG. 67 is a plan view of a twenty-eighth embodiment of the present invention.

68 is a plan view of the twenty-ninth embodiment of the present invention. FIG.

FIG. 69 is a plan view of the thirtieth embodiment of the present invention.

FIG. 70 is a plan view of the thirtieth embodiment of the present invention.

[Explanation of symbols]

100 ... First conductivity type semiconductor substrate, 101 ... Insulating film, 1
02 ... first electrode material film, 103 ... second electrode material film,
120 ... First conductive diffusion / reaction prevention film, 121 ...
Second conductive diffusion / reaction preventing film, 106 ... First interlayer insulating film, 104 ... Second interlayer insulating film, 105 ... Wiring, 1
10 ... Contact hole.

Continuation of the front page (56) Reference JP-A-5-48069 (JP, A) JP-A-2-5473 (JP, A) JP-A-5-145855 (JP, A) JP-A-2-234126 (JP , A) JP-A-5-315588 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/14-27/148 H01L 21/28 H01L 21/768 H04N 5/335

Claims (6)

(57) [Claims] 1. A plurality of light receiving and accumulating portions formed on a semiconductor substrate to photoelectrically convert incident light to generate signal charges, a charge-coupled device for transferring the signal charges, and a signal voltage for the signal charges. an output amplifier for converting, in the solid-state imaging device comprising a wiring connected to the transfer electrodes of the charge-coupled device in the contact areas on the transfer channel region of the charge-coupled device, in the contact area, the transfer electrostatic
The film forming the top of the pole or the top of the transfer electrode
A conductive material that prevents the diffusion of the material of the wiring or the reaction with the material of the wiring in the film forming the intermediate portion with the insulating film.
The solid-state imaging device characterized that you configured by. 2. The wiring material is Al or Al alloy-based material
And the conductive material is W, Ti, Mo or its
Characterized by being a silicide or a composite film thereof
The solid-state imaging device according to claim 1. 3. The transfer electrode is composed of a single layer.
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is a characteristic. 4. Diffusion of the material of the wiring or of the wiring
Before constructed of conductive material to prevent reaction with the material
The side wall of the film forming the uppermost part of the transfer electrode composed of a single layer
Or diffusion of the material of the wiring or material of the wiring
The single element made of a conductive material that prevents reaction with
Between the top of the transfer electrode consisting of one layer and the gate insulating film
It forms the uppermost part made up of the film and electrode material that form the interstitial part.
Insulating spacers are formed on the sidewalls of the film in a self-aligned manner.
The solid-state imaging device according to claim 3, wherein 5. The light receiving and accumulating units are arranged two-dimensionally,
The charge-coupled device vertically transmits the signal charge from the light receiving and accumulating portion.
A vertical charge-coupled device for transferring in the direction
The line is perpendicular to the signal charge transfer direction of the vertical charge coupled device.
Arranged to extend straight And the vertical of the wiring
The gap on the charge-coupled device is the same as that of the vertical charge-coupled device.
Of the transfer electrode composed of layers
The solid-state imaging device according to claim 3, wherein 6. A transfer electrode of the vertical charge-coupled device is a light-receiving device.
Characterized by one electrode per stack
The solid-state imaging device according to claim 5.