JP3393445B2 - Chroma signal processing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates also relates to a signal processing circuits of the chroma signal in the camera signal processing, in particular, R, G, B
Of about the appropriate signal processing circuits is used as the chroma signal processing circuit forming the signal processing on the two color difference signals generated from the three primary color signals.

[0002]

2. Description of the Related Art A conventional chroma signal processing circuit to which this type of signal processing circuit is applied is shown in FIG. In the figure, two color difference signals having a data rate of, for example, 4 fsc (fsc: color subcarrier frequency), which are obtained by generating from the three primary color signals of R, G, B in the chroma matrix circuit 4, that is, (RY) , (BY) signals are input to low-pass filters (LPF) 11 and 12. The low-pass filters 11 and 12 perform filtering for decimation processing at a data rate of 2 fsc. Here, the decimation process means an operation process for lowering the sampling frequency in the signal processing system.

The (R-Y) and (B-Y) signals that have passed through the low-pass filters 11 and 12, respectively, are subjected to decimation processing by being sequentially switched and selected by the select switch 13 in synchronization with the clock of 2 fsc. It By this decimation process, 2 fsc (≈7 MH
The (R-Y) and (B-Y) signals having the data rate of z) are sent to the low-pass filter 14 of the next stage at a clock rate of 4 fsc (≈14 MHz) as a dot sequence. FIG. 7 shows a processing concept between bits in the decimation processing and the filtering processing.

As is clear from FIG. 7, in the decimation process, data is thinned out every other bit for the (RY) and (BY) signals, and the data thinned out by one color difference signal. By inserting the data of another color difference signal on the time axis at the place, the (R
-Y), (B-Y) signals to (R- of 2fsc data rate
Y) / (BY) dot-sequential signals are processed. In addition, in FIG. 7, the frequency of the data transfer clock of the output signal is shown as 4 fsc, but the actual data is 2 fsc.
Decimation processing to the data rate of (RY)
/ (BY) dot sequential signal. Further, it is premised that the number of tap coefficients for filtering is seven.

[0005]

However, in the conventional signal processing circuit having the above-mentioned configuration, for the (RY) and (BY) signals having the data rate of 4 fsc, the signal band up to the data rate of 2 fsc, respectively. Limit (about 3.5MHz
Band limitation), and thereafter, as is clear from FIG. 7, the (RY) and (BY) signals are thinned out to (RY) /
Since the decimation process is performed by using the (BY) point sequential signal, it is necessary to use the two low-pass filters 11 and 12 corresponding to the two color difference signals, which increases the circuit scale. There was a problem. The present invention has been made in view of the above problems,
And an object thereof is to provide a signal processing circuitry of the chroma signal which enables the circuit scale.

[0006]

A signal processing circuit for a chroma signal according to the present invention produces 2 signals obtained from 3 primary color signals.
A decimation circuit for synchronizing two color-difference signals and switching them in synchronization with a sampling clock of a predetermined frequency to output as a dot-sequential signal , and n bits (n
Is a natural number) and a filter circuit for adding the tap coefficient and multiplying the tap coefficient is added. And deshimei
Is a single-stage delay circuit that delays one of the two color difference signals.
A first delay circuit including a 1-bit latch circuit and 2
Two cascading cascades that delay the other of the two color difference signals
A second delay circuit including a latch circuit and a first delay circuit
The input of the 1-bit latch circuit of the delay circuit and the second
The output of the 1-bit latch circuit in the first stage of the ray circuit
The first to switch and output in synchronization with the pulling clock
Select circuit and 1-bit latch of the first delay circuit
The output of the circuit and the 1st bit of the second stage of the second delay circuit
Switch circuit output is switched in synchronization with the sampling clock.
The second select circuit that exchanges the output and the first select circuit
M stages (m = (n-1) / 2) vertically for delaying the output of the output circuit
A third delay circuit including a 2-bit latch circuit connected in series.
Delay the output of the B circuit and the second select circuit (m-
1) 4th consisting of 2-bit latch circuits connected in cascade
Of the first and second select circuits.
2 bits for each output and each stage of the third and fourth delay circuits
A structure for outputting each output of the latch circuit as the dot-sequential signal
It has become successful.

[0007]

In the signal processing circuit having the above structure, R, G, B
Two color difference signals generated from the signal are latched 1 bit
Was first synchronization with the delay circuit composed of the road, the two color difference signals this is synchronized with the two selector circuits
By switching and selecting with a sampling clock of a predetermined frequency, a decimation process is performed to obtain a dot-sequential signal. Then, the filtering process is performed by multiplying each n bits of the color difference signal in the dot-sequential signal by the tap coefficient and adding them. Here, the value of n is determined by the number of tap coefficients at the time of filtering.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. Figure 1 is a block diagram showing a chroma signal processing circuit for signal processing <br/> circuit is applied in an embodiment according to the present invention. In the figure, the three primary color signals of R, G, B are color adjusted by the white balance circuits 1R, 1G, 1B,
After being γ-corrected by the γ-correction circuits 2R, 2G and 2B,
It is supplied to the chroma matrix circuit 4 through the white clip circuits 3R, 3G, 3B. Chroma matrix circuit 4
Generates two color difference signals having a data rate of 4 fsc, that is, (RY) and (BY) signals from the R, G, and B primary color signals and supplies them to the band limiting circuit 5.

The band limiting circuit 5 is the most characteristic part of the present invention, and has a circuit configuration for collectively performing the decimation process and the filtering process on the chroma signal. In this decimation process, (RY),
Data is thinned out every other bit with respect to the (BY) signal, and the same color difference signal data is inserted on the time axis at the location of the data thinned out by one color difference signal.
A process of converting (RY) and (BY) signals having a data rate of 4fsc into (RY) / (BY) point sequential signals having a data rate of 2fsc is performed. Therefore, it is not necessary to perform filtering processing on the thinned data. The present invention has been made paying attention to this point.

FIG. 2 is a block diagram showing an example of the structure of the band limiting circuit 5. In the figure, the (RY) signal is 6
1-bit latch circuits 22 _{1 to} 22 ₇ are input to the delay circuit 21, which is composed of 1-bit latches 21 _{1 to} 21 ₆ connected in cascade, and the (BY) signal is cascade-connected in 7 stages.
The color difference signals are synchronized in the horizontal direction by being input to the delay circuit 22 consisting of. That is, the synchronization is performed in anticipation of the phase relationship of the respective signals after the decimation in the latter stage. The number of 1-bit latch circuits of the delay circuits 21 and 22 is determined by the number of tap coefficients (7 in this example) forming the low-pass filter 24 in the subsequent stage.

Input of the 1-bit latch circuit 21 ₁ of the first stage of the delay circuit 21 and the 1-bit latch circuit 21 of each stage
Each output of ₁ to 21 ₆ constituting the select circuit 23 7
It becomes one input of the individual selectors 23 ₁ to 23 ₇ . On the other hand, the seven 1-bit latch circuits 22 ₁ to 2 of the delay circuit 22
Each output of 2 ₇ is supplied to each selector 23 _{1 of the} select circuit 23.
It becomes another input of ~ 23 ₇ . Each selector 23 _{1-23 7} select circuit 23, while in synchronization with the sampling clock of 2fsc (≒ 7MHz) (R- Y), and outputs the switched alternately (B-Y) signal.

The delay circuits 21 and 22 and the select circuit 23 constitute a decimation circuit, and by this decimation circuit, horizontal 7 bits are synchronized on the time axis and subjected to decimation processing.
-Y) / (BY) dot sequential signals are obtained. The seven (RY) / (BY) point sequential signals are supplied to the low pass filter 24. In the low-pass filter 24, 7 bits are simultaneously selected in the horizontal direction (RY).
A low-pass filter 24 for the / (BY) point sequential signal.
The filtering process is performed by multiplying the seven tap coefficients constituting the above by the coefficient unit 25 and then adding them by the adder 26.

FIG. 3 shows a concept of processing between bits in the decimation and filtering. In addition,
In this conceptual diagram, the frequency of the data transfer clock of the output signal is shown as 4 fsc, but the actual data is 2 fsc.
Decimated to fsc data rate (RY)
/ (BY) dot sequential signal. As described above, in the band limiting circuit 5, 4 generated from the R, G, B signals
Simultaneous (RY) and (BY) signals of fsc data rate and (RY) / (BY) of 2 fsc data rate
By adopting a circuit configuration that performs the decimation process and the filtering process on the dot-sequential signal, there is no need to separately provide a low-pass filter for the (RY) and (BY) signals as in the conventional circuit. Since only one circuit is required, the circuit scale can be reduced.

FIG. 4 is a block diagram showing another configuration example of the band limiting circuit 5. In this example, considering that the phase relationship of each point-sequential signal after the decimation by the signal output of the subsequent stage is the same, the (R-Y) signal is converted by the 1-bit latch circuit 31 by 1 bit, The -Y) signal is delayed by 2 bits by the 1-bit latch circuits 32 and 33 in the two-stage cascade connection, and the (RY) and (BY) signals are initially synchronized by 2 bits in the horizontal direction. . This synchronized 2-bit signal, that is, the input and output of the 1-bit latch circuit 31 becomes one input of each of the select circuits 34 and 35.
The input and the output of the 1-bit latch circuit 33 of the stage become the other inputs of the select circuits 34 and 35. The select circuits 34 and 35 switch between the (RY) and (BY) signals in synchronization with the sampling clock of 2 fsc (≈7 MHz) to select the 2 fsc data rate.
Two (RY) / (BY) dot sequential signals are output.

One of the two (RY) / (BY) point sequential signals, that is, the output of the select circuit 34, is divided into two bits by two-bit latch circuits 36, 37 and 38 which are cascaded in three stages. Each is delayed. Also, two (RY) / (B
-Y) The other of the dot-sequential signals, that is, the output of the select circuit 35 is connected to the 2-bit latch circuits 39 and 40 which are cascade-connected in two stages.
Is delayed by 2 bits each. The 1-bit latch circuits 31 to 33, the select circuits 34 and 35, and the 2-bit latch circuits 36 to 40 constitute a decimation circuit. In the decimation circuit, the select circuit 3
As the output of 4 and the outputs of the 2-bit latch circuits 36, 37, 38, and the output of the select circuit 35 and the outputs of the 2-bit latch circuits 39, 40, horizontal 7 bits are synchronized on the time axis. Two (RY) / (BY) point sequential signals are obtained.

In this way, seven (R-Y) and (B-Y) signals having a 2fsc data rate, which are obtained by performing simultaneous decimation processing on the (RY) and (BY) signals having a 4fsc data rate, are obtained.
The −Y) / (B−Y) point sequential signal is supplied to the low-pass filter 24 for filtering processing, as in the configuration example of FIG. 2. According to this configuration example, in order to synchronize and decimate horizontal 7 bits on the time axis, in the case of the configuration example of FIG. 2, seven selectors 23 ₁ to 2 are used.
While it is necessary to use 3 ₇ , it is only necessary to use the two select circuits 34 and 35, so that the circuit scale can be further reduced.

Referring again to FIG. 1, on the output side of the band limiting circuit 5, two low pass filters 6 having different pass band characteristics are provided so that the chroma signal output has two different output band characteristics. 7 is provided. Then, it passed through both low pass filters 6 and 7 (R
-Y) / (B-Y) dot sequential signal is output to the select switch 8
Either one is selected by and output. Now 2
As one output band characteristic, for the luminance signal of the (4fsc / 2) band, the first output band characteristic for giving the chroma signal a (2fsc / 2) band and for the luminance signal of the (4fsc / 2) band Second to give (fsc / 2) band to chroma signal
The output band characteristics of and are set.

Here, as an example, the transfer function H1a (z) of the filter for obtaining the first output band characteristic is

H1a (Z) = (1 + 2Z ^-1 + Z ^-2 ) (1 + 2Z ^-1 + Z ^-2 ) (3 + 2Z ^-1 + 3Z ^-2 ) (-1 + 6Z ^-2 -Z ^-4 ) (1 + Z ^-2 ) The transfer function H2a (z) of the filter for obtaining the second output band characteristic is

H2a (Z) = (1 + 2Z ^-1 + Z ^-2 ) (1 + 2Z ^-1 + Z ^-2 ) (3 + 2Z ^-1 + 3Z ^-2 ) (-1 + 6Z ^-4 -Z ^-8 ) (1 + Z ^-2 ) (1 + Z) ^-2 ) (3 + 2Z ^-2 + 3Z ^-4 ). In order to obtain these two output band characteristics, the low pass filter 24 and the two low pass filters 6 and 7 of the band limiting circuit 5 can be generally configured as follows.

That is, the transfer function H11 (Z) of the low-pass filter 24 is

[Equation 3] H11 (Z) = (1 + 2Z ⁻¹ + Z ⁻² ) (1 + 2Z ⁻¹ + Z ⁻² ) (3 + 2Z ⁻¹ + 3Z ⁻² ), and the transfer function H12 (Z) of the low-pass filter 6 is

## EQU00004 ## H12 (Z) = (-1 + 6Z- ² -Z- ⁴ ) (1 + Z- ² ) and the transfer function H13 (Z) of the low pass filter 7 is

[Formula 5] H13 (Z) = (-1 + 6Z- ^4- Z- ⁸ ) (1 + Z- ² ) (1 + Z- ² ) (3 + 2Z- ² + 3Z- ⁴ ). Here, focusing on both transfer functions H12 (Z) and H13 (Z) of the low-pass filters 6 and 7, it can be seen that the same term (1 + Z ^-2 ) is applied separately to both low-pass filters 6 and 7. .

In the present embodiment, paying attention to this point, the term (1 + Z ⁻² ) common to the low-pass filters 6 and 7 is given to the low-pass filter 24 of the band limiting circuit 5 so as to be common, thereby reducing the circuit scale. We are trying to reduce the size. That is, the transfer function H21 (Z) of the low pass filter 24 is

[Equation 6] H21 (Z) = (1 + 2Z ⁻¹ + Z ⁻² ) (1 + 2Z ⁻¹ + Z ⁻² ) (3 + 2Z ⁻¹ + 3Z ⁻² ) (1 + Z ⁻² ), and the transfer function H22 (Z) of the low pass filter 6 is obtained. To

[Equation 7] H22 (Z) = (-1 + 6Z ^-2 -Z ^-4 ) and the transfer function H23 (Z) of the low-pass filter 7 is

## EQU8 ## H13 (Z) = (-1 + 6Z- ⁴ -Z- ⁸ ) (1 + Z- ² ) (3 + 2Z- ² + 3Z- ⁴ ).

Here, each coefficient obtained by factorizing the equation of the equation 6 corresponds to the tap coefficient in the low pass filter 24 of the band limiting circuit 5. In this way, when giving two output band characteristics to the chroma signal, the same circuit configuration (the low pass filter 24 of the band limiting circuit 5) is used up to the middle of the low pass filter and then branched to separate circuit configurations. By using (low-pass filters 6, 7), a part of the filter circuit can be shared, and the circuit scale can be reduced.

As another example, the transfer function H1b (z) of the filter for obtaining the first output band characteristic is

[Equation 9] H1b (Z) = (1 + 2Z ⁻¹ + Z ⁻² ) (1 + 2Z ⁻¹ + Z ⁻² ) (3 + 2Z ⁻¹ + 3Z ⁻² ), and the transfer function H2b of the filter for obtaining the second output band characteristic (z)

H2b (Z) = (1 + 2Z ^-1 + Z ^-2 ) (1 + 2Z ^-1 + Z ^-2 ) (3 + 2Z ^-1 + 3Z ^-2 ) (-1 + 6Z ^-4 -Z ^-8 ) (1 + Z ^-2 ) (3 + 2Z) Consider the case of ^-2 + 3Z ^-4 ). In this case, the transfer function H2b (z) of the filter for obtaining the second output band characteristic is the transfer function H1b (z) of the filter for obtaining the first output band characteristic.
Will be completely included.

Therefore, as shown in FIG. 5, the system in which the low-pass filter 6 in FIG. 1 is omitted and the output of the band limiting circuit 5 is directly selected by the select switch 8 and the system in which the output is selected after passing through the low-pass filter 7 are selected. And the transfer function H31 (Z) of the low-pass filter 24 of the band limiting circuit 5 is

H31 (Z) = (1 + 2Z ⁻¹ + Z ⁻² ) (1 + 2Z ⁻¹ + Z ⁻² ) (3 + 2Z ⁻¹ + 3Z ⁻² ), and the transfer function H33 (Z) of the low pass filter 7 is

## EQU12 ## H33 (Z) = (-1 + 6Z- ^4- Z- ⁸ ) (1 + Z- ² ) (3 + 2Z- ² + 3Z- ⁴ ). By doing so, the circuit scale can be further reduced by the amount that one low-pass filter can be omitted.

[0024]

As described above, according to the present invention,
The two color difference signals generated from the R, G, and B primary color signals are previously synchronized by using a delay circuit including a 1-bit latch circuit, and the two synchronized color difference signals are combined into two signals .
A dot sequential signal is obtained by performing decimation processing by switching with a sampling clock of a predetermined frequency using a selector circuit, and each of the color difference signals in this dot sequential signal is n.
By adopting a configuration in which bits are multiplied by tap coefficients and added to perform filtering, it is not necessary to separately provide a low-pass filter for two color difference signals as in the conventional circuit, and only one circuit is required. Deci
Since the circuit configuration of the metation circuit can be simplified , the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a chroma signal processing circuit to which a band limiting circuit according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a band limiting circuit.

FIG. 3 is a conceptual diagram of processing between bits during decimation and filtering according to the present invention.

FIG. 4 is a block diagram showing another configuration example of the band limiting circuit.

FIG. 5 is a block diagram showing a chroma signal processing circuit to which a band limiting circuit of another embodiment according to the present invention is applied.

FIG. 6 is a block diagram showing a chroma signal processing circuit according to a conventional example.

FIG. 7 is a conceptual diagram of processing between bits at the time of decimation and filtering in the conventional example.

[Explanation of symbols]

4 Chroma Matrix Circuit 5 Band Limiting Circuits ₆ , ₇ , 24 Low Pass Filter (LPF) 8 Select Switches 21, 22 Delay Circuits 21 _{1 to} 21 ₆ , 22 _{1 to} 22 ₇ , 31 to 33 1 Bit Latch Circuit 23 , 34, 35 Select circuit 23 ₁ to 23 ₇ Selector 36 to 40 2 bit latch circuit

Claims (3)

(57) [Claims] 1. A decimation circuit for synchronizing two color difference signals generated from three primary color signals and switching them in synchronization with a sampling clock of a predetermined frequency to output as a dot-sequential signal, and an output from the decimation circuit. A decimation circuit delays one of the two color difference signals by multiplying n bits (n is a natural number) of each of the color difference signals in the dot-sequential signal by a tap coefficient and adding them. A first delay circuit including a one-stage 1-bit latch circuit; a second delay circuit including two-stage cascade-connected 1-bit latch circuits for delaying the other of the two color difference signals; and the first delay circuit. The input of the 1-bit latch circuit of the circuit and the output of the 1-bit latch circuit of the first stage of the second delay circuit are synchronized with the sampling clock. The output of the 1-bit latch circuit of the first delay circuit and the output of the 1-bit latch circuit of the second stage of the second delay circuit as the sampling clock. A second select circuit for switching and outputting in synchronization, and m stages (m = m) for delaying the output of the first select circuit.
(N-1) / 2) A third delay circuit composed of cascaded 2-bit latch circuits, and an (m-1) -stage cascaded 2-bit latch circuit for delaying the output of the second select circuit. And a fourth delay circuit including the outputs of the first and second select circuits and the third and third delay circuits.
A signal processing circuit for a chroma signal, wherein each output of the 2-bit latch circuit of each stage of the fourth delay circuit is output as the dot sequential signal. 2. When the output signal of the filter circuit has two different output band characteristics, the first transfer function of the filter for obtaining one output band characteristic and the other output band characteristic are When the second transfer function of the filter for obtaining is partly common, the common transfer function is provided to the filter circuit, and a part of the first transfer function different from the second transfer function is provided. A first low-pass filter having a transfer function and receiving the output signal of the filter circuit as an input; and a transfer function of a portion of the second transfer function different from the first transfer function, the output signal of the filter circuit Further comprising a second low-pass filter for receiving the input signal and a selecting means for selecting one of the output signals of the first and second low-pass filters. The signal processing circuit according to claim 1 chroma signal according. 3. When the output signal of the filter circuit is provided with two different output band characteristics, the first transfer function of the filter for obtaining one output band characteristic changes the other output band characteristic. When the second transfer function of the filter for obtaining is completely included, the filter circuit is provided with the second transfer function, and the transfer of a portion different from the second transfer function of the first transfer function It further comprises a low-pass filter having a function and having the output signal of the filter circuit as an input, and a selection means for selecting one of the output signal of the filter circuit and the output signal of the low-pass filter. A signal processing circuit for a chroma signal according to claim 1 .