JP3392726B2 - Data receiving device and data receiving method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus and a data receiving method used for digital mobile communication and the like, and more particularly to a data receiving apparatus and a data receiving method in which a calculation time for demodulating a received signal is shortened.

[0002]

2. Description of the Related Art A conventional data receiving apparatus is disclosed in
The signal processing device disclosed in Japanese Patent Laid-Open No. 6-110860 will be described as an example. Of the signal processing device described in the above publication, FIG. 4 shows a relevant part applicable to signal processing in a data receiving device. In FIG. 4, A-1 is an input terminal, and A-2 is an addition / power calculation function unit that adds a constant from an input signal and calculates a power to the addition result.

Next, the operation of the above conventional example will be described.
First, when the input signal x is input to A-1, a certain constant c is added, and the addition result (x + c) is output terminal A-3-1 and the multiplier A- in the addition / power calculation function unit A-2. It outputs to the input B of 2-1 and the input A of the multipliers A-2-1 to A-2-n. The multiplier A-2-1 is
Input A (x + c) and input B (x + c) are multiplied,
As a result, (x + c) ² is output to the output terminal A-3-2 and the multiplier A-2-2.
Output to input B of. The multiplier A-2-2 has an input A (x +
c) and the input B (x + c) ² are multiplied, and the result (x + c) ³ is output terminal A-3-3 and the input B of the multiplier A-2-3.
Output to. This is repeated up to the multiplier A-2-n.

As described above, also in the above-mentioned conventional signal processing apparatus, by configuring the systolic array, it is possible to shorten the time until a desired calculation result is obtained.

[0005]

However, in the conventional signal processing apparatus, the computations that can form the systolic array and reduce the computation time are limited to the computations without feedback. However, in the sequential calculation used in digital signal processing such as demodulation processing in digital mobile communication, there are many cases in which a certain calculation result is fed back to the calculation in the previous stage. That is, in the calculation including such feedback elements, there is a problem that the systolic array cannot be constructed and the time until a desired calculation result is obtained becomes long.

The present invention solves such a conventional problem, and by applying the configuration of the systolic array to the operation including the feedback element, the time until the desired operation result is obtained can be shortened. An object is to provide a data receiving device.

[0007]

In order to achieve the above object, the present invention calculates in advance all patterns of parameters to be fed back, and selects one of the calculation results according to the fed back parameters. The configuration of the systolic array can be applied to operations including feedback elements.

With this configuration, it is possible to realize a data receiving apparatus that shortens the time required to obtain a desired calculation result.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention is
An operation A section that performs the operation A for all patterns of parameters required to perform a predetermined operation A and an input signal set; an operation B section that calculates the parameter from the result of the operation A section; The result of the operation A section is selected based on the parameter of the result of the B section, and the operation B is selected.
The data receiving device is provided with a switch for inputting to the unit, and has an effect of shortening the time until a desired output is obtained.

The invention according to claim 2 of the present invention holds the result of performing the operation A in advance for all the combinations of the patterns of the parameters necessary for performing the predetermined operation A and all the patterns of the input signal. A data receiving device including a memory, an operation B unit that calculates the parameter from the result of the operation A, and an address generation unit that generates an address of the memory from the parameter of the result of the operation B unit and the input signal. This has the effect of shortening the time until a desired output is obtained.

According to a third aspect of the present invention, the operation A is performed for all patterns of parameters required for performing the predetermined operation A and a set of input signals, and a predetermined operation is performed for the result of the operation A. B is performed, the parameter is calculated, and the result of the operation A is selected by a switch based on the parameter of the result of the operation B to be the input of the operation B, and a desired output is obtained. It has the effect of shortening the time until.

According to a fourth aspect of the present invention, the result obtained by previously performing the operation A for a set of all the patterns of parameters necessary for performing the predetermined operation A and all the patterns of the input signal is stored in a memory. Hold, perform a predetermined operation B on the result of the operation A to calculate the parameter, generate an address of the memory from the parameter of the result of the operation B and the input signal, and access the memory at the address This is a data receiving method of reading the result of the operation A and inputting it to the operation B, and has the effect of shortening the time until a desired output is obtained.

FIG. 1 shows an embodiment of the present invention.
~ It demonstrates in detail with reference to FIG.

(First Embodiment) In the first embodiment of the present invention, an operation A section for performing operation on all patterns of parameters required to perform a certain operation A, and an operation A
The data receiving apparatus includes an operation B unit that calculates the next parameter from the result of 1) and a switch that selects the result of the operation A from the result of the operation B and inputs the result to the operation B unit.

FIG. 1 shows the configuration of a data receiving apparatus according to the first embodiment of the present invention. In FIG. 1, an input terminal 1-1 is a terminal to which a digital received signal is input. The initial value 1-2 is the initial value of the parameter used in the calculation A section when n = 0 (initial state), and is input to the calculation A section 1-3 only in the initial state. Operation A
The section 1-3 performs the operation A on all the patterns of the parameters used in the operation A, and outputs the result to the switch 1-4. The switch 1-4 is a switch for selecting one of the results calculated by the calculation A section using the result calculated by the calculation B section 1-5, and the calculation B section 1-5 and the output terminal. 1-6 are connected to output the selection result. Operation B section
1-5 calculates the output of the switch 1-4 to obtain the next parameter for selecting the result of the calculation A. The parameter is input to switch 1-4 and output terminal 1-7.
Is also output from.

Next, the operation of the data receiving apparatus of the first embodiment will be described. First, when a digital signal is input to the input terminal 1-1, when n = 0 (initial state), the operation A section 1-3 performs the operation A using the initial value 1-2 of the parameter, and the switch 1 It is output to -4. Switches 1-4 are
Based on the initial value parameters, the output of the calculation A section is output to the output terminal 1-6 and the calculation B section 1-5. In the calculation B section 1-5, the calculation B is performed based on the output of the switch 1-4, and the switch 1-4
The following parameters for switching are calculated, and the calculation result is output to the output terminal 1-7 and the switch 1-4. On the other hand, while the operation B unit 1-5 is operating, the operation A unit 1-3 uses the digital signal of the input terminal 1-1 to perform the operation A in parallel for all the patterns of the parameters used in the operation A, The results for each pattern are output to switches 1-4.
Therefore, the output of the operation A section 1-3 is selected by the switch 1-4 using the output parameter of the operation B section 1-5, and the output terminal 1-
6 and calculation B section 1-5. This operation is repeated for a desired time.

For example, assume that the input signal x is 8 bits and the parameter p is 4 bits. There are 16 parameter patterns in all. The operation A is y = f (x, p) =
(X + p) ² The initial value of p is 0. Operation B
Be p = y mod 16. In the calculation A section, first, (x
Calculate + p) ² = (x + 0) ² = x ² . This is output to the switch 1-4 and passed directly to the calculation B section 1-5. Operation B
The section 1-5 calculates p = x ² mod 16 and feeds it back to the switch 1-4. In the calculation B section 1-5, p = x ² mod 16
While calculating, the operation A section 1-3 performs 16 kinds of calculations for all patterns of parameters for the next input signal x. That is, x ² , (x +
1) ² , (x + 2) ² , ..., (x + 15) ² are all obtained. This calculation may be performed 16 times by one arithmetic circuit, or may be performed simultaneously by 16 arithmetic circuits. this
The 16 results are sent to the switch 1-4, the corresponding one is selected by the parameter from the calculation B section 1-5, and the calculation B section 1-
Pass to 5. This is repeated a predetermined number of times. As for the initial value, 16 calculations may be performed and the initial value may be selected.

In the present embodiment, the calculation A, the calculation B, and the parameters used are not limited to one type. Parameter is 2
An example in which there are three cases will be described. The parameters are p and q, and the operation A is y = f (x, p, q) = (x + p) · q
And x is 8 bits, both p and q are 4 bits, y
Is 13 bits. The calculation B is p = 2y mod 16
Let q = y ² mod 16. The calculation A section 1-3 calculates all 256 ways of p and q with respect to the input signal x, and outputs the result to the switch 1-4. The switch 1-4 selects one of the 256 results from the operation A section 1-3 according to the parameters p and q from the operation B section 1-5.

FIG. 3 shows an image of the time taken until a desired result is obtained with and without the use of the first embodiment. In the case of the first embodiment, since the main calculation A and the parameter calculation B for feedback are performed in parallel, one-step calculation can be performed substantially in the calculation time of only the calculation A. The calculation result can be obtained in about half the time compared with the comparison. Further, since the feedback calculation can be executed in substantially one step, it is possible to configure the systolic array for performing pipeline calculation by arranging the feedback calculation circuits in an array. Therefore, a high-speed arithmetic device for performing sequential processing including feedback, which is used for demodulation processing of received signals,
Can be realized with a systolic array.

As described above, according to the data receiving apparatus of the first embodiment, the input signal is calculated for all the patterns of the parameters, and the result is selected by the switch according to the parameters calculated in the calculation B section. The systolic array configuration can be applied to the calculation including the feedback element, and the time required to obtain a desired calculation result can be shortened.

(Second Embodiment) The second embodiment of the present invention is a result of performing the operation A in advance for all patterns of parameters necessary for performing the operation A and all patterns of input signals. And the memory that holds
In the data receiving device, an operation B unit for calculating a parameter required in step 1 and an address generation unit for generating an address of the memory from the result of the operation B and the input signal pattern are provided.

FIG. 2 shows the configuration of a data receiving apparatus according to the second embodiment of the present invention. In FIG. 2, an input terminal 2-1 is a terminal to which a digital signal is input.
The initial value 2-2 is the address generator 2-3 for n = 0 (initial state).
The initial values of the parameters used in
Connected to 1-3. The address generator 1-3 is a memory 2-
It is a circuit that generates an address for accessing 4, and is connected to the memory 2-4. The memory 2-4 is a memory that holds the parameters required for the operation A and the results of pre-calculation for all patterns of the input signal, and is connected to the output terminal 2-6 and the operation B unit 2-5. Computation B section 2-5 is a memory 2-
This is a circuit for performing a calculation B by using the output of 4 and calculating a parameter for generating an address for selectively reading the result of the calculation A from the memory. The result of operation B is output to both the output terminal 2-7 and the address generator 2-3.

Next, the operation of the data receiving apparatus according to the second embodiment will be described. First, when a digital signal is input to the input terminal 2-1, when n = 0 (initial state), the address generator 2-3 uses the input signal and the initial value 2-2 of the parameter to access the memory. The address for is calculated and output to memory 2-4. The memory 2-4 outputs the result of the operation A to the output terminal 2-6 and the operation B unit 2-5 according to the address output from the address generation unit 2-3. Operation B section
In 2-5, the parameter for generating the address is calculated in the address generating section 2-3 by performing the calculation B based on the output of the memory 2-4, and the calculation result is output to the output terminal 2-7. Output to the address generator 2-3. On the other hand, while the operation B unit 2-5 is in operation, the address generation unit 2-3 performs address generation in parallel for the digital signal of the input terminal 2-1 and all patterns of parameters, and the addresses generated for each pattern of parameters are generated. Among them, one address is selected by using the output of the calculation B section 2-5, and the memory 2-4 is accessed. The result read from the memory 2-4 is output to the output terminal 2-6 and the operation B unit 2-5. This operation is repeated for a desired time or a desired number of times.

For example, assume that the input signal x is 12 bits and the parameter p is 8 bits. There are 256 patterns of all parameters. The initial value of the parameter is 0. The calculation A is y = f (x, p) = (x + p) ² . As the memory 2-4, a memory having a capacity of 1 M word × 40 bits in which one word is 40 bits and an address is 20 bits is used. x
Is an upper bit and p is a lower bit, that is, (x + 256 + p)
p) Calculate and write the value of ² . The calculation B unit 2-5 obtains p from the output of the memory 2-4. First, x256 +
Generate address 0, access memory 2-4, x ²
To get At the next clock, in operation B section 2-5, from x ² to the next p
Ask for. At the same time, in the address generator 2-3,
For the next input signal x, the addresses corresponding to all the patterns of p are calculated. That is, (x256 +
0), (x · 256 + 1), (x · 256 + 2), ...
Calculate (x · 256 + 255). From these 256 addresses, one address is selected by p of the output of the calculation B unit 2-5. The memory 2-4 is accessed at the selected address and the (x + p) ² data is output.

In the present embodiment, the calculation A, the calculation B, and the parameters used are not limited to one type. Parameter is 2
In each case, the calculation of the operation A may be executed in advance for all the patterns of the two parameter sets and all the patterns of the input signal, and the result may be stored in the memory.

When only a part of the patterns of the input signal and the parameter has meaning, addresses are generated only for the meaningful patterns, and the address of the corresponding parameter is selected from them. Accessing the memory requires less memory. However, if all the patterns of input data and parameters are meaningful, it is easier to configure by directly inputting the input signals and parameters to the memory address because the address selection circuit is not required. Become.

Even if the operation A is a complicated and time-consuming operation, the memory read time is constant, so that the effect is greater when the operation A is a time-consuming operation.

As described above, according to the data receiving apparatus of the second embodiment, the address is generated from the input signal pattern and the parameter of the output of the operation B section, and the memory holding the result of the operation A is accessed. Since the calculation result is obtained by applying the configuration of the systolic array to the calculation including the feedback element, the time required to obtain a desired calculation result can be shortened. Further, as compared with the first embodiment, the calculation time can be shortened because the calculation is performed in advance when the calculation A is enormous.

[0029]

As is apparent from the above description, in the data receiving apparatus of the present invention, the configuration of the systolic array can be applied to the calculation including the feedback element to obtain a desired calculation result. The effect of shortening the time until is obtained.

Further, since the result of pre-calculation is stored in the memory, there is an effect that the calculation time can be shortened when the calculation is enormous.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data receiving device according to a first embodiment of the present invention,

FIG. 2 is a block diagram showing a configuration of a data receiving device according to a second embodiment of the present invention,

FIG. 3 is an operation explanatory diagram of the data receiving device according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration example of a conventional data receiving apparatus.

[Explanation of symbols]

1-1, 2-1, A-1 input terminals 1-2, 2-2 Initial value 1-3 Computation part A 1-4 switch 1-5, 2-5 Operation B section 1-6, 1-7, 2-6, 2-7, A-3-1 to A-3-n output terminals 2-3 Address generator 2-4 memory A-2 Addition / power calculation function section A-2-1 to A-2-n multiplier

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-4-149728 (JP, A) JP-A-6-309476 (JP, A) JP-A-6-324843 (JP, A) JP-A-6- 12228 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 7/00 H03M 13/00 G06F 17/10

Claims (4)

(57) [Claims] 1. An operation A section for performing the operation A for all patterns of input parameters and a set of parameters required to perform a predetermined operation A, and an operation B for calculating the parameter from the result of the operation A section. And a switch for selecting the result of the operation A section based on the parameter of the result of the operation B section and inputting the result to the operation B section. 2. A memory for holding a result of performing the operation A in advance for a set of all patterns of parameters necessary for performing the predetermined operation A and all patterns of input signals, and a result of the operation A. A data receiving apparatus comprising: an operation B unit that calculates the parameter; and an address generation unit that generates an address of the memory from the input signal and the parameter of the result of the operation B unit. 3. The operation A is performed for all patterns of parameters and input signals necessary for performing the operation A, and the operation B is performed for the result of the operation A.
Is performed to calculate the parameter, and the result of the operation A is selected by a switch based on the parameter of the result of the operation B and is input to the operation B. 4. A result of performing the operation A in advance is stored in a memory for a set of all patterns of parameters necessary for performing the predetermined operation A and all patterns of input signals, and the result of the operation A is stored. Perform a predetermined operation B to calculate the parameter, generate an address of the memory from the parameter of the result of the operation B and the input signal, access the memory at the address, and read the result of the operation A. A data receiving method, characterized in that the calculation B is input.