JP3390388B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring formed of a conductive thin film of a semiconductor device, and more particularly to a structure of a bent wiring bent in the same wiring layer.

[0002]

2. Description of the Related Art With the increase in scale and performance of semiconductor devices, the required wiring area of a semiconductor device chip is increasing more and more. Therefore, in order to further increase the scale and performance while suppressing the increase in the chip area, it is necessary to make the wiring multi-layered and miniaturized, and various technological developments are being made.

However, miniaturization of the wiring pattern causes another big problem of deterioration of wiring life due to electromigration (hereinafter referred to as EM). In particular,
The problem that the EM resistance of a wiring having a bent portion whose shape changes in a fine signal wiring is lower than the EM resistance of a wiring having only a straight portion due to uneven distribution of the flow path of the current flowing through this wiring in the bent portion. There is also.

FIG. 10 is a view for explaining the problem at the bent portion, and is a plan view schematically showing the bent wiring pattern and the current flow path in the wiring.

Referring to FIG. 10, the M of the wiring 101 is
When a current is passed from the point to the N point, the current is biased toward the inner corner side bending point K side of the bending portion 102. Therefore, even if the wiring 101 has a wiring width satisfying a predetermined current density standard in the straight portions 102 and 103, the bent portion 104
In some cases, wiring failure due to EM may occur.

As one of the solutions to these problems, Japanese Unexamined Patent Publication No. 62-237747 (hereinafter, referred to as known example 1).
Discloses a method of improving EM resistance without increasing the wiring area.

FIG. 11 is a schematic cross-sectional view of a wiring including a power supply wiring portion and a signal wiring portion of a semiconductor integrated circuit disclosed in the prior art example 1, and FIGS. 11A and 11B are wirings according to a conventional method. 3A and 3B are cross-sectional views of a wiring according to the method proposed in this known example 1.

Referring to FIGS. 11 (a) and 11 (b), in the case of a wiring through which a large current flows like the conventional power wiring 116, the power wiring width is simply widened in order to increase the cross-sectional area as an EM countermeasure. Was there. However, this increases the ratio of the power supply wiring area to the chip area of the semiconductor integrated circuit, which is an obstacle to high integration. Therefore, the film thickness of the wiring is increased to obtain the cross-sectional area required for the power wiring with the same wiring width as the signal wiring 112, and the same cross-sectional area as that of the power wiring 116 is obtained without increasing the wiring area. The power supply wiring 111 is formed.

Further, Japanese Patent Application Laid-Open No. 63-164337 (hereinafter, referred to as known example 2) discloses a method of suppressing EM failure by giving a gentle curvature to a portion where the wiring shape largely changes. ing.

FIG. 12 is a plan view of the wiring pattern disclosed in the known example 2, and (a) and (b) respectively show a pattern of a power supply wiring to which a plurality of lead-in wirings are connected and a wiring having a bent portion. ing.

With reference to FIGS. 12A and 12B, the wiring contour shape has a gentle curvature (specifically, the lead-in wiring 122) at the branch portion 123 with the plurality of lead-in wirings 122 connected to the power supply wiring 121. Where w is the width and z is the opening and r is the radius of curvature of the branch portion 123, r = 2
w, z = 5w), and the bent portion 1 of the wiring 125.
The wiring contour shape of 6 has a gentle curvature (for example, r = 3w)
Is giving. This suppresses the formation of voids in the wiring due to the current stress and improves the EM resistance of the wiring.

In addition, as shown in FIG. 13, the wiring direction is L-shaped.
There is also a method of relaxing the current concentration at the bent portion by changing the direction in two portions, for example, 45 degrees at the 0 ° bend portion.

[0013]

If the method disclosed in the known example 1 is used, it is effective in reducing the wiring area. However, when this method is applied to a signal wiring in which a plurality of long wirings, such as a bus line, are routed adjacent to each other in parallel, another problem occurs.

FIG. 14 is a view showing a cross section at an arbitrary position of adjacent signal wiring for explaining this problem.
(B) is a cross-sectional view when the wiring film thickness is increased and when it is not increased.

Referring to FIG. 14, in the method disclosed in the known example 1, the increase in the film thickness for increasing the cross-sectional area of the wiring is uniformly applied to the entire wiring. The state becomes like the signal wiring 141 and the signal wiring 142 of a). (Note that the wiring width and the distance between adjacent wirings are constant regardless of whether the wiring film thickness is increased or not.) Sections of the signal wiring 143 and the signal wiring 144 whose wiring film thickness is not increased Although there is no difference in the wiring area occupied on the chip between the two as compared with FIG. 6B, the area of the signal wirings facing each other increases by increasing the wiring film thickness. Therefore, the wiring 141,
It becomes larger than the inter-wiring capacitance C1 between 142 and the inter-wiring capacitance C2 between the wirings 143 and 144, which causes a problem in signal transfer characteristics (for example, signal delay and mutual interference between signal lines). Sometimes.

Further, in a semiconductor device having a multilayer wiring structure, when signal wirings having different film thicknesses are mixed in the same wiring layer other than the uppermost layer, a manufacturing problem occurs.

FIG. 15 is a schematic sectional view when wirings having different film thicknesses are mixed in the same wiring layer other than the uppermost layer.

Referring to FIG. 15, wiring 151 and wiring 1
Reference numeral 52 is a wiring formed in the same wiring layer, for example, wiring 1
It is assumed that the film thickness of 51 is larger than that of the wiring 152 having a normal film thickness. Also, the wiring 153, 15
Reference numeral 4 is a wiring formed in a layer higher than the wirings 151 and 152, which are wiring 151 and wiring 153, wiring 152 and wiring 154.
For transmitting signals respectively, the connection openings 155, 1
It is assumed that they are connected via 56.

The wiring 151 and the wiring 153 or the wiring 1
Although various manufacturing methods can be considered for connecting the wiring 52 and the wiring 154, since the connection openings 155 and 156 have different depths, the formation of the connection opening 155 and the formation of the connection opening 156 are performed separately or at least two times. It is usually performed in a step-wise manufacturing process.

Therefore, by mixing wirings having different film thicknesses in the same wiring layer, it becomes difficult to collectively process at least the step of forming an opening for connection with the wiring of the upper layer in the subsequent step. There is a problem that the manufacturing process is further added or complicated.

Further, in the case of using the known example 2 or the method related thereto, the effect of alleviating the current concentration at the bent portion brings a certain effect,
All of these have to form a curved portion or an inclined portion with a certain degree of curvature or angle at the bent portion, and have a considerable influence on the periphery of the signal wiring for which current concentration must be relaxed.

FIG. 16 is a view for explaining a problem when using this known example 2 or a method related thereto,
(A) and (b) are portions in which the wiring direction bends in an L-shape by 90 °, for example, when the direction is changed by dividing it by 45 ° in two times and when it is simply changed by 90 ° in one time. It is a schematic plan view which shows typically the inside angle side element arrangement | positioning area | region 164 and (167 + 168).

Referring to FIG. 16, the wiring 16 of FIG.
In the element arrangement region 164 in the case where the direction is bent 90 degrees into an L shape by dividing the direction into 45 degrees like 1, 162 in FIG.
5 and 166, the element arrangement region 16 of the element arrangement regions 167 and 168 simply changed by 90 ° at one time.
8 cannot be used, and the element arrangement area becomes narrower, or the wiring area at the bent portion increases in order to secure the element arrangement area.

One of the main objects of the present invention is to provide a semiconductor device in which the EM resistance of the wiring having a bent portion on the chip of the semiconductor device is improved without increasing the wiring area.

Another object of the present invention is the EM of the bent portion.
It is an object of the present invention to provide a semiconductor device having a wiring structure in which the signal transfer characteristics are not deteriorated by improving the resistance and the number of manufacturing steps for improving the EM resistance is minimized.

[0026]

The semiconductor device of the present invention comprises:
A continuous wiring in the same layer, which is formed by including a reference film thickness portion of a predetermined film thickness formed of a first conductive thin film and at least the first conductive thin film, thicker than the reference thickness portion, Rutotomoni same and a different reinforcing film thickness portion and the connection opening for connection to other wiring layers
Equipped with a bend that changes the wiring direction within the layer, this bend
It has a wiring that is a reinforced film thickness portion .

[0027]

Further, the plane shape of the wiring is such that a first straight line portion having a width W1 in the first direction and a width that is continuous with the first straight line portion and is bent in a second direction different from the first direction. Is a second straight line portion of W2 and a bending point at which an edge portion that defines the width of the wiring bends from the first direction to the second direction, and the first straight line portion and the second straight line are on the inner angle side. An inner corner side bending point that does not include a portion and an inner corner side bending point that does not include a portion, and the inner angle side bending point is surrounded by straight lines that pass through the inner angle side bending point and cross each of the first straight line portion and the second straight line portion at a right angle. The bent portion can be defined so as to include at least a region in which there is a joint connecting the point and the bending point on the outside corner side.

Further, the bent portion passes through the positions of W1 and W2 from the inner angle side bending point on the edge portion forming the inner angle side bending point of the first straight portion and the second straight portion, respectively, and passes through the first straight portion. Alternatively, the region may be surrounded by a straight line that crosses each of the second straight line portions at a right angle and that includes the joint portion.

Alternatively, each of the first straight line portion and the second straight line portion is surrounded by a straight line parallel to the joint portion, the distances from the inner angle side bending point on the edge portion forming the inner angle side bending point passing through the positions W2 and W1, respectively. The bent portion may be a region including the joint portion.

Further, an intersection of a straight line that passes through the inner corner side bending point and crosses each of the first straight line portion and the second straight line portion at a right angle, and an edge portion that forms the outer corner side bending point of the first straight line portion and the second straight line portion. When,
When the distances to the outside corner side bending points are respectively h1 and h2, the distances from the inside corner side bending points on the edge portions forming the inside angle side bending points of the first straight line portion and the second straight line portion are h1 and h2, respectively. h
The bent portion may be a region that is surrounded by straight lines that pass through the position 2 and crosses the first straight line portion and the second straight line portion at a right angle and that includes the joint portion.

Further, an intersection of a straight line that passes through the inner corner side bending point and crosses each of the first straight line portion and the second straight line portion at a right angle and an edge portion that forms the outer corner side bending point of the first straight line portion and the second straight line portion. When,
When the distances to the outside corner side bending points are respectively h1 and h2, the distances from the inside corner side bending points on the edge portions forming the inside angle side bending points of the first straight line portion and the second straight line portion are h1 and h2, respectively. h
A region surrounded by a straight line passing through the position 2 and parallel to the joint and including the joint may be the bent portion.

The reinforcing film thickness portion is formed so as to project above the reference film thickness portion, or is formed so as to project toward the lower layer side, and at least the projecting portion is buried in the lower layer side interlayer insulating film. It can also be formed. When the reinforcing film thickness portion is formed so as to project to the upper layer side with respect to the reference film thickness portion, it is preferable to connect this wiring and the wiring of the upper layer at a position avoiding the bent portion.

The reinforcing film thickness portion includes at least the first conductive thin film forming the reference film thickness portion, but further includes the second conductive thin film different from the first conductive thin film. You can also

The increase in the wiring cross-sectional area due to these configurations is
It plays the role of alleviating the current concentration at the bend. Therefore, the effect of improving electromigration resistance due to current concentration at the bent portion can be obtained.

The effects of these configurations are particularly remarkable when applied to a signal wiring which has been miniaturized.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Next, the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view schematically showing a bent portion of a wiring of a chip of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2A and 2B are each a view of FIG. FIG. 3 is a schematic plan view of the wiring and a cross-sectional view schematically showing a cross section taken along the line AA ′ of FIG.

Referring to FIGS. 1 and 2, the wiring 1 of the semiconductor device of this embodiment has a first straight line portion 11 having a width W1 and a first direction and a second straight line portion 11 having a width W2 and a second direction. 12 is an imaginary joint 2 that connects the inner-angle-side bending point P0 and the outer-angle-side bending point Q0, and is bent at a right angle, for example, and the first straight line portion is formed on the edge portion that forms the inner-angle-side bending point from the joint 2. The first straight line 16 that passes through the position P1 at the distance W1 on the 11 side and crosses the first straight line portion 11 at a right angle, and the second straight line portion 12 at the right angle through the position P2 at the distance W2 on the second straight line portion 12 side. The region surrounded by the second straight line 17 that crosses is the bent portion 3.

The bent portion 3 has a film thickness Δ on the reference film thickness portion 10 of the wiring film thickness s formed by using the first conductive thin film.
The film thickness adding portion 13 of s is formed to form the wiring film thickness t (t = s + Δ
s) is thicker than the film thickness s of the reference film thickness portion 10 by Δs in a convex shape on the upper layer side to increase the cross-sectional area. That is, the bent portion 3 is a film thickness reinforcing portion that is thicker than the reference film thickness portion 10 and protrudes above the reference film thickness portion.

To obtain a reliable effect of film thickness reinforcement, t
/S≧1.1 is desirable. The relationship between W1 and W2 is
Normally, W1 = W2, but W1 ≠ W2 may be satisfied.

Next, an outline of an example of a method of manufacturing the wiring 1 of the semiconductor device of this embodiment will be described.

FIG. 3 is a sectional view schematically showing a sectional outline in a main step for explaining this manufacturing method.
2 to (a4) are portions corresponding to the cross section along the line AA 'in FIG. 2 (a), and (b1) to (b4) are normal wiring portions formed in the same wiring layer.

Referring to FIG. 3, in the semiconductor device of this embodiment, first, a predetermined film thickness is formed on a first insulating film 21 on a substrate 20 of a semiconductor chip on which elements are formed by a known element forming method. A first conductive thin film 22 of s, for example, aluminum (Al) is deposited (a1, b1), and the reference film thickness portion 10 of the wiring 1 and a desired normal wiring 110 pattern are formed by using a photolithography technique. After that, the second on the entire surface
The insulating film 23 is deposited so as to cover the surface of the reference film thickness portion 10 and the normal wiring 110 (a2, b2).

Next, using photolithography, the second insulating film 23 is removed only on the upper portion of the bent portion 3 of the wiring 1 to form an opening 24, and the same Al as that of the first conductive thin film is formed on the entire surface. A second conductive thin film 25 such as
Only s is deposited so that the film thickness of the conductive thin film (the sum of the film thicknesses of the first and second conductive thin films) at the opening 24 becomes a desired film thickness t (a3, b3).

Next, the second conductive thin film 25 other than the portion of the opening 24 is removed by using the photolithography technique,
By depositing the third insulating film 26 on the entire surface (a4, b4), the film thickness t of the bent portion 3 is Δs thicker than the film thickness s of the reference film thickness portion 10 and more than the reference film thickness portion. The wiring 1 is formed as a reinforcing film thickness portion protruding to the upper layer side.

After that, since it is easy to form the upper layer wiring by using the well-known multilayer wiring technique, the description thereof will be omitted. At this time, it is desirable to dispose the through hole for connecting to the wiring of the upper layer while avoiding the bent portion 3. As a result, the depth of the through hole becomes substantially constant, and the complexity of the through hole opening process can be avoided.

As described above, in the wiring 1 of the semiconductor device of this embodiment, the wiring film thickness t of the bent portion 3 including the joint 2 is smaller than the wiring film thickness s of the linear region having the same film thickness as the reference film thickness portion 10. Also Δs
Therefore, even if the current is concentrated in the bent portion 3, the current density in the bent portion 3 can be relaxed and the EM resistance can be improved.

Further, since the film thickness reinforcing portion in which the wiring film thickness is increased by the film thickness adding portion 13 is limited to the portion where the problem of EM resistance is likely to occur due to the concentration of current, the capacitance between the adjacent wirings is increased. Is suppressed to a minimum, and the influence on the signal transfer characteristic and the like is suppressed to a range where it is not substantially detected.

In the method of manufacturing the wiring 1 according to the above-described embodiment, the film thickness addition portion 1 for increasing the wiring film thickness of the bent portion 3 is formed.
3 is formed on the second conductive thin film 25 forming the reference film thickness portion 10
Although the example of using Al of the same material as that of the first conductive thin film 22 for forming is described, the manufacturing method is not limited to this, and various changes can be made including the material and the film forming method. . For example, the conductive thin film material may be a low resistance metal film such as copper (Cu), and the first conductive thin film 22 and the second conductive thin film 25 are integrally formed into a desired film for the film thickness reinforcing portion. The normal wiring 110 and the wiring 1 are formed by forming a film to a thickness and etching.
It is also possible to form the film by controlling the film thickness of a linear portion or the like having the same film thickness as the reference film thickness part 10. Furthermore, the second conductive thin film 25 formed in the film thickness adding portion 13 may be made of a material different from that of the first conductive thin film 22, such as a refractory metal such as tungsten (W).

Next, a second embodiment of the present invention will be described.

Since the wiring of the semiconductor device of this embodiment has the same planar shape as that of the first embodiment, refer to FIG. 2A for a plan view. 4A and 4B are views for explaining the wiring of the semiconductor device of the present embodiment, FIG. 4A is a perspective view schematically showing a bent portion of the wiring, and FIG. 4B is a line A- in FIG. It is sectional drawing which shows the A'line cross section typically.

In the bent wiring 5 of this embodiment, the area definition of the bent portion is the same as that of the first embodiment together with the planar shape, and therefore the description of the area definition of the bent portion is omitted.

With reference to FIGS. 2A and 4, the wiring 5 of the semiconductor device of this embodiment also includes the first straight line portion 4 in the first direction.
1 and a second straight portion 42 in a second direction different from the first direction are bent at a right angle at the joint portion 2, and the bent portion 3 is the same as a normal wiring (not shown) formed in the same wiring layer. A film thickness addition portion 43 having a film thickness Δs is provided below the reference film thickness portion 40 formed of the wiring material / wiring film thickness s, and the wiring film thickness t (where t = s
The cross-sectional area is increased by making + Δs) thicker by Δs than the film thickness s of the reference film thickness portion 40 to the lower layer side.

That is, in the bent portion 3 of the wiring 5 of the semiconductor device of the present embodiment, unlike the first embodiment, the film thickness addition portion 43 is provided in a convex shape on the lower layer side of the reference film thickness portion 40 to form a wiring film. The thickness is increased, and the film thickness reinforcing portion projects to the lower layer side than the reference film thickness portion 40.

Next, an outline of an example of a method of manufacturing the wiring 5 of the semiconductor device of this embodiment will be described.

FIG. 5 is a sectional view schematically showing a sectional outline in a main step for explaining this manufacturing method.
2 to (a4) are portions corresponding to the cross section along the line AA 'in FIG. 2 (a), and (b1) to (b4) are normal wiring portions formed in the same wiring layer. .

Referring to FIG. 5, in the semiconductor device of the present embodiment, first, as in the case of the first embodiment, the substrate 5 of the semiconductor chip on which the elements are formed by the well-known element forming method.
On the first insulating film 51 above 0, a recess 52 having a depth Δs is formed by photolithography or the like in a portion where the bent portion 3 where the film thickness of the wiring 5 is desired to be thick is arranged (a
1, b1).

Next, a conductive thin film 53 such as aluminum (Al) having a predetermined film thickness t '(t'> t is desirable) is deposited (a2, b2).

Then, the conductive thin film 53 is etched or polished by using, for example, an etch back technique or a chemical mechanical polishing (CMP) technique so that the reference film thickness portion 40 and the normal wiring portion have a thickness of s. After that, a pattern including the wiring 5 and the desired normal wiring 120 is formed (c) by using a photolithography technique or the like, and then a fourth interlayer insulating film is formed on the entire surface.
The insulating film 54 is deposited to a predetermined thickness (d) to form the wiring 5 of the semiconductor device of this embodiment.

After that, as in the case of the first embodiment, the upper layer wiring can be easily formed by using the well-known multilayer wiring technique, and therefore the description thereof is omitted.

As described above, the semiconductor device of this embodiment is
After forming a recess 52 having a depth of Δs in a predetermined region of the first insulating film 51 (a region where the bent portion 3 of the wiring 5 is arranged), a conductive thin film 53 is deposited by a film thickness t ′. Normal wiring 1
20 and the reference film thickness portion 40 of the wiring 5 are etched or polished so that the wiring film thickness becomes a desired film thickness s.
While the surface is flattened, the film thickness t of the bent portion 3 becomes thicker than the wiring film thickness s of the reference film thickness portion 40 by Δs.

That is, the wiring 5 of the semiconductor device of this embodiment is a film thickness reinforcing portion in which the bent portion 3 is thicker than the reference film thickness portion 40 and protrudes below the reference film thickness portion 40. ing.

Therefore, even if the current is concentrated in the bent portion 3, the current density in the bent portion 3 is relaxed, and the EM resistance is improved as in the first embodiment.

Further, since the film thickness reinforcing portion in which the wiring film thickness is increased by the film thickness adding portion 43 is limited to the portion where the problem of the EM resistance is likely to occur due to the concentration of the current, the capacitance between the adjacent wirings is increased. Is suppressed to the minimum, and the point that the influence on the signal transfer characteristics and the like is suppressed to a range where it is not substantially detected is the same as in the first embodiment.

Further, in the case of the present embodiment, the film thickness adding portion 43
Has a shape embedded in the lower first insulating film 51, so that the unevenness of the chip surface can be alleviated and the subsequent process can be easily performed.

Next, a third embodiment of the present invention will be described.

The plan view of the wiring of the semiconductor device of this embodiment is the same as that of the first and second embodiments, so refer to FIG. 2A for the plan view. 6A and 6B are views for explaining the wiring of the semiconductor device of this embodiment, FIG. 6A is a perspective view schematically showing a bent portion of the wiring, and FIG.
It is sectional drawing which shows the AA 'line cross section in (a) typically.

Since the wiring 7 of this embodiment has the same planar shape as that of the first and second embodiments including the area definition of the bent portion, the description of the area definition of the bent portion will be omitted.

With reference to FIGS. 2A and 6, the wiring 7 of the semiconductor device of this embodiment also includes the first straight line portion 61 in the first direction.
And a second straight line portion 62 in a second direction different from the first direction are bent at a right angle at the joint portion 2, and the bent portion 3 has an upper layer side and a lower layer side of the reference film thickness portion 60 having a film thickness s, respectively. Is, for example, the film thickness Δs
An upper layer side film thickness addition section 63 and a lower layer side film thickness addition section 64 are provided. Therefore, the wiring film thickness t of the bent portion 3 is thicker than the film thickness s of the reference film thickness portion 60 by Δs, and the bent portion 3 is thicker than the reference film thickness portion 60. Has become.

That is, the wiring 7 of the semiconductor device of this embodiment is made to project to the upper layer side in the first embodiment and to the lower layer side in the second embodiment when increasing the wiring film thickness of the bent portion 3. This is different from the first and second embodiments in that it is made thicker by projecting it on both the upper layer side and the lower layer side, while it is made thicker by projecting.

In the description of the above embodiment, the bent portion 3
The thicknesses of the upper layer side film thickness addition portion 63 and the lower layer side film thickness addition portion 64 are made equal to each other, but the film thicknesses of these film thickness addition portions are different between the upper layer side and the lower layer side. However, how to allocate each may be appropriately determined in consideration of other factors such as ease of manufacturing. Further, the wiring 7 of the semiconductor device of the present embodiment can be easily manufactured by combining the manufacturing methods of the first and second embodiments, and therefore the description of the manufacturing method is omitted.

Further, in any of the above-described first, second and third embodiments, the bent portion area which is the film thickness reinforcing portion in which the wiring film thickness is made thicker than the reference film thickness portion is shown in FIG. Although the region including the joint portion surrounded by the straight line that passes through the predetermined positions P1 and P2 and crosses each straight line at a right angle in a) is defined as parallel to the joint portion 2 that passes the predetermined positions P1 and P2 as shown in FIG. It may be a region including the joint portion 2 surrounded by the third straight line 76 and the fourth straight line 77.

In each of the above-described first, second and third embodiments, the example in which the bent portion is bent 90 degrees in an L-shape has been described, but the present invention is not limited to this and is arbitrary. It may be bent at an angle.

For example, as shown in FIG. 8A, the wiring 8 has a first straight portion 81 having a width W1 and a second straight portion 8 having a width W2.
Even when 2 is bent at an arbitrary angle that is not a right angle, the position P1 and the second straight line where the distance is W1 from the inner angle side bending point P0 to the first straight line portion 81 side on the edge portion forming the inner angle side bending point P0. The first straight line 86 and the second straight line portion 8 that pass through the position P2 with the distance W2 toward the portion 82 side and cross the first straight line portion 81 at a right angle.
A region including the joint portion 2 surrounded by the second straight line 87 that crosses 2 at a right angle may be used as the bent portion 83 to form a film thickness reinforced portion in which the wiring film thickness is increased.

Further, as shown in FIG. 8B, these P1 and P2 are
Third straight line 88 and fourth straight line 8 parallel to the joint 2 passing through
A region including the joint portion 2 surrounded by 9 may be a bent portion 84 to increase the wiring film thickness.

Further, in the above description, regardless of the bending angle of the bent portion, in any case, the predetermined position P1 is the position of the distance of the width W1 of the first straight portion from the inner-angle-side bending point P0 and the predetermined position. P2 is set at the position of the distance of the width W2 of the second straight portion from the inner corner side bending point, but at least the inner corner side bending point P
It may be appropriately determined in consideration of the inter-wiring capacitance and other factors as long as it includes a region where there is a junction surrounded by straight lines that pass through 0 and cross the first straight line portion and the second straight line portion at right angles. .

For example, as shown in FIG. 9, a straight line that passes through the inner corner side bending point P0 of the wiring 9 and crosses the first straight line portion 91 and the second straight line portion 92 at a right angle, and the first straight line portion 91 and the second straight line portion 92. The intersections with the edge portion forming the outer corner side bending point Q0 are Q1 and Q2, and the distances between Q0 and Q1 and Q2 are h1 and h2, respectively. It is also possible to set the positions of the distance h1 on the side of the first straight line portion 91 and the distance h2 on the side of the second straight line portion 92 on the edge portion that forms the predetermined positions P1, P2, respectively.

[0079]

As described above, a semiconductor device having a continuous wiring formed of the conductive thin film of the present invention and having a bent portion in the same layer is a reference film in which a desired bent portion constitutes wiring. The cross-sectional area is increased because it is an additional film thickness that is thicker than the wiring thickness of the thick part, and even if there is current concentration in the bent portion, the current density in the bent portion is relaxed without increasing the wiring area. As a result, the effect that the EM resistance can be improved is obtained.

Moreover, at this time, since the film thickness additional portion where the wiring film thickness is increased is limited to the portion where the problem of EM resistance is likely to occur due to the current concentration, the increase in the capacitance between adjacent wirings is minimized. It is suppressed, and the effect of suppressing the influence on the signal transfer characteristic and the like to a range where it is not substantially detected is also obtained.

Further, since the increase of the wiring film thickness is limited only to the bent portion, when applied to the semiconductor device using the multilayer wiring structure, the through hole for connecting with the wiring of the upper layer is arranged avoiding the bent portion. By doing so, it is possible to obtain the effect that it is possible to suppress further addition and complication of the manufacturing process.

[Brief description of drawings]

FIG. 1 is a perspective view schematically showing a bent portion of a wiring having a bent portion of a chip of a semiconductor device according to a first embodiment of the present invention.

2A and 2B are schematic plan views of the wiring of FIG. 1A and FIG.
FIG. 6B is a cross-sectional view (b) schematically showing a cross section taken along line AA ′ of FIG.

FIG. 3 is a cross sectional view schematically showing a cross sectional outline in a main step for explaining an example of the method for manufacturing the wiring of the semiconductor device of the first embodiment of the present invention.

4A and 4B are views for explaining the wiring of the semiconductor device according to the second embodiment of the present invention, FIG. 4A is a perspective view schematically showing a bent portion of the wiring, and FIG. A- in a)
It is sectional drawing which shows the A'line cross section typically.

FIG. 5 is a cross sectional view schematically showing a cross sectional outline in a main step for explaining an example of the method for manufacturing the wiring of the semiconductor device according to the second embodiment of the present invention.

6A and 6B are views for explaining wiring of a semiconductor device according to a third embodiment of the present invention, FIG. 6A is a perspective view schematically showing a bent portion of the wiring, and FIG. A- in a)
It is sectional drawing which shows the A'line cross section typically.

FIG. 7 is a schematic plan view for explaining another example of a method of setting a boundary line that defines a bent portion.

FIG. 8 is a plan view schematically showing an example of a bent portion when bent at an arbitrary angle.

FIG. 9 is a schematic plan view for explaining another example of the method of setting the position of the boundary line that defines the bent portion.

FIG. 10 is a plan view schematically showing another example of a bent portion when bent at an arbitrary angle.

FIG. 11 is a schematic cross-sectional view of a wiring including a power supply wiring portion and a signal wiring portion of the semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 62-237747.

FIG. 12 is a diagram showing a wiring pattern disclosed in Japanese Patent Application Laid-Open No. 63-164337, wherein (a) and (b) respectively show a power supply wiring to which a plurality of lead-in wirings are connected and a wiring pattern having a bent portion. It is a top view.

FIG. 13 is a diagram for explaining an example of a method for relaxing current concentration at a bent portion, which is a schematic view of a portion bent by 90 ° into an L shape by changing the wiring direction by 45 ° twice. FIG.

FIG. 14 is a diagram showing a cross section at an arbitrary position of an adjacent signal wiring when the wiring cross sectional area is increased by the method disclosed in Japanese Patent Laid-Open No. 62-237747, (a) and (b).
FIG. 3A is a cross-sectional view of the case where the wiring film thickness is increased and FIG.

FIG. 15 is a schematic cross-sectional view when wirings having different film thicknesses are mixed in the same wiring layer other than the uppermost layer.

FIG. 16 is a portion in which the wiring direction bends 90 ° in an L shape,
FIG. 6 is a schematic plan view for explaining the influence on the element arrangement region when the direction is changed by dividing the angle into two parts.

[Explanation of symbols]

1,5,7,8,9 wiring 2 joints 3,83 bend 10, 40, 60 Standard thickness part 11, 41, 61, 81, 91 First straight line portion 12, 42, 62, 82, 92 Second straight part 13,43 additional film thickness 16,86 First straight line 17,87 Second straight line 20,50 substrate 21,51 First insulating film 22 First conductive thin film 23 Second insulating film 24 opening 25 Second conductive thin film 26 Third insulating film 52 recess 53 Conductive thin film 54 Fourth insulating film 63 Upper layer side film thickness addition section 64 Lower layer side film thickness addition section 76,88 Third straight line 77, 89 Fourth straight line 110, 120 Normal wiring

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (12)

(57) [Claims] 1. A semiconductor device having continuous wiring in the same layer, wherein the wiring has a reference film thickness portion of a predetermined film thickness formed of a first conductive thin film, and at least the first film. and film thickness is formed to include a conductive thin film is thicker than the thickness of the reference film thickness portion, and a different reinforcing film thickness portion and the connection opening for connection to other wiring layers Rutotomoni , The distribution
The wire is provided with a bent portion where the wiring direction changes in the same layer.
The semiconductor device bent portion characterized that you have made to the reinforcing film thickness portion. 2. The wiring has a first straight line portion having a width W1 in the first direction and a width W2 which is continuous with the first straight line portion and is bent in a second direction different from the first direction. The second straight part,
An edge portion that defines the width of the wiring is a bending point that bends from the first direction to the second direction, and includes an outer corner side bending point that includes the first straight line portion and the second straight line portion on the inner angle side. It has a planar shape including an inner angle side bending point, and the bending portion of the wiring is
A region surrounded by straight lines that pass through the inside-angle-side bending point and cross each of the first straight line portion and the second straight-line portion at a right angle, and that has a joint portion that connects the inside-angle-side bending point and the outside-angle-side bending point. the semiconductor device according to claim 1, wherein at least include. 3. The bent portion passes through the positions of W1 and W2, respectively, from the inner-angle-side bent point on each edge portion that forms the inner-angle-side bent point of the first straight portion and the second straight portion. The semiconductor device according to claim 1 , wherein the semiconductor device is a region including a junction portion surrounded by a straight line that crosses each of the first straight line portion and the second straight line portion at a right angle. 4. The bent portion passes through the positions of W1 and W2 from the inner-angle-side bent point on the edge portion that forms the inner-angle-side bent point of the first straight portion and the second straight portion, respectively, and joins the joint portion. a region including the bonding portion surrounded by a straight line parallel claim 1
The semiconductor device described. 5. The bending portion forms a straight line that passes through the bending point on the inner angle side and crosses each of the first straight line portion and the second straight line portion at a right angle, and the bending point on the outer angle side of the first straight line portion and the second straight line portion. When the distance between the intersection with the edge portion and the outside corner side bending point is h1 and h2, respectively, the first straight portion and the second straight portion
It is a region including the joint portion surrounded by straight lines parallel to the joint portion, the distances from the inner corner side bending point on the edge portion forming the inner angle side bending point of the straight line portion passing through the positions h1 and h2, respectively. The semiconductor device according to claim 1 . 6. The bending portion forms a straight line that passes through the bending point on the inner angle side and crosses each of the first straight portion and the second straight portion at a right angle, and the bending point on the outer angle side of the first straight portion and the second straight portion. When the distances between the intersection point with the edge portion and the outside corner side bending point are h1 and h2, respectively, on the edge portion forming the inside angle side bending point of the first straight line portion and the second straight line portion. claim 1, wherein a distance from the inner angle side inflection point is a region including a bonding portion which is rectilinear transverse h1, h2 positions respectively through the first linear portion and the second linear portion at right angles to each Semiconductor device. 7. A semiconductor device according to claim 1 to 6 any one protrudes on the upper side of the reinforcing film thickness portion is a reference thickness portion. 8. The semiconductor device according to claim 1 to 6 any one projects the lower layer side than the reinforcing film thickness portion is a reference thickness portion. 9. The semiconductor device according to claim 1, wherein the connection with the upper wiring is made at a position which is not a bent portion. 10. the reference thickness portion and the reinforcing film thickness portion are both semiconductor device according to any one of claims 1 to 9 are formed in the first conductive thin film. 11. The semiconductor device according to any one of claims 1 to 9 reinforcement film thickness portion includes a second conductive thin film that is different from the first conductive thin film. 12. The wiring according to claim 1, wherein the wiring is a signal wiring.
1. The semiconductor device according to any one of items 1.