JP3376990B2 - SEPP circuit and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SEPP circuit, and more particularly to a SEP provided with a resistor for adjusting a dark current in a semiconductor device.
It belongs to the P circuit and its manufacturing method.

[0002]

2. Description of the Related Art A conventional SEPP (Single Ende) shown in FIG.
The d-push-pull circuit includes a first semiconductor device (1) and a second semiconductor device (2) connected in series to a DC power supply (9), and a first semiconductor device (1).
Connected in series between the connection point between the semiconductor device (1) and the second semiconductor device (2) and the negative terminal of the DC power supply (9) and in parallel with the second semiconductor device (2). Capacitor (11) and load (1
0) and a non-transformer (OTL) circuit. The first semiconductor device (1) is a pair of NPN transistors of the same polarity.
A first Darlington circuit (3) consisting of (3a, 3b) and an NP
And a diode (4a, 4b) forming a temperature compensating diode (4) connected to the base of the N-transistor (3a). The collectors of the NPN transistor (3a) and the NPN transistor (3b) are connected to the positive terminal of the DC power supply (9), and the emitter of the NPN transistor (3b) is connected to the capacitor (11) via the resistor (12). . Second semiconductor device
(2) is a pair of PNP transistors of the same polarity (5a, 5b)
A second Darlington circuit (5) and a diode (6a, 6b) forming a temperature compensating diode (6) connected to the base of the PNP transistor (5a).
The emitter of the PNP transistor (5b) is connected to the capacitor (11) via the resistor (13), and the PNP transistor (5a, 5b) is connected.
The collector of b) is connected to the negative terminal of the DC power supply (9).
Further, the diodes (4, 6) are connected via the resistor (7). As indicated by the dotted line, the first semiconductor device (1) and the second semiconductor device (2) are each configured as a resin-sealed electronic component that is resin-sealed.

In operation, the base terminals of the NPN transistor (3a) of the first Darlington circuit (3) and the PNP transistor (5a) of the second Darlington circuit (5) which are symmetrically connected have the same size. A control signal having a phase difference of 180 degrees is given. NPN transistor (3
When a) is turned on, current flows from the DC power supply (9) to the NPN transistor (3b), the capacitor (11) and the load (10), and the capacitor (11) is charged. When the PNP transistor (5a) is turned on in the negative half cycle, the energy stored in the capacitor (11) is loaded through the PNP transistor (5b).
Supplied to (10). Where the first and second diodes
(4, 6) acts so as to compensate for the temperature dependence of the voltage between the base and emitter terminals of the first Darlington circuit (3) and the second Darlington circuit (5), and the resistor (7) causes dark current ( It has the function of adjusting the idling current). That is, by operating the first Darlington circuit (3) and the second Darlington circuit (5) with an idling current of a predetermined value, the non-linearities of the characteristic curves of the transistors are compensated for each other to operate in a complementary manner. The linearity is improved, and a large output power without distortion can be obtained.

[0004]

[Problems to be Solved by the Invention] First semiconductor device (1)
And when manufacturing the second semiconductor device (2), there are variations in the voltages V _BE1 and V _BE2 between the base and emitter terminals of the first Darlington circuit (3) and the second Darlington circuit (5). . Therefore, the dark current is controlled to an appropriate level by adjusting the level of the resistor (7), and the current I _C flowing through the collector terminals of the first Darlington circuit (3) and the second Darlington circuit (5) is adjusted. It must be set to the desired value.
The desired value of the current I _C flowing through the collector terminal is, for example, 40 to
It is about 100 [mA]. Conventionally, the resistor (7) is connected as an external resistor between the diodes (4, 6), and the semiconductor device (1,
Since the user who purchased 2) had to adjust the resistance value of the resistor (7) in accordance with the characteristics of the peripheral circuit at the time of use, a SEPP circuit that does not need to adjust the resistance value was desired. Also, instead of the bipolar transistor, MIS
Similarly, a SEPP circuit using a FET (metal-insulator-semiconductor contact field effect transistor), MESFET (metal-semiconductor contact field effect transistor), IGBT (insulated gate bipolar transistor), etc., has a resistance on the user side. Needed adjustment.

Therefore, an object of the present invention is to provide a SEPP circuit which does not require the user to adjust the resistance value and a manufacturing method thereof. Another object of the present invention is to provide a SEPP circuit in which a resistor for dark current adjustment can be integrally sealed with a resin sealing body, and a manufacturing method thereof.

[0006]

A SEPP circuit according to the present invention comprises a first resistor (58) for controlling a voltage applied to a first amplifying element (53) and a control terminal of the first amplifying element (53). And a second resistor (59) for controlling the voltage applied to the control terminals of the second amplifying element (55) and the second amplifying element (55). A second semiconductor device (52) is provided, and the first semiconductor device (51) and the second semiconductor device (52) are connected in series. The temperature compensating element (54) is connected in series with the first resistor (58) and the second resistor (59) between the control terminal of the first amplifying element (53) and the control terminal of the second amplifying element (55). ) Is connected. A The current ( _ID ) flowing through the temperature compensation element (54) and the first resistance (5
8) Resistance value (R ₁ ) product and temperature compensation element (54) terminal voltage
The sum of (V _F1 ) is higher than the threshold value (V _TH1 ) of the first amplifying element (53) by a constant level (V ₀ ), and the current (I
The product of _D ) and the resistance value (R ₂ ) of the second resistor (59) is lower than the threshold value (V _TH2 ) of the second amplifying element (55) by the constant level (V ₀ ), or the B temperature The current ( _ID ) flowing through the compensation element (54) and the first resistance (5
The product of 8) and the resistance value (R ₁ ) is the threshold value (V
_TH1 ) is lower by a certain level (V ₀ ), and the product of the current ( _ID ) flowing through the second resistor (59) and the resistance value (R ₂ ) of the second resistor (59) and the temperature compensation element (54 ) Is higher than the threshold voltage (V _TH2 ) of the second amplifying element (55) by a constant level (V ₀ ), and the sum of the terminal voltage (V _F1 ) and the resistance value satisfies either condition A or B. (R ₁ ,
A first resistor (58) and a second resistor (59) are adjusted for R ₂ ), respectively. Further, the first semiconductor device (51) and the second semiconductor device (52) are each sealed by the resin sealing body (64, 74). The threshold value (V _TH1 , V _TH2 ) in the present invention is
When the first and second amplifying elements (53, 55) are bipolar transistors, it means the base-emitter voltage when an idling current of a predetermined value is passed, and the first and second amplifying elements (53, 55) Is a MISFET, MESFET or the like, it means a gate-source voltage when an idling current of a predetermined value is passed.

Since the first resistor (58) and the second resistor (59) satisfy the above conditions, the following operational effects can be obtained. [1] Variations in the threshold value (V _TH1 ) of the first amplifying element (53) in the first semiconductor device (51) can be absorbed by the second semiconductor device (52) side. [2] The first semiconductor device (5
No matter how the 1) and the second semiconductor device (52) are combined, the first and second amplifying elements are connected after connecting the first semiconductor device (51) and the second semiconductor device (52). A constant idling current (I _C ) can always be applied to (53, 55). [3] Therefore, the external resistor (7) for adjusting the idling current becomes unnecessary, and the step of adjusting the idling current can be omitted when manufacturing the SEPP circuit. [4] The first resistor (58) and the second resistor (59) may be incorporated in the first semiconductor device (51) and the second semiconductor device (52) at the time of manufacturing. [5] The increase (V ₀ ) of the voltage level on one side of the first semiconductor device (51) and the second semiconductor device (52) can be absorbed on the other side. [6] The first semiconductor device (51) having the first resistor (58) and the second semiconductor device (52) having the second resistor (59) can be individually sealed with a resin sealing body. . [7] The idling currents of the first semiconductor device (51) and the second semiconductor device (52) can be set to predetermined values in advance. [8] The resistance values of the first resistor (58) and the second resistor (59) can be strictly controlled, and the reliability of the SEPP circuit can be improved.

In the embodiment of the present invention, the first resistor (58)
The resistance value (R ₁ ) of the following formula (1) or (2): R ₁ = [(V _TH1 ) + (V ₀ ) − (V _F1 )] / (I _D ) (1) R ₁ ＝ [( Satisfies V _TH1 ) − (V ₀ )] / (I _D ) (2). Further, the resistance value (R ₂ ) of the second resistor (59) is expressed by the following formula (3) or (4): R ₂ = [(V _TH2 ) − (V ₀ )] / (I _D ) (3) R ₂ = [(V _TH2 ) + (V ₀ ) − (V _F1 )] / ( _ID ) (4) is satisfied.

The first and second resistors (58, 59) have thick film resistors (58a, 59a) whose area can be reduced, and the first semiconductor device (51) and the second semiconductor device (52). ) Are individually sealed resin (6
4, 74). The resistance value of the first or second resistor (58, 59) can be adjusted by changing the area of the thick film resistor (58a, 59a). Further, since the first and second semiconductor devices (51, 52) have the detection terminals (62, 72), for example, the probe of the measuring instrument is brought into contact with the detection terminals (62, 72) to make the first or second semiconductor device. The electrical characteristics of the amplifier elements (53, 55) and the temperature compensating element (54) built in the second semiconductor device (51, 52) can be accurately measured, and the first or second resistor (58, 5)
There is an advantage that the resistance value can be adjusted with high accuracy while measuring the resistance value in 9).

The manufacturing method of the SEPP circuit according to the present invention is as follows.
Amplifier element (53), a first resistor (58) for controlling the voltage applied to the control terminal of the first amplifier element (53), a first resistor (58)
A temperature compensation element (54), a first external lead (66), a first amplification element (53) and a temperature compensation element (54) which are connected in series to A first lead frame assembly (51a) having a thin lead wire (61) and a second amplification element (5
5), a second resistor (59) for controlling the voltage applied to the control terminal of the second amplification element (55), a second external lead (76), a second
And a second lead frame assembly (52a) having a second thin lead wire (71) for electrically connecting between the amplifying element (55) and the second resistor (59) and the like. , The first amplification element
When the current (53) is energized, the product of the current ( _ID ) flowing through the temperature compensation element (54) and the resistance value (R ₁ ) of the first resistor (58) and the temperature compensation element (5
When the sum of the voltage between terminals (V _F1 ) of 4) is higher than the threshold value (V _TH1 ) of the first amplifying element (53) by a certain level (V ₀ ), the first resistance
A step of adjusting (58), and a current (I _D ) flowing through the second resistor (59) by energizing the second amplifying element (55) and the second resistor (59).
The product of the resistance value (R ₂ ) and the threshold value of the second amplification element (55)
(V _TH2) than a predetermined level (V ₀₎ only a low state a second resistor (5
9) adjusting the first lead frame assembly (51
a) and the second lead frame assembly (52a) with a resin sealing body
The first semiconductor device (5) in which the ends of the external leads (66) are led out from the resin encapsulant (64, 74) by individually encapsulating them with (64, 74).
1) and the step of forming the second semiconductor device (52), the first amplifying element (53) and the second amplifying element (55) are connected in series, and the first resistor (58) , The temperature compensating element (54) and the second resistor (59) are connected in series. Further, the first semiconductor device (51) in which the resistance value of the first resistor (58) is adjusted and the second semiconductor device (52) in which the resistance value of the second resistor (59) is adjusted are respectively made of resin. After sealing, the first semiconductor device
Since the (51) and the second semiconductor device (52) are connected, there is an advantage that the value of the idling current (I _C0 ) does not change due to external factors and the stability increases.

In another embodiment of the present invention, the first amplifying element (53), the first resistor (58) for controlling the voltage applied to the control terminal of the first amplifying element (53), and the first resistor (58) 1 external lead
(66), a first lead frame assembly (51a) having a first lead wire (61) for electrically connecting the first amplifying element (53) and the first resistor (58), etc. And the second amplification element (55),
A second resistor (59) for controlling the voltage applied to the control terminal of the second amplifier element (55), a temperature compensation element (54) connected in series with the second resistor (59), and a second resistor (59). A second lead frame assembly (2) having a second lead wire (71) for electrically connecting the external lead (76), the second amplifying element (55) and the second resistor (59), etc. 52a) and the step of preparing the first amplification element (53)
The current (I _D ) flowing through the temperature compensation element (54)
And the resistance value (R ₁ ) of the resistor (58) of the first amplifier element (53)
Adjusting the first resistor (58) to a state lower than the threshold value (V _TH1 ) by a constant level (V ₀ ), and energizing the second amplifier element (55) to supply the second resistor (59). Current (I _D ) and the second resistance (5
The product of the resistance value (R ₂ ) of 9) and the voltage (V _F1 ) between the terminals of the temperature compensation element (54) is at a constant level (V _TH2 ) from the threshold value (V _TH2 ) of the second amplification element (55). _The step of adjusting the second resistance (59) so that it is higher than the first lead frame assembly (51a) and the second resistance (59).
The lead frame assembly (52a) is individually sealed by the resin sealing bodies (64, 74), and the ends of the external leads (66) are led out from the resin sealing bodies (64, 74). A step of forming a semiconductor device (51) and a second semiconductor device (52), and a first amplification element (5
3) and the second amplification element (55) are connected in series, and the first resistance (58), the temperature compensation element (54) and the second resistance (59) are connected in series. .

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the SEPP circuit and its manufacturing method according to the present invention will be described with reference to FIGS. In FIG. 1, the same parts as those shown in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted. The SEPP circuit according to the present embodiment shown in FIG. 1 includes a first semiconductor device (51) and a second semiconductor device (52) connected in series to a DC power supply (9),
Connected in series between the connection point between the first semiconductor device (51) and the second semiconductor device (52) and the negative terminal of the DC power supply (9) and in parallel with the second semiconductor device (52). And a load (10). The first semiconductor device (51) has n
A first amplification element (53) composed of a channel MISFET, a temperature compensation diode (54) as a temperature compensation element connected to the gate of the first amplification element (53), and a first resistance (58). ) Has. The drain of the first amplification element (53) is connected to the positive terminal of the DC power supply (9), and the source is connected to the capacitor (11). The second semiconductor device (52) is a second amplification element composed of a p-channel MISFET.
(55) and a second amplifier connected to the gate of the second amplifying element (55)
Resistance (59), but not a diode for temperature compensation. The source of the second amplification element (55) is a capacitor
The drain is connected to the negative side terminal of the DC power supply (9). As indicated by the broken line, the first semiconductor device (51)
The second semiconductor device (52) and the second semiconductor device (52) are individually resin-sealed electronic components.

In the SEPP circuit shown in FIG. 1, the first resistor
Resistance value of (58) (R₁), The current flowing through the diode (54)
(I_D), The threshold value of the first amplifying element (53) (V_TH1), Fixed value (V₀) And
And the voltage between the terminals of the diode (54) (V_F1) And
A person in charge is required. R₁・ I_D+ V_F1= V_TH1+ V₀ That is, the current (I_D) And the first resistance (5
8) Resistance value (R₁) And the voltage across the diode (54)
(V_F1) Is the threshold (V of the first amplifying element (53)_TH1) More
Constant level (V₀) Only expensive. As shown in FIG. 6 (A), the first
A drain current of about 100mA is applied to the semiconductor chip (53a).
Voltage applied to the diode (54) and the first resistance
The sum of the voltages applied to (58) is the threshold of the first amplifying element (53).
Value (V_TH1) Of the first semiconductor chip (53a)
Source voltage (V_GS1) From a certain level (V₀) Only expensive. This
A certain level (V₀) Is set higher,
The threshold value (V_TH1)
Can be compensated. Constant level (V₀) Adjust the resistance
Initial of first resistance (58) measured before trimming to trim
The voltage value obtained by multiplying the resistance value by the current value 3mA
From the value of the maximum forward voltage applied, the gain of the first amplification element (53)
Gate-source voltage (V_GS1) Is a fixed value less the minimum value of
It Specifically, a certain level (V₀) Is of 0.05-3.0V
Various values can be taken between. Forward current of 3mA
Maximum forward voltage of diode (54) generated when
Value and the number that occurs when a drain current of 100 mA is applied
Gate-source voltage (V_GS1) Minimum
Values are calculated from multiple first leadframe assemblies (51a).
It can be calculated in advance as an average value. First resistance (58)
The initial resistance value of the
It is calculated when it is completed.

Further, in the SEPP circuit shown in FIG.
Of the current (I_D) And the resistance of the second resistor (59)
Value (R₂) And the threshold value of the second amplification element (55) (V_TH2) And fixed
Value (V₀) And the following relations are necessary. R₂・ I_D= V_TH2−V₀ That is, the current (I_D) And the second resistor (5
9) Resistance value (R₂) Is the threshold of the second amplification element (55)
(V_TH2) From a certain level (V₀) Only low. As shown in Figure 6 (B)
Drain of about 100mA on the second semiconductor chip (55a)
Current flowing in the second resistor (59) (I_D)
And the resistance value of the second resistor (59) (R₂) Is the product of the second
Child (55) threshold (V_TH2) Of the second semiconductor chip (55a)
Gate-source voltage (V_GS2) From a certain level (V₀) Only low
Yes. Thus, a constant level (V₀) Should be set lower
Causes the threshold value of the second amplifying element (55) (V_TH2)
The effect of this can be compensated.

At the time of assembly, the first amplifying element (5
The external terminals (66b), (66d) and (66e) in 3) are shown in Fig. 5 respectively.
2 is connected to the external terminals (76b), (76d) and (76e) of the second amplifying element (55) to construct the SEPP circuit shown in FIG.

In operation, control signals having the same size but different phases by 180 degrees are applied to the gate terminals of the first amplifying element 53 and the second amplifying element 55 which are connected symmetrically. .
When the first amplification element (53) is turned on in the positive half cycle,
DC power supply (9) to the first amplification element (53), capacitor (11)
And a current flows through the load (10) and the capacitor (11) is charged. When the second amplification element (55) is turned on in the negative half cycle, the energy stored in the capacitor (11) is supplied to the load (10) through the second amplification element (55). The first amplifying element (53) and the second amplifying element (55) are transistors (MISFET) by flowing a predetermined idling current.
Since the non-linearity of the characteristic curve is mutually compensated, they operate in a complementary manner, so that the linearity is improved and a large output power without distortion can be obtained. Diode for temperature compensation
(54) has a function of compensating for the temperature dependence of the voltage between the gate and source terminals of the first amplifying element (53) and the second amplifying element (55). Further, variations in the threshold value (V _TH1 ) of the first amplifying element (53) in the first semiconductor device (51) are caused by the second semiconductor device (52).
Since it is absorbed by the side, the first
Also, no matter how the semiconductor devices (51, 52) are combined, an idling current of a constant value can always flow through the first and second amplifying elements (53, 55).

When manufacturing the first semiconductor device (51), first, as shown in FIG. 2, an n-channel MI is formed on the support plate (63).
A first lead frame assembly (51a) in which the first semiconductor chip (53a) of the SFET and the circuit board (60) are fixed is prepared. The first lead frame assembly (51a) constituting the first semiconductor device (51) includes a support plate (63) and a plurality of external parts arranged along one edge of the support plate (63). First semiconductor chip fixed to the terminal (66) and one main surface of the support plate (63)
(53a) and the circuit board (60), and the first lead thin wires (61a to 61d) for electrically connecting the first semiconductor chip (53a) and the circuit board (60). In the first lead frame assembly (51a), the first semiconductor chip (53a) and the circuit board (6
0) is electrically connected by the first lead thin wires (61a to 61d), while the circuit board (60) and the external terminals (66) are electrically connected by the first connection thin wires (67). Not connected. The external terminal (66) is, in order from the left of the array, the gate terminal (66a),
They are a resistance connection terminal (66b), a drain terminal (66c), and two source terminals (66d, 66e). The resistor (thick film resistor) (58a) that becomes the first resistor (58), the wiring conductor (65), and the connection terminal (65
a to 65c) and detection terminals (62a to 62d) are formed on one main surface of the circuit board (60).

Next, after setting the idling current required for removing the crossover distortion to 100 mA, a constant current source is connected between the central external terminal (66c) and the electrode (62d), and the semiconductor chip ( A drain current of about 100 mA is applied to 53a). Semiconductor chip (53a) through the first thin lead wire (61a, 61d)
A probe of the measuring instrument is brought into contact with the detection terminals (62a, 62d) electrically connected to the gate electrode and the source electrode of and the gate-source voltage (V _GS ) is measured. Detection terminals (62a, 62a
The d) and the detection terminals (62b, 62c) are formed in an area sufficient for abutting the probe.

Then, the first lead frame assembly (51
A forward current of about 3mA is applied to the diode (54) configured in a) and electrically connected to the anode electrode and cathode electrode of the diode (54) via the first thin lead wires (61a, 61b). The forward voltage (V _F1 ) of the diode (54) is measured by bringing the probe of the measuring instrument into contact with the detection terminals (62a, 62b). In the present embodiment, the diode (54) is formed of a diffusion layer formed in the semiconductor substrate of the semiconductor chip (53a) or polysilicon formed on the upper surface of the semiconductor substrate. 2 of the first amplification element (53) and the second amplification element (55)
In order to compensate the temperature dependence of the gate-source voltage of one semiconductor chip (53a, 55a), all eight diodes (54) are incorporated in the first lead frame assembly (51a), and eight diodes ( Measure the total forward voltage of 54). Depending on the voltage drop of the diode (54) when a forward current of 3 mA is applied, it becomes a dark current, that is, an idling current of about 100.
When the mA drain current flows to the semiconductor chip (53a),
Gate-source voltage of the first semiconductor chip (53a)
(V _GS ), that is, the threshold value (V _TH1 ) is measured, and the forward voltage of the diode (54) is used to determine the resistance value (R ₁ ) of the first resistor (58) based on the following equation (1). To calculate. In equation (1), the diode (5
The current flowing in (4) is ( _ID ) and the terminal voltage of the diode (54) is (V
_F1 ), the threshold value of the first amplifying element (53) is (V _TH1 ), and a fixed value (V ₀ ) which is a constant level. R ₁ = [(V _TH1 ) + (V ₀ ) − (V _F1 )] / (I _D ) (1) Therefore, the measured gate-source voltage (V _GS1 ) of the first semiconductor chip (53) The resistance value (R ₁ ) of the first resistor (58) can be calculated by substituting the forward voltage of the diode (54) and the fixed value (V ₀ ) calculated in advance into the equation (1). .

Next, the first resistor (5) formed on the circuit board (60) of the first lead frame assembly (51a) shown in FIG.
8) Detection terminals (62
b, 62c) by touching the probe of the measuring instrument to the first resistance
Well-known trimming can be performed while measuring the resistance value (R ₁ ) of (58) to adjust the first resistance (58) to the resistance value R ₁ with high accuracy. For example, there is an advantage that the first resistor (58) can be adjusted to an accurate resistance value by cutting off a part of the thick film resistor (58a) by laser trimming or the like, and the adjustment work can be automated.

After adjusting the resistance value R ₁ of the first resistor 58, the circuit board 60 of the first lead frame assembly 51a.
The first connection thin wires (67a to 67d) are connected between the external connection terminal (66) and the external terminal (66). After that, the first lead frame assembly (51a) is provided with a resin sealing body (6
4) to form the support plate (63) by the resin encapsulant (64), the components fixed to the support plate (63) and the external leads (6).
The inner end portions of 6a to 66e) are covered to complete the first semiconductor device (51) shown in FIG.

Next, when manufacturing the second semiconductor device (52), as shown in FIG. 4, the second semiconductor chip (55a) of the p-channel MISFET and the circuit board (70) are supported by the support plate (73). ) Prepare a second lead frame assembly (52a) secured on top. The second lead frame assembly (52a) constituting the second semiconductor device (52) has a support plate (73) as shown in FIG.
A plurality of external terminals (76a to 76e) arranged along one edge of the support plate (73), and a second semiconductor chip fixed to one main surface of the support plate (73). 55a) and circuit board (70)
And the second lead wires (71a to 71d) for electrically connecting the second semiconductor chip (55a) and the circuit board (70). In the second lead frame assembly (52a), the second
The semiconductor chip (55a) and the circuit board (70) are electrically connected by the second thin lead wires (71a to 71d), but between the circuit board (70) and the external terminal (76). Second connection thin wire (77)
Not electrically connected by. The external terminal (76) is a gate terminal (76a), a resistor connection terminal (76b), in order from the right of the array.
A drain terminal (76c) and two source terminals (76d, 76e). Second resistor (59) resistor (thick film resistor) (59a)
The wiring conductor (75), the connection terminals (75a to 75c), and the detection terminals (72a to 72d) are formed on one main surface of the circuit board (70).

Next, after setting the idling current required for removing the crossover distortion to 100 mA, a constant current source is connected between the external terminal (76c) at the center and the electrode (72d), and the second
A drain current of about 100 mA is applied to the semiconductor chip (55a). The probe of the measuring instrument is brought into contact with the detection terminals (72a, 72d) electrically connected to the gate electrode and the source electrode of the second semiconductor chip (55a) through the second thin lead wires (71a, 71d). And measure the gate-source voltage (V _GS ). The detection terminals (72a, 72d) and the detection terminals (72b, 72c) are formed in an area sufficient for abutting the probe.

Then, a drain current of about 100 mA, which is a dark current or an idling current, is applied to the second semiconductor chip (55).
When flowing to a), the gate of the second semiconductor chip (55a)
The voltage between sources (V _GS ), that is, the threshold value (V _TH2 ) is measured, and the resistance value (R ₂ ) of the second resistor (59) is calculated based on the following equation (3). R ₂ = [(V _TH2 ) − (V ₀ )] / (I _D ) (3) In equation (3), the current flowing through the second resistor (59) is changed to (I _D ), second
The threshold value of the amplification element (55) is set to (V _TH2 ), and a fixed level (V ₀ ) is set to a fixed value. Therefore, the measured gate-source voltage (V _GS ) of the second semiconductor chip (55a) and the fixed value calculated in advance
The resistance value R ₂ of the second resistor (59) can be calculated by substituting (V ₀ ) and equation (3).

Next, the second resistor (5) formed on the circuit board (70) of the second lead frame assembly (52a) shown in FIG.
9) The detection terminals (72
b, 72c) by touching the probe of the measuring instrument to the second resistance
Performing well-known trimming while measuring the resistance value of (59),
The second resistor (59) can be adjusted to the resistance value R ₂ with high precision. For example, there is an advantage that the second resistor (59) can be adjusted to an accurate resistance value by cutting off a part of the thick film resistor (59a) by laser trimming and the adjustment work can be automated.

After adjusting the _second resistor 59 to the resistance value R ₂ , as shown in FIG. 5, the second lead frame assembly 5
The second connection thin wires (77a to 77d) are connected between the circuit board (70) of 2a) and the external terminals (76). After that, a resin sealing body (74) is formed on the second lead frame assembly (52a) by a known transfer molding method, so that the resin sealing body (74) supports the supporting plate (73) and the supporting plate (73). ) And the inner ends of the external leads (76a to 76e) fixed thereto are completed to complete the second semiconductor device (52) shown in FIG. 3 and 5
As shown in, since the first semiconductor device (51) and the second semiconductor device (52) have opposite arrangements of the external terminals (66, 76),
When both semiconductor devices are mounted on the main circuit board, the source terminals of the first semiconductor device (51) and the second semiconductor device (52) can be connected by a short wiring conductor.

The above embodiment of the present invention can be modified. For example, instead of connecting the diode (54) between the first resistor (58) and the control terminal of the first amplifying element (53), the first resistor (58) and the second resistor (59) Between diode (54)
May be connected. Further, instead of incorporating the diode (54) in the first semiconductor device (51), the second semiconductor device (5
It can be connected in series with the second resistor (59) in 2).
In this case, the resistance value (R ₁ ) of the first resistor (58) satisfies the following equation (2): R ₁ = [(V _TH1 ) − (V ₀ )] / (I _D ) (2) , The resistance value (R ₂ ) of the second resistor (59) is expressed by the following formula (4): R ₂ = [(V _TH2 ) + (V ₀ ) − (V _F1 )] / (I _D ) (4) Be satisfied.

In the above embodiment of the present invention, MISFE is used.
Although an example using T is shown, instead of MISFET,
Other amplification elements such as bipolar transistors, MESFETs, IGBTs may be used. Further, the diode (54) may be formed in both the first semiconductor device (51) and the second semiconductor device (52). The diode (54) is connected to the first semiconductor device (5
1) or only the first semiconductor device (51) in comparison with the number of diodes (54) in the second semiconductor device (52).
If the number of diodes (54) in
The resistance (58) and the second resistance (59) of A are as set forth in claim 1.
Satisfy the condition of. On the other hand, when the diode (54) is formed only in the second semiconductor device (52), or when compared to the number of diodes (54) in the first semiconductor device (51), the diode in the second semiconductor device (52) When the number of (54) is increased, the first resistor (58) and the second resistor (59) satisfy the condition of B described in claim 1. Furthermore,
In the above-described embodiment, the circuit example in which the capacitor (11) is connected in parallel with the second semiconductor device (52) has been described.
1) can be omitted. In this case, the load (10) is grounded, a positive voltage is applied to the collector or drain of the first amplification element (53), and a negative voltage is applied to the collector or drain of the second amplification element (55). Apply. Further, resistors can be connected to the emitters or sources of the first and second amplifying elements (53, 55). This resistor may be built in the first or second semiconductor device (51, 52) or may be formed externally.

[0029]

As described above, according to the present invention, it is not necessary to adjust the resistance value on the user side, and the dark current, that is, the resistor for adjusting the idling current can be integrally sealed by the resin sealing body. Easy and reliable SE with long life
A PP circuit is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a SEPP circuit according to the present invention.

FIG. 2 is a plan view of a first lead frame assembly used for manufacturing a first semiconductor device.

FIG. 3 is a sectional view of a first semiconductor device.

FIG. 4 is a plan view of a second lead frame assembly used for manufacturing a second semiconductor device.

FIG. 5 is a sectional view of a second semiconductor device.

FIG. 6 is a graph showing the relationship between operating voltage and current of the first and second amplifying elements.

FIG. 7 is a circuit diagram of a conventional SEPP circuit.

[Explanation of symbols]

(51) ・ ・ First semiconductor device, (52) ・ ・ Second semiconductor device, (53) ・ ・ First amplification element, (54) ・ ・ Diode (temperature compensation element), (55) ・ ・Second amplification element, (58)
..First resistance, (59) .. Second resistance,

Front page continuation (51) Int.Cl. ⁷ Identification code FI H03K 17/66 H03K 17/66 C 17/687 17/687 F

Claims (6)

(57) [Claims] 1. A first semiconductor device having a first amplifying element and a first resistor for controlling a voltage applied to a control terminal of the first amplifying element, a second amplifying element and the second amplifying element. And a second semiconductor device having a second resistance for controlling a voltage applied to the control terminal of the amplifying element of SE, in which the first semiconductor device and the second semiconductor device are connected in series.
In the PP circuit, a temperature compensation element is connected in series with the first resistor and the second resistor between the control terminal of the first amplification element and the control terminal of the second amplification element, The sum of the product of the current flowing through the compensating element and the resistance value of the first resistor and the voltage across the terminals of the temperature compensating element is higher than the threshold value of the first amplifying element by a certain level, and The product of the flowing current and the resistance value of the second resistor is lower than the threshold value of the second amplifying element by the certain level, or B the current flowing through the temperature compensating element and the resistance value of the first resistor. Is lower than the threshold value of the first amplifying element by a certain level, and the sum of the product of the current flowing through the second resistor and the resistance value of the second resistor and the terminal voltage of the temperature compensating element is A higher than the threshold value of the second amplifying element by the certain level Alternatively, the first resistance and the second resistance are respectively adjusted to have resistance values satisfying either condition B.
SE, wherein the first semiconductor device and the second semiconductor device are each sealed with a resin sealing body.
PP circuit. 2. The resistance value of the first resistor is expressed by the following formula (1) or
(2): R ₁ = [(V _TH1 ) + (V ₀ ) − (V _F1 )] / (I _D ) (1) R ₁ ＝ [(V _TH1 ) − (V ₀ )] / (I _D ) (2) is satisfied, and the resistance value of the second resistor is expressed by the following formula (3) or (4): R ₂ = [(V _TH2 ) − (V ₀ )] / (I _D ) (3) R ₂ 2. The SEPP circuit according to claim 1, which satisfies the following _formula : [[V _TH2 ) + (V ₀ ) − (V _F1 )] / (I _D ) (4). 3. The first and second resistors have thick film resistors capable of reducing the area, and the first semiconductor device and the second semiconductor device are individually sealed with a resin sealing body. The SEPP circuit according to claim 1 or 2, further comprising: 4. The SEPP circuit according to claim 1, wherein each of the first semiconductor device and the second semiconductor device has a detection terminal. 5. A first amplifier element, a first resistor for controlling a voltage applied to a control terminal of the first amplifier element, and the first resistor.
Lead frame having a temperature compensating element, a first external lead, and a first lead thin wire electrically connecting between the first amplifying element and the first resistor connected in series to the resistor An assembly, a second amplification element, a second resistance for controlling a voltage applied to a control terminal of the second amplification element, a second external lead, the second amplification element and the second resistance. A step of preparing a second lead frame assembly having a second lead thin wire that electrically connects between the first lead element and the second lead frame assembly; Adjusting the first resistance such that the sum of the product of the resistance value of the first resistance and the voltage across the temperature compensation element is higher than the threshold value of the first amplification element by a certain level. When the second amplifying element is energized, the current flowing in the second resistor and the second resistor Adjusting the second resistance so that the product of the resistance value and the resistance value of the second amplification element is lower than the threshold value of the second amplifying element by the certain level, and the first lead frame assembly and the second lead frame set. Forming a first semiconductor device and a second semiconductor device that individually seal the solid body with a resin encapsulant and lead out the end portions of the external leads from the resin encapsulant; Connecting the first amplifying element and the second amplifying element in series, and connecting the first resistor, the temperature compensating element, and the second resistor in series, the SEPP circuit. Manufacturing method. 6. A first amplifier element, a first resistor for controlling a voltage applied to a control terminal of the first amplifier element, a first external lead, the first amplifier element and the first resistor. A first lead frame assembly having a first thin lead wire for electrically connecting between the second amplifying element and a second amplifying element, and a second controlling a voltage applied to a control terminal of the second amplifying element. Resistance of
A second lead frame set having a temperature compensating element connected in series to the second resistor, an external lead, and a second lead thin wire electrically connecting the second amplifying element and the second resistor. A step of preparing a solid, and a product of a current flowing through the temperature compensating element and a resistance value of the first resistor when the first amplifying element is energized to have a constant level higher than a threshold value of the first amplifying element. Only the first to the low state
A step of adjusting the resistance of the second amplification element, and a product of a current flowing through the second resistance and a resistance value of the second resistance and a voltage between terminals of the temperature compensation element. Adjusting the second resistance so that the sum is higher than the threshold value of the second amplifying element by the constant level, and the first lead frame assembly and the second lead frame assembly are sealed with resin. Forming a first semiconductor device and a second semiconductor device, which are individually sealed by means of, and lead out the end portions of the external leads from the resin sealing body; Connecting the two amplifying elements in series, and connecting the first resistor, the temperature compensating element and the second resistor in series, the SEPP circuit manufacturing method.