JP3374813B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor in which a bias voltage does not have a deviation in circuit design even if a deviation occurs in the depth of an emitter junction, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a logic circuit using bipolar transistors, differential pairs (differential amplification pairs) are often connected in multiple stages. The differential pair is composed of two bipolar transistors (hereinafter referred to as transistors). The emitter of each transistor is connected to a common constant current source, and the collector is connected to a power source through a resistor. ing. In a logic circuit in which a plurality of stages of such differential pairs are connected, different voltages are applied to the bases of the transistors in the operating stages. That is, when the input voltage is applied, the operating stage of the transistor switches,
The transistor in the next stage operates.

Generally, in a logic circuit using a bipolar transistor, a base-emitter forward voltage V _{BE of the} transistor is used as an input threshold voltage VIN.

For example, if all the transistors forming the differential amplifier circuit have exactly the same characteristics,
The circuit can obtain the characteristics as designed. However, in reality, the characteristics of transistors are slightly different.
Therefore, the input threshold voltage of each transistor forming a pair varies, and as a result, there is a deviation in the switching voltage V _{f of the} differential pair (the voltage that switches which of the two transistors forming the differential pair operates). Occurs.

The switching voltage V _f of the differential pair is a voltage applied between the base and the emitter in order to obtain the same collector current in the transistors manufactured to have the same circuit design. _If a deviation occurs between the pair of switching voltages V _f , the current output to the collector differs for each transistor pair even when the pair of input voltages are exactly the same.

From the above, when the logic circuit in which the differential pairs are connected in multiple stages is operated, the deviation of the switching voltage V _f of the differential pair of each stage and the differential pair of the next stage accordingly. Coupled with the deviation of the signal pair transmitted to the
The deviation may be amplified, which may cause a decrease in circuit operation margin with respect to fluctuations in the power supply voltage and deterioration of frequency characteristics.

The main causes of the deviation of the switching voltage V _f of the differential pair are (1) deviation of the effective area of the emitter-base junction, (2) deviation of resistance such as emitter resistance, and (3)
The deviation of the profile such as the base profile is included.

Among these factors, (1) the deviation of the effective area of the emitter-base junction is kept within a certain range by suppressing the variation of the effective area of the emitter-base junction due to the progress of lithography technology. I can control it.

(2) The deviation of the emitter resistance depends on the deviation of the effective area of the emitter-base junction. That is, since the emitter resistance depends on the emitter-base junction area and is affected by it, the deviation in the junction area can be suppressed if the deviation in the junction area can be suppressed. That is, if the junction area is large, the emitter resistance is small, and if the junction area is small, the emitter resistance is large.

As described above, the deviation of the switching voltage V _f of the differential pair due to the factors (1) and (2) can be suppressed by using the conventional technique.

However, regarding (3) the deviation of the base profile, no effective solution has been proposed so far. In recent years, in the manufacture of bipolar transistors,
In order to improve the cutoff frequency f _T , since the junction is made extremely shallow, the deviation of the base profile appears remarkably and its influence is great.

[0012]

In the production of bipolar transistors, the techniques used for forming the base include
There are an ion implantation method and an epitaxial growth method.

When the base region is formed by the ion implantation method, the concentration profile of the impurities contained in the base region is a profile close to a Gaussian distribution, which is a profile that changes in the depth direction. Therefore, when the emitter region is formed, the bonding surface of the emitter region varies.

On the other hand, when the base region is formed by the epitaxial growth method, the concentration of the p-type (or n-type) impurity contained in the base region is not related to the depth of the emitter junction. That is, p-type (or n-type) included in the base region of any transistor on the same wafer
(Type) impurities have the same concentration. On the other hand, since the emitter region is formed by thermally diffusing or ion-implanting an n-type (or p-type) impurity in the base region, the concentration distribution of the n-type (or p-type) impurity differs for each transistor. Therefore, the depth of the emitter junction has a deviation.

Further, in order to reduce ohmic resistance, a polysilicon film or the like may be formed on a region where an emitter is to be formed. In this case, the emitter is formed by performing impurity diffusion from the polysilicon film or the like. However, due to the natural oxide film formed between the polycrystalline film such as the polysilicon film and the region where the emitter is to be formed, There are variations in diffusion. As a result, the depth of the emitter junction varies.

As described above, the concentration of impurities contained in the base region changes in the depth direction and the depth of the emitter junction also has a deviation, which causes the deviation of the base profile. Further, that also causes a deviation in the base width W _B.

Since the current flowing through the base of the bipolar transistor is a diffusion current, the base width W _B is fixed when the voltage applied to the input of the transistor is fixed at a certain value V _BE (the input threshold voltage is when a V _bE), with respect to the collector current _{I C,} having the relationship of I C α1 / _{W B.} That is, the collector current is inversely proportional to the base width. From this, it is understood that the collector current I _C also changes as the base width W _B changes. That is, the deviation in the depth of the emitter junction affects the collector current I _C.

In the multi-stage differential amplifier circuit, when the collector current I _C differs by ΔIc, the voltage output through the resistor R differs, so that only the voltage R × ΔIc applied to the base of the transistor in the next stage. Will be different. That is,
The change in the collector current I _C affects the switching voltage V _f (bias voltage V _f ) of the differential pair.

Therefore, in the multistage differential amplifier circuit, when the emitter junctions of the transistors are different in depth, the collector current I _C is different, and therefore the switching voltage V _f (bias voltage V _f ) of the differential pair. Deviation will occur.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a bipolar transistor in which bias voltage is less likely to have a deviation in circuit design and a method for manufacturing the same. Another object of the present invention is to facilitate circuit design and provide a circuit having desired characteristics.

[0021]

In order to achieve the above object, a bipolar transistor according to a first aspect of the present invention is a bipolar transistor having a collector region, a base region and an emitter region, wherein the base region is A region including at least a portion in contact with the emitter region has a profile in which the square of the intrinsic carrier concentration has a negative linear function change with respect to depth.

A bipolar transistor according to a second aspect of the present invention is a bipolar transistor having a collector region, a base region and an emitter region, wherein a region including at least a portion of the base region in contact with the emitter region is , Its intrinsic carrier concentration _ni is
It is characterized in that it has approximately the profile shown in the above-mentioned mathematical expression 1.

According to the bipolar transistor according to the first and second aspects, the intrinsic carrier concentration n _i at the base region of the portion in contact with at least the emitter region, FIG. 2
As illustrated in, the depth decreases linearly.
When such characteristics are given to the base region, the collector current does not change so much even if the depth of the junction surface between the emitter and the base changes. Therefore, a bipolar transistor having a small bias voltage deviation and a differential pair thereof can be obtained, the circuit design becomes easy, and the circuit can operate without being affected by the deviation.

A bipolar transistor according to a third aspect of the present invention is a bipolar transistor having a collector region, a base region, and an emitter region, wherein a part or all of the base region is made of silicon and germanium. It is characterized in that it is made of a semiconductor material made of an alloy and has a profile in which the proportion of germanium at least in the base region in contact with the emitter region changes logarithmically in the depth direction.

A bipolar transistor according to a fourth aspect of the present invention is a bipolar transistor having a collector region, a base region, and an emitter region, wherein a part or all of the base region is made of silicon and germanium. It is characterized in that it is made of a semiconductor material made of an alloy Si _{1- a} Ge _a, and the composition ratio a of germanium has a profile expressed by the above-mentioned mathematical expression 2 in at least a portion of the base region in contact with the emitter region.

According to the bipolar transistors of the third and fourth aspects, the composition ratio of the base semiconductor material is as shown in FIG.
As illustrated in, the logarithmic function changes in the depth direction. When the base region is formed with such a composition, even if the depth of the junction surface between the emitter and the base changes,
The collector current does not change much. Therefore, a bipolar transistor having a small bias voltage deviation and a differential pair thereof can be obtained, the circuit design becomes easy, and the circuit can operate without being affected by the deviation.

In the method for manufacturing a bipolar transistor according to the fifth aspect of the present invention, the square of the intrinsic carrier concentration has a negative linear function with respect to the depth on a semiconductor layer functioning as a collector. A single crystal semiconductor layer having a changing profile and functioning as a base is formed, and an impurity is added to the formed base layer to form a single crystal semiconductor layer functioning as an emitter region.

Further, in the method for manufacturing a bipolar transistor according to the sixth aspect of the present invention, a portion which is made of a semiconductor material made of an alloy of silicon and germanium and is in contact with at least the emitter region is formed on the semiconductor layer which functions as a collector. In the base region, the ratio of germanium has a profile that changes logarithmically in the depth direction.

Further, a method of manufacturing a bipolar transistor according to a seventh aspect of the present invention is configured such that a semiconductor material made of an alloy Si _1-a Ge _{a of} silicon and germanium is formed on a semiconductor substrate and at least an emitter region is formed. The germanium composition ratio a in the contact base region
The method is characterized by forming a synthetic semiconductor layer having the profile shown in Formula 2 and diffusing impurities into the surface region of the synthetic semiconductor layer to form an emitter region.

The base region is formed, for example, by epitaxial growth.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 shows the profile of the base semiconductor material composition of this embodiment. FIG. 2 shows a profile of the intrinsic carrier concentration of this embodiment. FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device according to the present embodiment.

The transistor according to this embodiment is an npn-type bipolar transistor (hereinafter referred to as a transistor) in which a SiGe alloy made of Si (silicon) and Ge (germanium) is used as a base semiconductor material. The base region is doped with B (boron),
The emitter region is doped with P (phosphorus).

First, in a multistage differential amplifier circuit,
The principle for obtaining the same collector current I _C in order to prevent the switching voltage V _f of the differential pair from having a deviation will be described.

Common emitter current amplification factor h of transistor
_FE is because it has a value of about 70 to 200, in the transistor alone, its current amplification factor _{h FE h FE} ≒ 1
When it is set to 00, it can be considered that (collector current I _C ) = (emitter current I _E ) − (base current I _B ) ≈ (emitter current I _E ), and Formula 3 holds.

[Equation 3] Where A _E : emitter junction area, q: elementary charge,
W _B: base _width, N B (x): base impurity concentration at a depth _x, D n (x): diffusion constant of the minority carriers in the depth _x, n i (x): the intrinsic carrier concentration in the depth x, V _BE : bias voltage, x: position in base region (that is, depth from emitter junction surface).

Here, in order to facilitate understanding, the intrinsic carrier concentration of the region of the neutral base region in contact with the emitter is n _i , and the average value of the minority carrier diffusion constants in the base is D _n. , The average value of the base impurity concentration is N _B
Then, Equation 3 can be approximated to Equation 4.

[Equation 4]

In order to prevent the switching voltage V _{f of the} differential pair from having a deviation, I _C shown in the equation 4 does not change even if the base width W _B has a variation ΔW _B. .

Therefore, the width of the shallowest emitter junction position and the deepest emitter junction position is defined as d with the emitter junction position of the transistor having the shallowest emitter junction as a reference.
Let W _{B be} the base width of the transistor having the shallowest emitter junction. Since the width d between the shallowest emitter junction position and the deepest emitter junction position is based on the shallowest emitter junction position, it has different values depending on the substrate (wafer) on which the transistor is formed.

Under the above conditions, it is sufficient that the equation 5 is satisfied.

[Equation 5]

If the condition of Expression 5 is satisfied, the collector current I _C shown in Expression 2 can be made constant even if the base width W _B of the completed transistor varies. That is, if Expression 5 is satisfied, the same collector current I _C can be obtained when the bias voltage V _BE is applied to the transistor. Therefore, the deviation of the switching voltage _Vf of the differential pair can be suppressed. Further, even if this condition is not completely satisfied, if it is close to this condition, the variation in V _f can be reduced.

Next, a profile of the intrinsic carrier concentration n _{i that} satisfies the condition of Expression 5 is obtained.

When Equation 5 is modified, Equation 6 is established.

[Equation 6]

Here, assuming that the impurity concentration N _B in the base region is constant in the depth direction, N _B (d) / N _B is given in Equation 6.
By substituting (0) = 1, Expression 7 holds.

[Equation 7]

In the equation (7), the variable d represents the width of the shallowest emitter junction position and the deepest emitter junction position based on the position of the emitter junction of the transistor having the shallowest emitter junction. Expression 7 is an expression representing the intrinsic carrier concentration between the position of the shallowest emitter junction and the position of the deepest emitter junction. here,
To guide the expression representing the intrinsic carrier concentration n _i in the depth direction of the intrinsic region of the transistor (single crystal region), the variable d, replacing the depth of the intrinsic region of the transistor to the variable x to the variable. In Equation 7, the shallowest because the intrinsic carrier concentration at the position of the emitter junction n _{i 2} ⁽⁰⁾ is a constant, by replacing variable d for the variable x, the intrinsic carrier concentration in the depth direction of the intrinsic region of the transistor n _i Equation 8 is obtained as an equation expressing

[Equation 8] _{^{n i 2 (x) ≒ n}} i 2 (0) · (1-x / W B)

[0045] Thus, the profile of the intrinsic carrier concentration n _i for satisfying Equation 8 becomes as shown in FIG.

Since it suffices to obtain the intrinsic carrier concentration n _i as expressed by the equation 7 at least in the vicinity of the region where the emitter is formed by the diffusion of impurities, in the present embodiment, the base / collector junction is formed from the hetero junction surface. plane, showing a profile in accordance with equation 8 that is x = 0 in the region of x = _{W B.} Therefore, if Equation 8 is filled between the x = 0 the x = W _B, condition the collector current I _C becomes constant can be obtained. That is, in the multistage differential amplifier circuit, even if the base width W _B varies, the same collector current I _C can be obtained, and the deviation of the differential pair switching voltage V _f can be suppressed. .

Next, the intrinsic carrier concentration n in the base region
A profile of the base semiconductor material composition is calculated such that _i satisfies the relationship of Expression 7.

[0048] Between the semiconductor intrinsic carrier concentration n _i and bandgap E _g is generally relationship is established as shown in Equation 9.

[Equation 9] N _V : Effective density of states in valence band, N _C : Effective density of states in conduction band

That is, Expression 10 is obtained by modifying Expression 9.

[Equation 10] E _g =-(kT / q) · ln (n _i ² / (N
_V・ N _C ))

As described above, when the width of the shallowest emitter junction position and the deepest emitter junction position is d with reference to the emitter junction position of the transistor having the shallowest emitter junction, the forbidden state at the shallowest emitter junction position is set. When the band width and the forbidden band width at the deepest emitter junction position are E _g (0) and E _g (0) + ΔE _g (d), respectively, Formula 11 is established from Formula 7 and Formula 10.

[Equation 11]

The lattice constants of Si and Ge used in the base semiconductor material of the transistor according to the present embodiment are Si 0.54 nm and Ge 0.55 nm.
In general, when a semiconductor made of a mixture and a single element semiconductor are in contact with each other, stress is applied between atoms unless the lattice constants of the two are matched. The forbidden band width of a semiconductor is a physical quantity determined by the influence of the lattice constant and the potential distribution of atomic nuclei. That is, when the lattice constant changes, the forbidden band width of the semiconductor also changes. Therefore, the forbidden band width of the SiGe alloy is determined by the mixing ratio of the two and the stress applied to the SiGe alloy.

The forbidden band width of Si at room temperature is about 1.12.
The forbidden band width of 4 eV and Ge is about 0.67 eV. Si
The ratio of Ge in the Ge alloy is a and the ratio of Si is 1-a.
Then, when the Ge content is small (that is, a is 1
(If it is sufficiently smaller than −a), the forbidden band width E _g of the SiGe alloy can be approximated by Expression 12.

## EQU12 ## E _g (Si _1-a Ge _a ) = E _g (Si)-
0.76 × a (0 ≦ a ≦ 0.1)

That is, G in the Si _1-a Ge _a alloy
Equation 13 is obtained as the composition ratio of e.

A = (E _g (Si) −E _g (Si _1−a Ge)
_a )) / 0.76

Therefore, from Equation 11 and Equation 13, Equation 1
4 is introduced.

[Expression 14] a (d) ≈ (kT / q) · (1 / 0.76)
_{· Ln (W B / (W} B -d))

In Equation 14, the variable d is the emitter connection.
Based on the position of the emitter junction of the shallowest transistor
, The shallowest emitter junction position and the deepest
Shows the width of the mitter joining position. Equation 14 is the shallowest
Position of the deepest emitter junction and the position of the deepest emitter junction
It is a formula showing the composition ratio of Ge between and. here,
In the depth direction of the intrinsic region (single crystal region) of the transistor
In order to derive an equation expressing the composition ratio of Ge,
In the variable x with the depth direction of the intrinsic region of the transistor as the variable
replace. Therefore, the depth of the intrinsic region of the transistor
Si in the direction _1-aGe_aComposition of Ge in alloy
Equation 15 is obtained as a relational expression expressing the ratio a.

Mathematical Expression 15 a (x) ≈ (kT / q) · (1 / 0.7
_{6) · ln (W B /} (W B -x))

At room temperature, kT / q = 0.025, so by substituting this into Equation 15, Equation 16 is obtained.

[Number 16] a (x) ≒ (1/30) · ln (W B / (W B -x))

From the equation 16, the composition ratio of Ge is a = 0 at the depth x = 0. That is, the Ge composition ratio becomes 0 at the hetero interface. Further, the depth x = W _B, although natural logarithm becomes infinite, it becomes a profile which Ge concentration near the region where the emitter by impurity diffusion are formed is represented by Equation 16. Therefore, in this embodiment, to create a profile that follows from a depth x = 0 in Equation 16 with x = W B _{/ 2} region.

Substituting x = W _B / 2 into Equation 16,
It becomes a≈0.023. That is, the Ge molar concentration in SiGe near the middle of the base width is about 2.3%.

Therefore, the profile of the base semiconductor material composition such that the intrinsic carrier concentration n _i in the base region satisfies the relation of Expression 8 is as shown in FIG.

Therefore, by adjusting the composition of Si and Ge so that the ratio a of Ge increases logarithmically from the vicinity of the surface of the base epitaxial layer toward the depth direction, the depth of the emitter junction can be adjusted. Even if there is a deviation, the collector current I _C can be made the same. As a result, the deviation of the switching voltage V _f of the differential pair can be suppressed. Even if this condition is not completely satisfied, it is possible to reduce the variation of V _f if a base profile close to this condition can be realized.

Next, a method of manufacturing the bipolar transistor having the above structure will be described.

First, as shown in FIG. 3A, an n-type silicon substrate 1 functioning as a collector is prepared (a p-type silicon substrate may be provided with an n-type collector region). An oxide film 2 is formed on the n-type silicon substrate 1, a portion on the base formation planned region is removed by a lithography process, and an opening is formed.

Next, in the region where the oxide film 2 is removed, SiG
The e-alloy is epitaxially grown to form the base region 3.

For example, when vapor phase epitaxial growth of a SiGe alloy is performed, the components of the Si-based reaction gas and the Ge-based reaction gas are changed over time. That is, the proportion of the Ge-based gas is reduced according to the growth of the epitaxial layer. For example, Si ₂ H ₆ is used as the Si-based reaction gas, and GeH ₄ is used as the Ge-based reaction gas. Figure 1
As shown in the profile of Fig. 2, the GeH ₄ supply amount is increased so that the Ge concentration rises from 0% to about 10% within a range of about 0.2 nm from the vicinity of the collector region, and the GeH ₄ is supplied near the middle of the base layer. Grow the SiGe alloy. Then, from there to a thickness of about 2.0 nm, as the Ge concentration is decreased a linear function manner, further Ge concentration from there to a thickness of about 2.0 nm decreases logarithmically, GeH ₄
To reduce the supply of. Thus, the epitaxial layer is grown while changing the Ge concentration.

That is, when the SiGe alloy is epitaxially grown, the components of the Si-based reaction gas and the Ge-based reaction gas are changed with the passage of time (the proportion of the Ge-based gas is decreased according to the growth of the epitaxial layer. ) G is grown at a depth d from the surface of the completed epitaxial layer (or the shallowest expected emitter junction position).
Crystal growth is performed on a SiGe alloy in which e is included in the ratio a (d) shown in Expression 16.

At this time, boron having a concentration of about 5 × 10 ¹⁸ cm ⁻³ is added as an electrically active impurity.

Therefore, as shown in FIG. 1, the concentration of boron is constant regardless of the depth, and the proportion of Ge increases from the surface of the epitaxial layer according to the logarithm of the distance. An epitaxial layer (base layer) having a profile that increases (in a linear function) is obtained.

The specific crystal growth conditions are shown below. In recent years, the ultra-high vacuum chemical vapor deposition method (UHV-CVD), which has been attracting attention as a precise control method for SiGe alloy films, is similar to the crystal growth method called molecular beam epitaxy method.
This is a method using an ultra-high vacuum chamber. The application to the bipolar transistor was made by F. satoet by the present inventor.
al., “A super self-aligned selectively grown SiGe
base (SSSB) bipolar transistor fabricated by cold
-wall type ".

When a SiGe alloy base is formed using the above method, for example, the temperature of the silicon substrate 1 is 605 ° C.
And Si ₂ H ₆ is 3 sccm and GeH ₄ is 2 sccm.
When used at a ratio of 10%, a SiGe alloy base having a Ge concentration of 10% is formed. Ge concentration is 0 to 1
In order to contain 0%, 2 sccc of GeH ₄
It may be adjusted within the range of m or less.

B ₂ H ₆ is used as a reaction gas for doping the base region with boron.

Next, after forming the base region 3, FIG.
As shown in, an oxide film 4 is formed on the entire surface of the wafer.

After that, a region other than the region where the base electrode is to be formed is covered with a photoresist mask, and boron is ion-implanted to form a diffusion layer 5 as shown in FIG. 3C. Then, the oxide film on the region where the emitter region is to be formed is removed by a lithography process, and an opening is formed as shown in FIG.

Next, as shown in FIG. 3D, a polysilicon film 6 is deposited by LPCVD (Low Pressure Vapor Deposition) method, and phosphorus is added to the base region 3 by thermal diffusion or ion implantation. Then, the emitter region 7 is formed. At this time, phosphorus is added so as not to penetrate the base region 3.

At this time, the position of the emitter junction surface (base-emitter interface) varies a little, but as shown in FIG. 1, the position where the emitter junction surface is formed is Ge in the crystal.
Is the position where the ratio of is changing logarithmically, and
As shown in FIG. 2, this is a region in which the square of the intrinsic carrier concentration decreases linearly with depth.

After forming the emitter region 7, an oxide film 8 is formed on the entire surface of the wafer, a hole is formed in a region where an electrode is to be formed by a lithography process, and sputtering or the like is used.
A metal film is formed on the entire surface of the wafer.

Then, as shown in FIG. 3E, unnecessary portions of the metal film formed on the entire surface of the wafer are removed by a lithography process to form electrodes 9 and 10.

That is, by using the above manufacturing method,
To manufacture a bipolar transistor in which the same collector current I _C can be obtained even if there is a deviation in the depth of the emitter junction, and there is no deviation in the switching voltage V _f (bias voltage V _f ) of the differential pair. You can

[0078]

EXAMPLE A bipolar transistor of the present embodiment was actually manufactured, and the deviation of the bias voltage V _f of the conventional bipolar transistor was compared. Transistors each having an emitter area of 0.6 μm × 8.0 μm were formed in a matrix on the wafer by using the method of the above-described embodiment and the conventional manufacturing method. Next, the bias voltages V _f1 , V _f2 , V _f3 , ... Of the transistors on the wafer surface are measured, and the bias voltage difference | V _f1 between adjacent transistors is measured.
_{-V f2 |, | V f2 -V} f3 |, asked for ..., to measure the standard deviation σ.

As a result, the transistor according to the conventional profile shown in FIG. 4 has σ = 1.4 mV, but the transistor according to the present embodiment has σ = 1.1 mV, showing an improvement of about 20%. Was given.

As is clear from the above results, by using the transistor according to the present embodiment, it is confirmed that the deviation of the bias voltage V _f can be suppressed even if the depth of the emitter junction is different. .

In the present embodiment, SiGe alloys are used as the two or more types of semiconductor materials in the base region, but other combinations of semiconductor materials can be used if the principles of the present invention are used.

For example, the composition ratio of Si and C in SiC (silicon carbide) may be changed. Also,
Even if a base semiconductor material made of SiGeC or SiC and Si is used, the same effect as this embodiment can be obtained.

In this embodiment, the base region is doped with boron and the emitter region is doped with phosphorus, but other impurities may be doped. For example, arsenic may be used as an impurity in the emitter region.

Further, in this embodiment, the method of forming the base region by the selective epitaxial growth is used, but non-selective epitaxial growth may be used.

Further, in the present embodiment, the Ge molar concentration is increased from 2.3% to about 10% as the depth of the base region becomes deeper. In order to form an accelerating electric field,
It is not necessary to have such a profile. For example,
A fixed value of 2.3% may be used.

Further, in the bipolar transistor using the polysilicon emitter technology, the base semiconductor material composition may be set so that the forbidden band width E _g in the neutral base region on the emitter side becomes the formula (17).

[Equation 17] E _g (d) = E _g (0) · kT · ln (1-
d _{/ W} B)

The present invention is not limited to the above embodiment, and various applications and modifications are possible. For example, in the above embodiment, an NPN transistor is taken as an example,
Although the present invention has been described, it is also applicable to, for example, a PNP transistor.

[0088]

As described above, according to the present invention,
It is possible to provide a bipolar transistor in which the bias voltage apparently has no deviation. Further, the circuit design is facilitated, and the circuit operation close to the design specification can be obtained.

[Brief description of drawings]

FIG. 1 shows a profile of a base semiconductor material composition of the present embodiment.

FIG. 2 shows a profile of intrinsic carrier concentration according to the present embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the present embodiment.

FIG. 4 shows a profile of a conventional base semiconductor material composition.

[Explanation of symbols]

1 n-type silicon substrate 2, 4, 8 oxide film 3 base area 5 diffusion layer 6 Polysilicon film 7 Emitter area 9 Emitter electrode 10 Base electrode

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-3-292740 (JP, A) JP-A-4-196436 (JP, A) JP-A-9-260397 (JP, A) J. C. Sturm, et. a. , "Graded-Base Si / Si1-xGex / Si Heter ojunction Bipolar Transistors Grown by Rapid Thermal C hemical Vapor, Depo sition with Near-I deal Electrical Ch aracteristics", IEE E ELECTRON DEVICE LETTERS, 6 May 1991, VO L. 12, NO. 6, pp. 303-305 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/8222-21/8228 H01L 21/8232 H01L 27 / 06 H01L 27/08 H01L 27/082

Claims (8)

(57) [Claims] 1. A bipolar transistor including a collector region, a base region, and an emitter region, wherein a region of at least a portion of the base region in contact with the emitter region has a square of an intrinsic carrier concentration with respect to a depth. A bipolar transistor having a profile whose slope changes in a negative linear function. 2. A collector region, a base region, in a bipolar transistor comprising an emitter region, a region including a portion in contact with the at least the emitter region of said base region, its intrinsic carrier concentration n _i, approximately formula 1. A bipolar transistor having the profile shown in 1. [Number 1] ^{_{n i 2 (x) ≒ n}} i 2 (0) · (N B (x) /
N _B (0)) · (1−x / W _B ), where x is the depth in the intrinsic region of the transistor, n _i (x) is the intrinsic carrier concentration at the position where the depth is x, N _B (X) is the impurity concentration at the position where the depth is x, and n _i (0), N _B (0), and W _B are constants, respectively. 3. A bipolar transistor having a collector region, a base region and an emitter region, wherein a part or all of the base region is made of a semiconductor material made of an alloy of silicon and germanium, and at least the emitter region is provided. A bipolar transistor characterized in that the proportion of germanium in the base region of the contact portion has a profile that changes logarithmically in the depth direction. 4. A bipolar transistor having a collector region, a base region, and an emitter region, wherein a part or all of the base region is made of a semiconductor material made of an alloy Si _{1- a} Ge _{a of} silicon and germanium. And a composition ratio a of germanium in at least a portion of the base region which is in contact with the emitter region has a profile represented by Formula 2. [Number 2] a (x) ≒ (1/30) · ln (W B / (W B -x)) ( profile of the base semiconductor material composition at room temperature) where, x is the depth in the intrinsic region of the transistor is, a (x) is the concentration of germanium at the position where the depth is x, and W _B is a constant. 5. A region which functions as a base is formed on a semiconductor layer which functions as a collector, which has a profile in which the square of the intrinsic carrier concentration changes in a negative linear function with respect to the depth. Then, an impurity is added to the formed base layer to form a region functioning as an emitter. 6. A semiconductor material, which is partially or wholly made of an alloy of silicon and germanium, is formed on the semiconductor layer functioning as a collector, and the proportion of germanium changes logarithmically with respect to the depth direction. A method of manufacturing a bipolar transistor, comprising forming a region having a profile that functions as a base and forming an emitter region by adding an impurity to the formed region. 7. A semiconductor substrate is partially or wholly formed of a semiconductor material made of an alloy Si _1-a Ge _{a of} silicon and germanium, and the composition ratio a of germanium has a profile shown in the mathematical formula 2. A method of manufacturing a bipolar transistor, comprising forming a synthetic semiconductor layer, and diffusing impurities in a surface region of the synthetic semiconductor layer to form an emitter region. 8. The method for manufacturing a bipolar transistor according to claim 5, 6 or 7, wherein the base region is formed by epitaxial growth.