JP3374433B2 - Clock signal correction circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk device such as a magnetic disk device or an optical disk device, and more particularly, a plurality of clock marks for giving a time standard are embedded in advance in a data track on the disk surface at the time of manufacturing the disk. Such as the so-called "sampled servo system"
The present invention relates to a clock signal correction circuit suitable for the disk device.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional clock generation circuit.
A configuration shown in 2 is known. The clock generation circuit shown in FIG. 12 is a so-called PLL (Phase L).
This is called an "ockLoop" circuit. The PLL circuit 30 includes a phase comparator 31, a loop filter 32, a VC.
It includes an O (voltage controlled oscillator) 35 and a frequency divider 36. The clock signal reproduced from the disc is supplied to one input of the phase comparator 31. The clock signal output from the VCO 35 is supplied to the other input of the phase comparator 31 with its frequency reduced to 1 / N by the frequency divider 36. The loop filter 32 performs a predetermined filtering process such as low-pass filtering on the output of the phase comparator 31 and supplies the output to the VCO 35.
A clock signal having a phase corresponding to the input voltage is output. VC
The clock signal output from O35 is locked to the phase of the reproduction signal from the disc.

[0003]

The above-described conventional clock generation circuit has the following problems in generating a highly accurate clock signal.

(1) When the disk is chucked on the spindle, the center of the rotation axis and the center of the track circle are offset, that is, eccentricity causes a high speed in a portion where the track circle has a substantial radius. On the other hand, and in the portion where the track circle has a small radius, the effective peripheral speed fluctuates toward the low speed side, which causes a large phase fluctuation in the reproduced clock signal from the track.

(2) Further, if the low-pass gain of the PLL loop is increased in order to sufficiently suppress the amount of phase fluctuation caused by eccentricity, the noise in the high-pass is increased due to the widening of the band associated therewith, so that the PLL is reduced. The eccentricity of the disc cannot be accurately followed.

(3) Further, in a storage device having a plurality of disk surfaces, when the disk surface to be processed is switched, the eccentricity of the disks before and after the switching is different,
It is difficult to immediately follow the disc eccentricity after switching.

A first object of the present invention is to provide a clock signal correction circuit which can accurately follow the eccentricity of a disk.

A second object of the present invention is to provide a clock signal correction circuit capable of immediately following the eccentricity of the switched disk when the disk surface to be processed is switched when there are a plurality of disk surfaces. It is in.

[0009]

[0010]

A first clock signal correction circuit according to the present invention comprises a phase comparator (for example, the phase comparator 31 in FIG. 1) and a predetermined filter processing for the output of the phase comparator. And a voltage-controlled oscillator (for example, the voltage-controlled oscillator 35 in FIG. 1) that outputs a clock signal having a phase or frequency corresponding to the output of the filter. Comparator measures the eccentricity of the disk and the PLL circuit that outputs the phase difference between the clock signal read from the disk and the clock signal fed back from the voltage controlled oscillator.
Eccentricity measuring means (for example, eccentricity measuring unit 2 in FIG. 4)
5) and the eccentricity measured by this eccentricity measuring means
To a speed (for example, in FIG.
Calculation unit 252) and the speed calculated by this calculation means
Is stored as a signal corresponding to the eccentricity of the disk (for example, the eccentricity storage unit 26 in FIG. 1, or
4) and a correction means (for example, a drawing shown in FIG. 4) for adding a signal corresponding to the eccentricity amount stored in this storage means to the output of the loop filter in synchronization with the rotation of the disk and supplying it to the voltage controlled oscillator. 1 reading circuit 27, D / A converter 28, feedforward compensator 29, switch 34 and analog adder 33, or selection units 27A, D of FIG.
A / A converter 28, a feedforward compensator 29, a switch 34 and an analog adder 33).

[0011]

A second clock signal correction circuit of the present invention is
A phase comparator (e.g., a phase comparator 31 in FIG. 6), a loop filter for filtering the output of the phase comparator (e.g., a loop filter 32 of FIG. 6), the output of the loop <br/> filter A voltage controlled oscillator (for example, the voltage controlled oscillator 35 of FIG. 6) that outputs a clock signal of a corresponding phase or frequency, and the phase comparator feeds back the clock signal read from the disk and the voltage controlled oscillator. PLL that outputs the phase difference from the clock signal
In the circuit, an eccentricity storage means for storing the eccentricity of the disk (for example, the eccentricity storage section 26 in FIG. 6) and a signal for reading the eccentricity stored in the storage means from the disk.
Correcting means for performing processing for converting to the position of the head , adding to the output of the phase comparator in synchronism with the rotation of the disk and supplying it to the loop filter (for example, the eccentric feedforward filter 32 and the analog adder 33A in FIG. 6). ) And are provided.

A third clock signal correction circuit of the present invention is
Voltage controlled oscillator (eg, voltage controlled oscillator 35 of FIG. 4)
And measuring means for measuring the amount of eccentricity for each of the plurality of disk surfaces (for example, the amount of eccentricity measuring unit 251 in FIG. 4).
And storage means for storing a signal corresponding to the eccentricity amount for each disk surface (for example, the storage unit 26A in FIG. 4), and storage means for storing a signal corresponding to the eccentricity amount of the disk surface to be accessed among the plurality of disk surfaces. Selecting means (for example, the selecting unit 27A in FIG. 4) for selectively reading from the voltage control oscillator and the phase or frequency of the clock signal output from the voltage controlled oscillator based on the signal corresponding to the eccentricity amount read by the selecting means. It is characterized by comprising a correcting means for changing (for example, the D / A converter 28, the switch 34 and the analog adder 33 in FIG. 4).

A fourth clock signal correction circuit of the present invention is
Voltage controlled oscillator (eg, voltage controlled oscillator 35 of FIG. 4)
A sine wave generating means for generating a sine wave (for example, a storage section 26A for storing the sine wave function generated by the calculating section 252 in FIG. 4), and a voltage controlled oscillator according to the signal generated by the sine wave generating means. And a correction means for changing the phase or frequency of the clock signal output from.

A fifth clock signal correction circuit of the present invention is
A voltage-controlled oscillator (for example, a voltage-controlled oscillator included in the PLL circuit 30 of FIG. 10), a storage unit (for example, an eccentricity storage unit 26B of FIG. 10) that stores a signal corresponding to the eccentricity of the disk, and this storage. Adjusting the signal corresponding to the amount of eccentricity stored in the means according to the track number of the disk, and changing the phase or frequency of the clock signal output from the voltage controlled oscillator according to the signal corresponding to the changed amount of eccentricity. Means (for example, the adjusting unit 5 in FIG. 10)
3) and are provided.

In the fifth clock signal correction circuit, the storage means stores the displacement of the predetermined data track of the disk from the ideal trajectory circle based on the amount of eccentricity, and the adjustment means stores the displacement. It is preferable that the displacement read out from is changed according to the track number.

In the fifth clock signal correction circuit, the adjusting means corresponds to the track number,
Phase difference generating means for generating a phase difference between the home index of the disk rotation axis and the home index on the data track of the disk (for example, the phase difference table 53 in FIG. 10).
P), a reading means for reading the displacement from the storage means in accordance with the phase difference generated by the phase difference generating means (for example, the memory access section 53A in FIG. 10), and the reading means for reading the displacement from the storage means. Multiplying means for multiplying the displacement by a multiplication coefficient corresponding to the track number (for example, FIG. 10).
It is preferable to include a multiplication coefficient table 53K and a multiplier 53M).

The sixth clock signal correction circuit of the present invention is
A voltage-controlled oscillator (for example, the voltage-controlled oscillator of the PLL circuit 30 in FIG. 11) and storage means for storing a signal corresponding to the eccentricity amount of the disk (for example, the eccentricity amount storage unit 26 in FIG. 11).
C) and the signal corresponding to the amount of eccentricity stored in the storage means are changed in accordance with the position of the head for reading the signal from the disk, and are output from the voltage controlled oscillator according to the signal corresponding to the changed amount of eccentricity. An adjusting unit (for example, the adjusting unit 63 in FIG. 11) that changes the phase or frequency of the clock signal is provided.

In the sixth clock signal correction circuit, the storage means stores the displacement of the predetermined data track of the disk from the ideal trajectory circle based on the amount of eccentricity, and the adjustment means reads it from the storage means. It is preferable to change the generated displacement according to the position of the head.

In the sixth clock signal correction circuit, the adjusting means generates a phase difference between the home index of the disk rotation axis and the home index on the data track of the disk corresponding to the position of the head. Generating means (for example, the phase difference table 63 in FIG. 11)
P) and the reading means for reading the displacement corresponding to the phase difference generated by the phase difference generating means from the storage means (for example, FIG. 11).
Memory access unit 63A) and a multiplication means for multiplying the displacement read from the storage means by the reading means by a multiplication coefficient corresponding to the position of the head (for example, FIG. 11).
Of the multiplication coefficient table 63K and the multiplier 63M).

[0021]

[0022]

In the first clock signal correction circuit of the present invention, the clock signal read from the disk and the voltage control
Position with the clock signal fed back from the oscillator
The phase difference is output and the measured disk eccentricity is converted to speed.
Calculation is performed, and the speed corresponds to the eccentricity of the disc.
Stored as a signal , added to the output of the loop filter in synchronization with the rotation of the disk, and supplied to the voltage controlled oscillator. Therefore, the clock signal can be made to accurately follow the eccentricity of the disk, and the eccentricity or displacement
Analog feedforward for speed conversion
Low cost because compensator (filter) can be eliminated
You can

[0023]

In the second clock signal correction circuit of the present invention, the clock signal read from the disk and the signal
The clock signal fed back from the pressure controlled oscillator
Of the phase difference is output, the stored eccentricity from the disk
The process of converting the position of the head to read the signal is performed,
It is added to the output of the phase comparator in synchronization with the rotation of the disk and supplied to the loop filter. Therefore, the clock signal can accurately follow the eccentricity of the disk.

In the third clock signal correction circuit of the present invention, the amount of eccentricity for each of the plurality of disk surfaces is measured, and the signal corresponding to the amount of eccentricity is stored in the storage means for each disk surface. The phase of the clock signal output from the voltage controlled oscillator on the basis of the signal corresponding to the read eccentricity, the signal corresponding to the eccentricity of the disk surface to be accessed among the surfaces being selectively read out from the storage means. Or the frequency is changed. Therefore, when the surface of the disk to be processed is switched, the eccentricity of the disk after switching can be immediately followed.

In the fourth clock signal correction circuit of the present invention, the phase or frequency of the clock signal output from the voltage controlled oscillator is changed according to the signal generated by the sine wave generating means. The eccentricity of the disk can be approximated by a sine wave function. Therefore, the clock signal can accurately follow the eccentricity of the disk without actually measuring the eccentricity of the disk.

In the fifth clock signal correction circuit of the present invention, the signal corresponding to the amount of eccentricity stored in the storage means is changed according to the track number of the disk, and corresponds to the changed amount of eccentricity. The phase or frequency of the clock signal output from the voltage controlled oscillator is changed according to the signal. Therefore, the clock signal can be made to accurately follow the eccentricity of the disk.

In the sixth clock signal correction circuit of the present invention, the signal corresponding to the stored eccentricity amount is changed according to the position of the head that reads the signal from the disk, and corresponds to the changed eccentricity amount. The phase or frequency of the clock signal output from the voltage controlled oscillator is changed according to the signal. Therefore, the clock signal can be made to accurately follow the eccentricity of the disk.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the configuration of an embodiment in which the present invention is applied to a magnetic hard disk device. The double-sided magnetic disks 1A, 1B, 1C and 1D are rotationally driven by a spindle motor 2. Magnetic heads 3A, 3
B, 3C and 3D are respectively arms 4A, 4B,
4C and 4D, and is rotated about a rotation center 5C by a voice coil motor (VCM) 5 to follow the tracks 502 on the upper surfaces of the double-sided magnetic disks 1A, 1B, 1C and 1D, and to these tracks. On the other hand, data writing and reading are performed. The tracks 502 of the four magnetic disks 1A, 1B, 1C and 1D form a cylinder 100. Although not shown, four magnetic heads for writing and reading data to and from the lower surfaces of the double-sided disks 1A, 1B, 1C and 1D are provided, and the magnetic heads 3A, 3B,
Similar to 3C and 3D, it is supported by arms 4A, 4B, 4C and 4D and is pivoted by VCM 5 to the center of rotation 5.
Rotated with respect to C. Magnetic disks 1A, 1B,
In the data tracks on the surface of 1C and 1D, a plurality of clock marks that give a time standard are embedded in advance at the time of disk manufacturing. Reference numeral 6 indicates the center of rotation of the spindle motor 6, that is, the magnetic disk 1A,
The rotation centers of 1B, 1C and 1D are shown.

The host computer 50 supplies commands such as a write command and a read command to the controller 70 via the interface cable 60.
The controller 70 outputs a control signal for controlling the magnetic hard disk device to the signal processing circuit 20.

The reproduction signals read from the disks 1A, 1B, 1C and 1D by the heads 3A, 3B, 3C and 3D are amplified by the reproduction amplifier circuit 21 to have a predetermined amplitude. The output of the reproduction / amplification circuit 21 is distributed to a clock extraction circuit 22, a track position error detection circuit 23, and a home index (one pulse for one rotation) extraction circuit 24. The reproduced clock signal extracted by the clock extraction circuit 22 is supplied to the track eccentricity amount measuring unit 25.
The track position error signal output from the track position error detection circuit 23 is also supplied to the track eccentricity amount measuring unit 25. Further, the home index signal extracted by the home index extracting circuit 24, that is, the rotation phase origin signal is also supplied to the track eccentricity amount measuring unit 25.

The track eccentricity measuring unit 24 measures the eccentricity of the data track circle 502 with respect to the rotation center axis 6 by a known method described later or by the method according to the present invention, and determines the home index generation position of the disk as an angular coordinate value of 0 degree. Is measured as a function of the angular position θ on the disk and is stored in the eccentricity amount storage unit 26 in a table format. This eccentricity amount is used by the tracking servo circuit 40 to control the VCM 5.

One of the features of the embodiment of the present invention shown in FIG. 1 is that the eccentricity amount stored in the storage unit 26 is read by the read circuit 27 in synchronization with the rotation of the disk, and is read by the D / A converter 28. After being converted into an analog signal and subjected to a compensating operation, that is, conversion into a speed signal by the feedforward compensator 29, a feedforward is additionally applied as a control voltage of the voltage controlled oscillator (VCO) 35 of the PLL circuit 30. is there.

The PLL circuit 30 includes a phase comparator 31, a loop filter 32 for performing a predetermined filtering process such as low-pass filtering on the output of the phase comparator 31.
The phase comparator 31 includes a voltage control oscillator 35 that outputs a clock signal having a phase or frequency according to the output of the filter 32. The phase comparator 31 outputs the clock signal extracted by the clock extraction circuit 22 and the voltage control oscillator 35 from the voltage control oscillator 35 to N. It outputs the phase difference from the clock signal fed back via the divide-by-1 divider 36. The feature of the embodiment of the present invention in FIG. 1 is that an analog adder (operational amplifier) 33 is provided between a loop filter 32 and a VCO 35, and a signal supplied from a feedforward compensator 29 via a switch 34 is looped. The point is that the signal is added to the signal output from the filter 32 and is supplied to the VCO 35. The loop filter 32 and the adder 33 may be digital arithmetic elements.

Because of this structure, the VCO
Reference numeral 35 denotes not only the output from the phase comparator 31 but also the eccentricity storage unit 26, the reading circuit 27, and the D / A converter 2.
8, feedforward compensator 29 and switch 34
It is also driven by the track circle eccentricity display voltage that arrives via. Therefore, the VCO 35 follows the pulse signal of 840 pieces / revolution generated from the disk by the so-called closed loop operation, and also performs the open loop operation by the prediction signal of the current instantaneous eccentricity amount from the storage unit 26.

That is, in the operation of such an eccentric disc, the clock from the disc observed when viewed from the reproducing head fixed in the θ direction has a coarse and fine fluctuation in the time axis direction. Of the fluctuation components, most of the components corresponding to the rotation frequency are intentionally “excited” by the open loop operation, so that the clock signal output from the clock extraction circuit 22 and the VCO 35. The clock signal output from is approached to the in-phase vicinity of approximately ± 20 ns (nanosecond).

Due to the approach by the open loop operation, the closed loop operation only needs to cancel the high-frequency component (several times to several tens times the rotation frequency) having a small amplitude among the fluctuation components. Therefore, the trackability that is realized is finally determined by the clock extraction circuit 22.
The output signal of the VCO 35 with respect to the clock signal output from can be held in an extremely close oscillation phase of ± 1 ns or less.

In the present embodiment, the data track circle is formed by using a cutting machine having a feeding accuracy of about 0.01 micron as in the optical disk manufacturing apparatus, so that the circularity is sufficiently better than 1 micron. . However, when such a disc is attached to the rotation axis, the center of the disc, that is, the center of the data track circle is 1
A mounting error of about 0 to 50 microns occurs.

Several methods can be considered for measuring this deviation (eccentricity), but the first method uses the most direct method. That is, the read heads 3A, 3B, 3
After constraining C and 3D in both R and θ directions,
Rotate the disks 1A, 1B, 1C and 1D.
It is now assumed that the disc is mounted with a track width of 10.0 μmm and an eccentricity of 50 μmm. When viewed from the read head, it is observed that as the disk rotates, the tracks escape to the outer circumference side of about five tracks and then return to the inner circumference side of about five tracks. Therefore, the rough eccentricity can be known by counting the number of tracks crossing this track.

In this example, the observed amount is 5 × 10 μm / line =
The eccentricity is determined to be 50 ± 5 μm, assuming an uncertainty of 5 μm.

However, with this method, it is not possible to measure with a resolution better than one track, that is, 10 μm. Therefore, the follow-up characteristic of the VCO 35 cannot be said to be the best.

In the second method of measuring eccentricity, first, at the time of forming a disk, track numbers are given to all tracks from the inner circumference to the outer circumference, and marking is performed at a sufficient return frequency over one circumference of all tracks. deep. 8 in this embodiment
40 pieces / lap. Next, the track number reading means (not shown) and the tracking servo circuit 40 operate the provisional closed loop servo so as to follow only the same track number. In this way, the VCM 5 is caused to generate a drive current that temporarily follows the eccentricity of the disk. The value of the current supplied from the tracking servo circuit 40 to the VCM 5 is detected every moment by the current detector 40, and is stored in the eccentricity storage unit 26 as time series data corresponding to one rotation in digital format.

In the third eccentricity measuring method, both the first and second eccentricity measuring methods directly measure the eccentricity of the track viewed from the reproducing head, whereas the eccentricity is reproduced from one track. The eccentricity amount is obtained from the non-equidistant nature observed in the clock pulse train that is originally equidistant, and the eccentricity amount is stored in the storage unit 2.
It is stored in 6.

Next, a third eccentricity measuring method will be described with reference to FIG. In FIG. 2, reference numeral 500 indicates the center of the track 502, and reference numeral 501 indicates the center of rotation of the disc. The reproducing head 3 is supported by the arm 4 and positioned by the tracking servo circuit 40 so as to trace on the center of the track 502.

Now, let the radius of the track 502 be r0 (m),
When the eccentricity is δ (m) and the rotation speed is N (Hz), the average peripheral speed V0 of the track 502 is

V0 = 2πr0 × N (m / sec)

It is If the number of pulses included in the circular track 502 having a radius r0 is M (pieces / one rotation), the inter-pulse distance L0 is

L0 = 2πr0 / M

It is Time T0 required to pass this
Is

[0050]   T0 = L0 / V0 = (2πr0 / M) / (2πr0 × N) = 1 / (N × M)

Thus, for example, N = 60.0 Hz, M = 8
If 40, T0 = 19.841 (μsec).

On the other hand, the pulse period T2 of the portion where the radius is increased to r2 = r0 + δ due to the eccentricity is

[0053]   T2 = 2πr0 / M / (2πr2 × N) = r0 / r2 × (N × M)

It becomes Therefore, for example, r0 = 20m
m, r2 = 20.05 mm, T2 is T0 × 1.
It becomes 0025, which is a 0.25% change. This is a minute amount, but since it is an amount in the time domain, it can be measured relatively accurately.

That is, in this example, T0 = 19.84.
1 (μs), T2 = 19.891, T1 = 19.
Since it is 792 (μs), there is a difference of about 50 ns (nanosecond) between the average value of T and the maximum value and the minimum value. Since this can be measured with sufficient accuracy using current electronic circuit technology, the measurement of the eccentricity results in the measurement of the time interval.

In an actual measurement operation, the following method is adopted because it is difficult to create the above-mentioned constant velocity time standard.

That is, instead of the constant velocity time standard, the switch 34 of FIG. 1 is opened and the PLL circuit 30 is operated only in the closed loop.
Is used as a time standard, and the phase of the reproduced clock from the clock extraction circuit 22 is measured over one round with reference to this. At this time, 840 pieces of time data are observed as shown in FIG. Since the time standard used at this time is the output of the PLL circuit 30 that follows the closed loop, the time standard itself also follows the eccentricity with the loop gain, and therefore the observation result has already suppressed the eccentricity to some extent. Therefore, the phase shift due to eccentricity with respect to the true time axis is obtained by multiplying the observation result by the loop gain (usually a constant of 100 or less). In this example, since the observed amount is ± 18 ns and the loop gain at 60 Hz is 40 times, one point on the disk with respect to the constant velocity time axis has a lead / lag of ± 720 ns.

The eccentricity table is completed by storing the advance / delay observed over one rotation in this way in the storage unit 26 as a digital numerical value.

Feedforward control of the VCO 35 according to the present invention using the eccentricity table stored in the storage unit 26 in this manner is performed as follows. First, the storage circuit 2 is synchronized with the rotation phase of the disk by the read circuit 27.
The contents of 6 are read out, converted into an analog voltage by the D / A converter 28, and then phase-compensated via a feedforward compensator 29 composed of a coil L, a capacitor C and a resistor R, and then a switch 33 and an analog addition. It is applied to the VCO 35 via the device 33. This gives V
The oscillation phase of the CO 35 approaches 0 ° over the entire range of one rotation, as indicated by the broken line in FIG.

FIG. 4 shows a second embodiment of the clock signal correction circuit of the present invention. In the embodiment of FIG. 1, the displacement (eccentricity) of the track itself with respect to each rotational position of the disk is used as the storage content of the storage unit 26, but in the embodiment of FIG. 4, the displacement of the track itself is stored in the temporary storage unit 251. Then, the amount equivalent to the feedforward compensator 29 of FIG. 1 is stored in the storage unit 26A in advance, and then stored in the storage unit 26A. Therefore, the amount stored in the storage unit 251 has a speed corresponding to the eccentricity.

In this way, there is an advantage that the feedforward compensator 29 of FIG. 1 can be omitted. That is, the compensator 29, that is, the filter shown in FIG. 1 needs to be composed of high-speed elements for real-time operation. However, since the eccentricity measurement is performed once a day, as in the embodiment shown in FIG. If a calculation equivalent to that of the compensator 29 of the embodiment is performed in advance, there is an advantage that an inexpensive general-purpose processor can be used. Furthermore, there is an advantage that an operation that is difficult with analog processing can be realized.

In the embodiment of FIG. 4, the storage content selection unit 2
7A selectively extracts amounts (that is, speeds) corresponding to the eccentric amounts of the plurality of disk surfaces stored in the storage unit 26A based on a command from the controller 70.

Since the embodiment of FIG. 4 has the above-mentioned configuration, the eccentricity measurement result obtained in the same manner as the embodiment of FIG. 1 is adjusted to the required amplitude / phase characteristic by the calculation unit 252. , Are stored in the storage unit 26A. This eccentricity measurement operation is independently repeated for each surface of the plurality of disks at an appropriate time after the power switch is turned on. Since there are eight surfaces on the disk, the heads provided corresponding to the respective surfaces are used to perform a total of eight times. Therefore, eight types of eccentricity amounts are stored in the storage unit 26A.

Here, a case where the controller 70 selects, for example, the disk 1B (see FIG. 1) will be described. At this time, the selection unit 27A outputs the eccentricity data detected by the head 3B from the information stored in the storage unit 26A in synchronization with the rotation of the disk 1B. In the output eccentricity data, for example, as shown in FIG. 5, the memory address corresponds to the angular position coordinate on the disk, and the stored data corresponds to the eccentricity amount at this coordinate with phase compensation.

Therefore, after converting this into an analog voltage by the D / A converter 28, the VCO is supplied via the adder 33.
When applied to the VCO 35, the VCO 35 accurately cancels the advance or delay of the clock due to the eccentricity of the disk,
The output of 35 can generate pulses with a phase very close to the clock reproduced from the disc.

In the embodiment of FIG. 4, the calculation result for the eccentricity amount of the calculation unit 252 is stored in the storage unit 26A and the calculation result corresponding to the disk surface to be processed is read out. It may be stored and the eccentricity amount corresponding to the disk surface to be processed may be read out.

In each of the above embodiments, the amount of eccentricity was measured and found, but this amount is generally as shown in FIG.
It corresponds to the initial phase of the sine wave function shifted. Therefore, for example, the calculation unit 252 of FIG.
Then, a sine function is generated and stored in the storage unit 26A.

In this method, it is necessary to determine two parameters, the phase and the amplitude of the sine wave. Below, an example of this method is shown. First, the calculation unit 252 stores a temporary data set corresponding to an initial phase of 0 ° and an amplitude of 10 tracks in the storage unit 26A. Next, based on this, provisional feedforward servo is performed using the tracking servo circuit 40. Further, the track position error detection circuit 2
Count the truck traverse (crossing due to eccentricity) at 3,
The current eccentricity amount is known by the calculation unit 252. Finally, the previous track traverse count stored in the temporary storage unit 251 is compared with the current traverse count to determine whether or not there is an improvement.

Based on this determination result, the initial phase and amplitude are determined for the second trial. This series of operations is N
The contents of the storage unit 26A are fixed when the track traverse reaches a predetermined value, for example, 0 (zero).

In this way, the eccentricity measuring unit 25 only needs to take the number of track crossings due to eccentricity as a coefficient and does not need to measure the absolute amount thereof.

FIG. 6 shows a third example of the clock correction circuit of the present invention.
An example of is shown. 6, the magnetic disk 1 corresponds to one of the four magnetic disks 1A, 1B, 1C and 1D of FIG. 1, the spindle motor 2 corresponds to the spindle motor 2 of FIG. 1, and the magnetic head 3 corresponds to 1 corresponds to one of the magnetic heads 3A, 3B, 3C and 3D shown in FIG. 1, and the arm 4 includes four arms 4A, 4B, 4C and 4D shown in FIG.
VCM 5, clock extraction circuit 22, home index extraction circuit 24, eccentricity amount measuring unit 25, eccentricity amount storage unit 26, phase comparator 31, loop filter 3
2, VCO 35 and frequency divider 36 are the same as in FIG.

Eccentric feedforward filter 29A
Converts the eccentricity amount read from the eccentricity amount storage unit 26 into a feedforward compensation amount, that is, a position signal, and supplies it to one input terminal of the analog adder 33A. The adder 33A includes a signal from the filter 29A and a phase comparator 31.
The signal from is added and supplied to the loop filter 32.

In the embodiment of FIG. 6, the eccentricity amount is stored, the eccentricity amount is read out and converted into the feedforward compensation amount by the filter 29A. However, the eccentricity amount is converted into the feedforward compensation amount in advance. You may make it memorize | store a digital value.

According to the embodiments of the invention described above,
It becomes possible to reproduce a clock signal that is very accurately synchronized with the clock mark engraved on the disk, and if this clock is used for detecting the track position error signal and demodulating the data code, it is possible to obtain extremely good results. You can Further, the gain in the eccentric frequency range can be increased without widening the band of the black reproduction loop.

FIG. 7 shows a fourth example of the clock correction circuit of the present invention.
An example of is shown. This embodiment is suitable when a very precise phase lock is not needed and omits the phase control loop. The eccentricity amount measured by the measuring unit 25 is the eccentric feedforward filter 29.
It is converted into a feedforward compensation amount by A (in this case, a digital filter) and stored in the eccentricity amount storage unit 26B. The eccentricity amount stored in the storage unit 26B is read according to the home index signal output from the home index extraction circuit 24 and supplied to the VCO 35. The VCO 35 changes the phase or frequency of the output clock signal according to the supplied amount of eccentricity.

In the first to fourth embodiments, the phase fluctuation of the reproduced clock signal due to the offset between the spindle rotation center and the data track circle center is corrected by using the displacement of the specific track from the ideal track. is there. Therefore, there are the following problems in generating a highly accurate clock signal.

(1) When a disk on which data tracks are formed in advance is chucked on a spindle, the head running track radial position fluctuation (spindle) of the reproduced clock signal caused by the offset between the data track circle center and the spindle rotation axis center The amount of frequency fluctuation with respect to the fluctuation of the distance from the center of rotation to the track on which the head is located) increases in the inner circumferential direction of the disk.

(2) For a disk in which clock marks are arranged along the rotation locus of the signal read head supported by the rotation arm, the home index of the spindle rotation axis and the home index on the data track circle of the disk. Since the phase difference between the head running track radius and the track number is different for each track number, that is, a phase error occurs in the eccentricity correction signal according to the change in the head running track radius.

In order to solve such a problem, in the fifth and sixth embodiments of the present invention described below, the external control voltage applied by the PLL circuit 30, that is, VCO3.
The input voltage to 5 is changed according to the track number or the head traveling track radial position. This makes it possible to adjust the amplitude and phase of the clock correction amount that changes between the inner circumference and the outer circumference of the specific track of the disk, and thus it is possible to configure a PLL system that performs extremely accurate tracking.

FIG. 8 shows changes in the same track running radius of the signal read head due to the eccentricity between the data track center and the spindle rotation center and the clock marks recorded at equal intervals on the circular data track of the disk. . In the figure, reference numeral 500 is the center of a circular data track, and data tracks D3, D4, D5, D6 and D7 are formed concentrically with respect to the center 500.
N (N is a positive integer) clock marks CM are physically recorded at equal intervals on each data track.

When an eccentricity 511 occurs when a disk having circular data tracks as described above is chucked by the spindle motor rotating shaft 501, the signal read head running on the same track causes the disk rotating shaft center 51.
As shown in FIG. 8, the running radius from 1 is r _min , r ₀ ,
It changes with r _max .

Here, the eccentric distance 511 between the data track center 500 and the spindle motor rotating shaft 501 is d, and the radial distance 512 from the track center of the circular data track is 512.
R, data track center 500 and head traveling position HP
The angle formed by the line connecting to and the line connecting the data track center 500 and the spindle rotation center 501 is θ, and the spindle rotation angular velocity is ω. At this time, the distance R (θ) from the spindle rotation center 511 to the head traveling position HP
Is

R (θ) = (r ² + d ² −2rd · cos (θ)) ^1/2 (Equation 1)

The angle θ is (r
Is much larger than d),

[0085]   θ = π−ωt (Equation 2)

It can be expressed as By substituting (Equation 2) into (Equation 1), the track traveling speed of the head is changed to v (t).
Can be expressed by the following (formula 3).

V (t) = (r ² + d ² + 2rd · cos (ωt)) ^1/2 . ω ... (Formula 3)

Since the distance between the clock marks CM is r · 2π / N at equal intervals on the same track, the passing time between the clock marks when the distance from the spindle rotation center 501 to the data track is the longest is t1. , If the clock transit time at the time of the closest approach is t2,

T1-t2 = 2πr / (ωN) · 2d / (r ² −d ² ) (Equation 4)

Is satisfied. (Equation 4) is simplified as follows using the condition (r is much larger than d).

[0091]   t1-t2 = 2π / (ωN) · 2d / r (Equation 5)

In (Equation 5), the number N of clock marks on the circular data track and the spindle rotation angular velocity ω are values obtained as design values in advance. Therefore, as is apparent from (Equation 5), the amplitude of the time interval of the clock mark reproduction signal changes with the eccentric distance d and also with the head traveling track radius r.

Therefore, the eccentricity distance d is measured and held, and the value of the part of 2π / (ωN) · 2 / r when r changes is held in a table format as a multiplication coefficient. By multiplying by the multiplication coefficient, the amplitude of the time interval of the clock mark reproduction signal at an arbitrary head traveling track radius r can be obtained.

FIG. 9 shows the locus of the radius of the head mounting arm of the signal reading head, and the clock mark and the home index mark arranged on this locus. In the figure, reference numeral 500 is the center of the circular data track, and the data tracks D3 are concentrically arranged with respect to the center 500.
D4, D5, D6 and D7 are formed, N clock marks CM are physically recorded at equal intervals on each data track, and one home index mark HI is recorded for each circumference. Has been done. Further, the clock mark CM and the home index mark HI are arranged on the turning radius locus 517 of the head mounting arm extending in the disk radial direction.

Here, the head mounting arm turning radius distance 515 is A, and the track on which the signal read head is located from the track center 500 (in FIG. 9, the track center 500 and the spindle rotation axis are aligned). In the example of FIG. 9, the disk rotation radius distance 512 to the data track D5), that is, the head traveling track radius is r, the phase difference angle between the home index position of the spindle rotation axis and the home index mark recorded on the disk data track. Is δ, δ is

[0096]   δ = sin-1 (r / (2A)) (Equation 6)

It is represented by As is clear from (Equation 6),
The phase difference angle δ changes with a change in the disk rotation radius position of the head, that is, the head traveling track number r. Therefore, if the phase difference angle δ for various values of r is calculated in advance and stored in a table format, the phase fluctuation of the home index mark reproduction signal can be obtained by inputting r of the track being reproduced. be able to.

FIG. 10 shows the configuration of the fifth embodiment of the clock signal correction circuit of the present invention. In the figure, reference numeral 1 denotes a disk in which N clock marks are recorded at equal intervals on each circular data track, and the disk 1 is chucked by a spindle shaft 2. The recording / reproducing head 3 is attached to the rotatable arm 4 and moves on the disk 1 to record / reproduce signals. The signal read from the disk 1 by the head 3 is amplified by the reproducing / amplifying circuit 21 and converted into a TTL level pulse signal PS by the A / D converting circuit 21A.

The pulse signal PS is supplied to the clock extraction circuit 22.
A, home index extraction circuit 24A and track number extraction circuit 51. Clock extraction circuit 22
A is a clock mark reproduction signal CM from the pulse signal PS
S is extracted, and the eccentricity amount measuring unit 25C and the PLL circuit 30 are extracted.
Supply to. The home index extraction circuit 24A extracts the home index reproduction signal HIS from the pulse signal PS and supplies it to the eccentricity measurement unit 25C and the memory access unit 53A of the adjustment unit 53. Track number extraction circuit 5
1 is the head traveling track number TN from the pulse signal PS
Is extracted and supplied to the eccentricity amount measuring unit 25C and the phase difference table 53P and the multiplication coefficient table 53K of the adjusting unit 53.

The eccentricity measuring unit 25C uses the clock mark reproduction signal CMS, the home index reproduction signal HI and the head traveling track number TN to calculate the eccentricity information D over one round of the head traveling track based on (Equation 5).
I is calculated and output to the eccentricity amount storage unit 26C. The memory access unit 53A of the adjustment unit 53 outputs the control signal and the address signal to the eccentricity amount storage unit 26C based on the home index reproduction signal HIS. The eccentricity amount storage unit 26C stores the eccentricity amount DI output from the eccentricity amount measurement unit 25C over one round of the head traveling track according to the control signal and the access signal from the memory access unit 53A. The stored eccentricity information indicates the displacement from the ideal trajectory circle of the data track circle.

The phase difference table 53P of the adjusting unit 53 stores the phase difference angle δ between the home index position of the spindle rotation axis and the home index mark recorded on the disk data track, using the head traveling track number as an input parameter. ing. The head traveling track number corresponds to the disk rotation radius distance of the head in FIG. 9, that is, the head traveling track radius r. Therefore, as is clear from (Equation 6), the phase difference angle δ changes as the traveling track number changes. The phase difference table 53P is a table in which phase difference angles δ for various track number values are calculated in advance and stored in a table format. The phase variation of the index mark reproduction signal is output as the phase difference angle δ.

The multiplication coefficient table 53K stores the value of the 2π / (ωN) · 2 / r portion of (Equation 5) when the head traveling track radius r corresponding to the track number changes as a multiplication coefficient in a table format. is doing.

When the head traveling track number TN is output from the track number extraction circuit 51, the phase difference table 53 is output.
P outputs the phase difference δ corresponding to the track number TN. The memory access unit 53A outputs the control signal and the address signal corresponding to the phase difference δ output from the table 53P to the eccentricity amount storage unit 26C, and the eccentricity amount storage unit 25C adjusts the eccentricity amount DI accordingly. 53 is supplied to one input of the multiplier 53M. On the other hand, the multiplication coefficient table 53K supplies the multiplication coefficient corresponding to the head traveling track number TN supplied from the track number extraction circuit 51 to the other input terminal of the multiplier 53M. Multiplier 53
M multiplies the input eccentricity DI by a multiplication coefficient. That is, the multiplier 53M changes the displacement, that is, the amount of eccentricity read from the storage unit 26C, according to the head traveling track number, and outputs it.

The eccentricity amount thus changed or adjusted is converted into an analog external control voltage by the D / A conversion circuit 28 and applied to the PLL circuit 30 as a feedforward compensation amount. The PLL circuit 30 receives the clock mark reproduction signal CM according to the input external control voltage.
The phase or frequency of S is changed. Therefore, in the embodiment of FIG. 10, the clock signal can follow the eccentricity of the disk 1 with high accuracy.

FIG. 11 shows the configuration of the sixth embodiment of the clock signal correction circuit of the present invention. 11 embodiment and FIG.
11 is different from the embodiment shown in FIG. 11 in that an angle sensor 61 and a head traveling radius position detection circuit 62 are provided instead of the track number detection circuit 51, and an eccentricity amount measuring unit 25C and an eccentricity amount storage unit are provided. 26C is provided with an eccentricity measuring section 25D and an eccentricity storage section 26D, and instead of the adjusting section 53 including the memory access section 53A, the multiplication section 53M, the phase difference table 53P and the multiplication coefficient table 53K, a memory access section. 63A, multiplication unit 6
3M, phase difference table 63P and multiplication coefficient table 6
The point is that an adjusting unit 63 including 3K is provided.

The angle sensor 61 is attached to the rotation shaft of the arm 4 and detects the rotation angle of the arm 4. The head traveling radius position detection circuit 62 obtains a head traveling track radius r (see FIG. 9) based on the rotation angle of the arm 4 detected by the sensor 61, and outputs the head traveling radius position signal HRP as an eccentricity measuring unit. 25D, the phase amount table 63P, and the multiplication coefficient 63K.

The eccentricity amount measuring unit 25D uses the clock mark reproduction signal CMS, the home index reproduction signal HI, and the head traveling radius position signal HRP to represent the head traveling track radius r, and based on (Equation 5), the head traveling is calculated. The eccentricity information DI is calculated over the entire circumference of the track and is output to the eccentricity amount storage unit 26D. The memory access unit 63A of the adjustment unit 63 outputs the control signal and the address signal to the eccentricity storage unit 26D based on the home index reproduction signal HIS. The eccentricity amount storage unit 26D stores the eccentricity amount DI output from the eccentricity amount measurement unit 25D over one round of the head traveling track according to the control signal and the access signal from the memory access unit 63A. The stored eccentricity information indicates the displacement from the ideal trajectory circle of the data track circle.

The phase difference table 63P of the adjusting unit 63 uses the phase difference angle δ between the home index position of the spindle rotation axis and the home index mark recorded on the disk data track, with the head traveling track radius r as an input parameter. I remember. As is clear from (Equation 6), the phase difference angle δ changes as the head traveling track radius r changes. The phase difference table 63P is a table in which the phase difference angles δ for various values of the radius r are calculated in advance and stored in a table format. , The phase variation of the home index mark reproduction signal is output as the phase difference angle δ.

The multiplication coefficient table 63K stores the value of 2π / (ωN) / 2 / r in (Equation 5) when the radius r changes as a multiplication coefficient in a table format.

When the head traveling radial position signal HRP is output from the head traveling radial position detecting circuit 62, the phase difference table 63P outputs a phase difference δ corresponding to the radius r indicated by the head traveling radial position signal HRP. The memory access unit 63A outputs a control signal and an address signal corresponding to the phase difference δ output from the table 63P to the eccentricity amount storage unit 26D, and the eccentricity amount storage unit 25D accordingly adjusts the eccentricity amount DI. It is supplied to one input of the multiplier 63M of 63. On the other hand, the multiplication coefficient table 63K supplies the head traveling radius position signal HRP supplied from the head traveling radius position detection circuit 62, that is, the multiplication coefficient corresponding to the radius r to the other input terminal of the multiplier 63M. Multiplier 63
M multiplies the input eccentricity DI by a multiplication coefficient. That is, the multiplier 63M changes the displacement, that is, the amount of eccentricity read from the storage unit 26D, according to the radius r and outputs it.

The eccentricity amount thus changed or adjusted is converted into an analog external control voltage by the D / A conversion circuit 28 and applied to the PLL circuit 30 as a feedforward compensation amount. The PLL circuit 30 receives the clock mark reproduction signal CM according to the input external control voltage.
The phase or frequency of S is changed. Therefore, in the embodiment of FIG. 11, the clock signal can follow the eccentricity of the disk 1 with high accuracy.

As is apparent from the above description, according to the embodiments of FIGS. 10 and 11, the reproduction clock signal caused by the offset between the center of the rotation axis and the center of the data track circle when the disk is chucked by the spindle. It is possible to optimize the correction of the frequency fluctuation amount with respect to the unit radius fluctuation of.

Further, according to the embodiments of FIGS. 10 and 11, the phase of the home index of the spindle rotation axis and the reproduction signal of the home index physically recorded on the data track circle of the disk is the track number, that is, the head. When the traveling track positions are different, the phase error due to the traveling radial position of the signal read head can be optimized.

Although the above embodiment relates to a magnetic disk device, the present invention is not limited to this, and can be applied to other disk devices such as an optical disk device.

[0115]

[0116]

According to the present invention a first clock signal correcting circuit according to the present invention, the phase comparator is read from the disc clock
Signal and the clock fed back from the voltage controlled oscillator.
Output the phase difference with the clock signal and measure the eccentricity of the disk.
And calculate the disk eccentricity to speed,
The recorded speed is recorded as a signal corresponding to the eccentricity of the disc.
Remember, I added it to the output of the loop filter in synchronization with the rotation of the disk and supplied it to the voltage controlled oscillator.
The clock signal can be made to accurately follow the eccentricity of the disk, and the amount of eccentricity or displacement can be converted into velocity.
Analog feedforward compensator (
Cost can be reduced because it is unnecessary.
It

[0117]

According to the second clock signal correction circuit of the present invention, the phase comparator detects the clock signal read from the disk.
And the clock fed back from the voltage controlled oscillator.
And it outputs a phase difference between the click signal, diss stored eccentricity
Process to convert the signal from the
On the other hand, since it is added to the output of the phase comparator and supplied to the loop filter in synchronization with the rotation of the disk, the clock signal can accurately follow the eccentricity of the disk.

According to the third clock signal correction circuit of the present invention, the eccentricity amount for each of the plurality of disk surfaces is measured, the signal corresponding to the eccentricity amount is stored in the storage means for each disk surface, and a plurality of signals are stored. A signal corresponding to the amount of eccentricity of the disk surface to be accessed of the disk surface is selectively read from the storage means, and the phase or frequency of the clock signal output from the voltage controlled oscillator is determined based on the read signal corresponding to the amount of eccentricity. since so as to change, when switching the processing target disk surface, can follow immediately the eccentricity of the after switching disk.

According to the fourth clock signal correction circuit of the present invention, the phase or frequency of the clock signal output from the voltage controlled oscillator is changed according to the signal generated by the sine wave generating means. The clock signal can accurately follow the eccentricity of the disk even if the eccentricity of the disk is not measured.

According to the fifth clock signal correction circuit of the present invention, the signal corresponding to the eccentricity amount stored in the storage means is
Since the phase or frequency of the clock signal output from the voltage controlled oscillator is changed according to the signal corresponding to the changed eccentricity, it is possible to change the clock signal more accurately according to the eccentricity of the disk. Can be followed.

According to the sixth clock signal correction circuit of the present invention, the signal corresponding to the stored eccentricity amount is changed in accordance with the position of the head for reading the signal from the disk, and the changed eccentricity amount is dealt with. Since the phase or frequency of the clock signal output from the voltage controlled oscillator is changed according to the signal, the clock signal can be more accurately made to follow the eccentricity of the disk.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock signal correction circuit according to the present invention.

FIG. 2 is an explanatory diagram showing an example of a deviation between a center of a track of a disc and a center of rotation of the disc, that is, an eccentricity of the disc.

FIG. 3 is a graph showing the phase of the clock signal extracted from the disk and the phase of the clock signal output from the VCO 35 of the PLL loop 30 in comparison.

FIG. 4 is a block diagram showing a second embodiment of the clock signal correction circuit of the present invention.

FIG. 5 is an explanatory diagram showing storage contents of a storage unit 26A of the embodiment shown in FIG.

FIG. 6 is a block diagram showing a third embodiment of the clock signal correction circuit of the present invention.

FIG. 7 is a block diagram showing a fourth embodiment of the clock signal correction circuit of the present invention.

FIG. 8 shows clock marks physically stored at equal intervals in a circumferential direction of a circular data track on a disk and a running radius of a signal read head running on the same track of an eccentrically chucked disk. It is a figure which shows the relationship with the change of.

FIG. 9 is a diagram showing a relationship between clock marks and home index signals stored physically at equal intervals in a circumferential direction of a circular data track on a disk, and a head mounting arm rotation radius locus of a signal read head. .

FIG. 10 is a block diagram showing a fifth embodiment of the clock signal correction circuit of the present invention.

FIG. 11 is a block diagram showing a sixth embodiment of the clock signal correction circuit of the present invention.

FIG. 12 is a block diagram showing an example of a conventional clock generation circuit.

[Explanation of symbols]

1, 1A, 1B, 1C, 1D magnetic disk, 2 spindle motor 3, 3A, 3B, 3C, 3D magnetic head 4,4A, 4B, 4D, 4D arm 5 VCM 6 Disc rotation center axis 20 Signal processing circuit 21 Regenerative amplifier circuit 22,22A clock extraction circuit 23 Track position error detection circuit 24, 24A Home index extraction circuit 25, 25B, 25C, 25D Eccentricity measurement unit 26, 26B, 26C, 25D Eccentricity storage unit 27 Read circuit 27A selection section 28 D / A converter 29 Feedforward compensator 29A Eccentric feedforward filter 30 PLL circuit 31 Phase comparator 32 loop filter 33 analog adder 34 switch 35 VCO 36 frequency divider 40 Tracking servo circuit 45 Current detector 50 host computer 53, 63 adjustment unit 53A, 63A memory access unit 53K, 63K multiplication coefficient table 53M, 63M multiplier 53P, 63P phase difference table 60 interface cable 70 Disk controller 100 cylinders 500 track center 501 disk rotation center 502 truck

Front page continued (72) Hideaki Ishioka Inventor Hideaki Ishioka 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) Reference JP-A-63-18579 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 20/10

Claims (10)

(57) [Claims] 1. A phase comparator, a loop filter for performing a predetermined filtering process on the output of the phase comparator, pre
A voltage controlled oscillator for outputting a clock signal having a phase or frequency according to the output of the loop filter, wherein the phase comparator has a clock signal read from a disk and a clock signal fed back from the voltage controlled oscillator. the speed and the PLL circuit for outputting a phase difference, and eccentricity measuring means for measuring the amount of eccentricity of the disc, the eccentricity amount measured by the eccentricity measuring means and
Arithmetic means for performing an operation of converting an eccentric amount storage means for storing the rate computed by the computing means as a signal corresponding to the eccentricity of the disk, signals corresponding to the eccentricity stored in the storage means Is added to the output of the loop filter in synchronization with the rotation of the disk and is supplied to the voltage controlled oscillator. 2. A phase comparator, a loop filter for performing a predetermined filtering process on the output of the phase comparator, pre
A voltage controlled oscillator for outputting a clock signal having a phase or frequency according to the output of the loop filter, wherein the phase comparator has a clock signal read from a disk and a clock signal fed back from the voltage controlled oscillator. wherein either disk and PLL circuit for outputting a phase difference, an eccentric amount storage means for storing the eccentricity of the disk, said eccentricity stored in the storage means with the
And a correction means for performing a process of converting the signal to a position of a head for reading the signal , adding the signal to the output of the phase comparator in synchronization with the rotation of the disk, and supplying the output to the loop filter. Clock signal correction circuit. 3. A voltage controlled oscillator, eccentricity amount measuring means for measuring an eccentricity amount for each of a plurality of disk surfaces, storage means for storing a signal corresponding to the eccentricity amount for each disk surface, and the plurality of Selection means for selectively reading from the storage means a signal corresponding to the amount of eccentricity of the disk surface to be accessed, and the voltage controlled oscillator based on the signal corresponding to the amount of eccentricity read by the selection means. And a correction means for changing the phase or frequency of the clock signal output from the clock signal correction circuit. 4. A voltage controlled oscillator, sine wave generating means for generating a sine wave, and correction for changing the phase or frequency of a clock signal output from the voltage controlled oscillator according to the signal generated by the sine wave generating means. And a clock signal correction circuit. 5. A voltage-controlled oscillator, storage means for storing a signal corresponding to an eccentricity amount of a disk, and a signal corresponding to the eccentricity amount stored in the storage means is changed according to a track number of the disk. A clock signal correction circuit comprising: an adjusting unit that changes a phase or a frequency of a clock signal output from the voltage controlled oscillator according to the signal corresponding to the changed eccentricity amount. 6. The storage means is based on the eccentricity amount,
A displacement of a predetermined data track of the disk from an ideal locus circle is stored for one round, and the adjustment unit changes the displacement read from the storage unit according to the track number. Item 5. The clock signal correction circuit according to Item 5 . 7. The phase difference generating means for generating a phase difference between the home index of the disk rotation axis and the home index on the disk data track corresponding to the track number, the adjusting means generating the phase difference generating means from the phase difference generating means. Read-out means for reading the displacement from the storage means in accordance with the detected phase difference; and multiplying means for multiplying the displacement read by the read-out means from the storage means by a multiplication coefficient corresponding to the track number. The clock signal correction circuit according to claim 6 , further comprising: 8. A voltage controlled oscillator, storage means for storing a signal corresponding to an eccentricity amount of a disk, and a signal corresponding to the eccentricity amount stored in the storage means at a position of a head for reading a signal from the disk. A clock signal correction circuit comprising: an adjustment unit that changes the phase or frequency of a clock signal output from the voltage controlled oscillator according to a signal corresponding to the changed eccentricity amount. 9. The storage means is based on the amount of eccentricity,
A displacement of a predetermined data track of the disk from an ideal locus circle is stored for one round, and the adjustment unit changes the displacement read from the storage unit according to the position of the head. Item 8. A clock signal correction circuit according to Item 8 . 10. The phase difference generating means for generating a phase difference between the home index of the disk rotation axis and the home index on the data track of the disk, which corresponds to the position of the head, and the phase difference generating means. Reading means for reading the displacement from the storage means in accordance with the phase difference generated by the multiplying means for multiplying the displacement read by the reading means from the storage means by a multiplication coefficient corresponding to the head position. The clock signal correction circuit according to claim 9 , further comprising: