JP3373784B2 - Video camera equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera device for time-division processing a video signal taken in from an image pickup device by using a memory.

[0002]

2. Description of the Related Art A conventional digital signal processing video camera device will be described with reference to the block diagram of FIG. The one-dimensional analog video signal extracted from the solid-state image sensor 31 is input to the analog signal processing section 32, where the CDS
(Correlated double sampling circuit) removes noise,
The gain is adjusted by a GCA (gain control amplifier) and output to the A / D converter 33 at the next stage, where it is converted into a digital video signal. The digital video signal is input to the pre-processing unit 34. As the processing performed by the former processing unit 34, black (O
B: Optical black) clamp, fluorescent light flicker correction, lens shading correction, scratch (pixel defect) correction, color carrier amplification, high luminance color carrier (horizontal stripe) suppression, AES + AGC control, gamma correction (non-linear processing). The video signal processed by the pre-processing unit 34 is written in the frame memory 35.

The video signal read out from the frame memory 35 is multidimensionalized as a simultaneous video signal for two lines via a line memory (1H delay line) 36, and is sent to a luminance signal processing section 37 and a color signal processing section 38. Enter each. The luminance signal processing unit 37 performs horizontal and vertical contour correction,
The color signal processing unit 38 performs color separation, color correction, and generation of color difference signals. The color-processed color difference signals are input to the UV converter 39, where the signal band is lowered, and serial digital U and V signals are time-division output.

The timing generator 40 uses the continuous-wave clock signal CK to drive the solid-state image pickup device 31, write and read pulses to the frame memory 35, etc. from the solid-state image pickup device 31 to the luminance signal processing section 37 and the UV converter 39. Generates and supplies the clock pulse necessary for the processing of each block up to.

In the above-mentioned conventional video camera, driving of a solid-state image pickup device for reading out a video signal, analog signal processing for performing noise reduction (CDS) / gain adjustment (AGC) of the video signal, A / D conversion, digital video Signal preprocessing,
The 1 or 2H delay using the line memory and the luminance signal processing / color signal processing are all operated in parallel at the same time using the timing pulse generated from the timing generator 40. Therefore, it is impossible to reduce the peak power consumption and reduce the power consumption.

The video camera has a broadcasting system (P or P) of 25 or 30 frames (50 or 60 fields) / second.
Designed on the premise of images by AL / NTSC,
Y / C output at 25 or 30 frames even when only a few tens of frames / second are required
(Brightness / color) signal is thinned out before use.

The reason is that it is difficult to reduce the driving frequency itself of the solid-state image pickup device in view of the operation and characteristics of the device, and an automatic sensitivity adjustment (AES: electronic shutter iris) circuit or a fluorescent lamp flicker correction circuit is formed. In some cases, the system becomes complicated. In analog signal processing that performs noise reduction / gain adjustment of a video signal and A / D conversion, power consumption is almost determined by the signal band (frequency characteristic) that passes, so in a circuit designed on the premise of a broadcasting system, Simply sample and hold pulse or A / D
Even if the clock frequency for conversion is lowered, low power consumption cannot be realized.

[0008]

In the above-mentioned conventional video camera device, it is functionally impossible to stop a part of the processing in order to save power.

The present invention provides a video camera device which is capable of time-division processing with clock signals having different frequencies and temporarily stops a desired function to save power.

[0010]

In order to solve the above-mentioned problems, in the video camera device of the present invention, an analog signal is converted into an analog video signal which is optically taken in based on a first clock frequency, and Based on a second clock frequency, a pre-stage signal processing unit that converts the analog video signal into a digital video signal at a clock frequency and performs digital signal processing that requires minimum writing in a frame (or field) memory; A second-stage signal processing unit that reads out the digital video signal written in the memory and performs at least a luminance signal process and a chrominance signal process, the first-stage and second-stage signal processing units perform time-division operation, and By setting the clock frequencies of 2 to different values, the desired frame rate and peak power consumption can be obtained. Achieving a reduction.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, one embodiment of the present invention will be described in detail with reference to the circuit configuration diagram of FIG. 1. The same components as those of FIG. 3 are designated by the same reference numerals. explain.

In FIG. 1, the one-dimensional analog video signal taken out from the solid-state image pickup device 31 is inputted to the analog signal processing section 32. The analog signal processing unit 32 is a CDS
And GCA to remove noise and adjust gain. The output of the analog signal processing unit 32 is converted into a digital video signal via the A / D converter 33 and input to the pre-processing unit 34. The processing performed by the pre-processing unit 34 includes a black clamp,
Fluorescent light flicker correction, lens shading correction, scratch correction, color carrier amplification, high brightness color carrier suppression, AES
There are + AGC control and gamma correction. The pre-processed video signal is written in the frame memory 35.

The video signal read out from the frame memory 35 is multidimensionalized as a simultaneous video signal for two lines via a line memory (1H delay line) 36, and is sent to a luminance signal processing section 37 and a color signal processing section 38. Enter each. The luminance signal processing unit 37 performs horizontal and vertical contour correction,
The digital luminance signal Y is output from the output. The color signal processing unit 38 performs color separation, color correction, and generation of color difference signals. The color-processed color difference signals are input to the UV converter 39, where the signal band is lowered, and serial digital U and V signals are time-division output.

The timing generator 401 generates and supplies clock pulses required for signal processing in the preceding stage from the solid-state image pickup device 31 to the writing in the frame memory 35 based on the continuous wave clock signal CK1. Also,
The timing generator 402 generates and supplies a clock pulse required for signal processing of subsequent stages from the reading of the frame memory 35 to the luminance signal processing unit and the UV converter 39 based on the continuous wave clock signal CK2.

The operation of FIG. 1 will be described with reference to the timing chart of FIG. FIG. 2A shows one vertical period (one screen).
The video signal after A / D conversion, which is written in the frame memory 35, is shown, and (b) shows the video signal read from the frame memory 35 in one vertical period (one screen). Figure 2
(C) shows a clock pulse for driving the A / D converter 33, which is generated based on the continuous wave clock signal CK1, and (d) is generated based on the continuous wave clock signal CK2. Clock pulses for driving the luminance and color signal processing units 37 and 38 are shown.

In the example of FIG. 2, the clock frequency of (c) is set to be three times that of (d). That is, the frequency of the clock signal CK1 is 3 times that of the clock signal CK2.
It is set to double. Therefore, the read time is three times as long as the write time to the frame memory 35.

Therefore, the clock signal CK2 is stopped during the period in which the clock pulse of FIG.
If the clock signal CK1 is stopped during the period in which the clock pulse in (d) is generated, low power consumption can be achieved.

Further, the solid-state image pickup device 31 is driven as shown in FIG.
In the clock pulse period corresponding to (d), the solid-state image sensor 3
If the power supply 1 is turned on and the clock signal CK1 is stopped, the maximum storage (photoelectric conversion) time in the solid-state image sensor 31 during the period in which the clock signal CK1 is stopped can be extended, and high sensitivity can be realized.

According to this embodiment, the signal processing unit in the preceding stage until writing to the frame memory 35 and the signal processing unit in the subsequent stage after reading are time-divisionally operated, and the clock frequency for the signal processing units in the preceding and succeeding stages is set. By making the values different, it is possible to reduce the power consumption according to the peak power consumption and the desired frame rate.

[0020]

As described above, according to the video camera device of the present invention, the power consumption is reduced in accordance with the peak power consumption and the frame rate of the video camera, so that the power supply is small in scale and low in cost. A circuit can be adopted, and it is possible to reduce the size and cost of the video camera.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a circuit configuration diagram for explaining a conventional video camera device for digital signal processing.

[Explanation of symbols]

31 ... Solid-state image sensor, 32 ... Analog signal processing unit, 33
... A / D converter, 34 ... Pre-stage processing section, 35 ... Frame memory, 36 ... Line memory, 37 ... Luminance signal processing section, 3
8 ... Color signal processing unit, 39 ... UV converter, 401, 402
… Timing generator.

─────────────────────────────────────────────────── --Continued from the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/232 H04N 5/235

Claims (5)

(57) [Claims] 1. An analog signal is converted into an optically captured analog video signal based on a first clock frequency, the analog video signal is converted into a digital video signal at the clock frequency, and a frame (or field) is also included. A pre-stage signal processing unit that performs digital signal processing that requires minimum writing in the memory, and reads the digital video signal written in the frame memory based on a second clock frequency, and performs at least luminance signal processing and color signal processing. A second-stage signal processing unit for performing peak-power consumption and a desired frame rate by setting the first-stage and second-stage signal processing units to time-division operation and setting the first and second clock frequencies to different values. A video camera device, which is characterized by being lowered. 2. The video camera device according to claim 1, wherein in the time division operation, power consumption is reduced by stopping a clock of a function or a period which does not require a clock. 3. The video camera device according to claim 1, wherein the power supply for the function or period not required is turned off. 4. When the first clock frequency is fck , the second clock frequency is fck / n (n is arbitrary), and the signal processing time for one frame (field) and the maximum accumulation of the solid-state imaging device ( photoelectric conversion) time and the video camera apparatus according to any one of claims 1 to 3, characterized in that the n + 1 times. 5. The video camera according to claim 4, wherein when the illuminance of the subject becomes low, a desired frame rate is automatically lowered, and long-time storage is realized to achieve high sensitivity. apparatus.