JP2000023003A - Video camera device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video camera device which can perform time division processing by clock signals of different frequencies and can reduce its power consumption by stopping temporarily a desired function. SOLUTION: A signal processing part of the preceding stage including to a writing operation that is executed to a frame memory 35 from a solid state image pickup device 31 and a signal processing part of the next stage following a read operation executed out of the memory 35 are operated in time division. The clock signals CK1 and CK2 are set at different clock frequencies for both signal processing parts of the preceding and next stages. Then the signals CK1 and CK2 are turned on and off according to the said time division operations. Thus, the power consumption can be reduced for a video camera device in response to its peak power consumption and its frame rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a video camera apparatus for performing a time-division process using a memory on a video signal captured by an image sensor.

[0002]

2. Description of the Related Art A conventional digital signal processing video camera apparatus will be described with reference to the block diagram of FIG. The one-dimensional analog video signal extracted from the solid-state imaging device 31 is input to an analog signal processing unit 32, where a
(Correlated double sampling circuit) to remove noise,
The gain is adjusted by a GCA (gain control amplifier) and output to the A / D converter 33 in the next stage, where it is converted into a digital video signal. The digital video signal is input to the pre-processing unit 34. The processing performed by the pre-processing unit 34 includes black (O
B: optical black) clamping, fluorescent lamp flicker correction, lens shading correction, flaw (pixel defect) correction, color carrier amplification, high-luminance color carrier (horizontal stripe) suppression, AES + AGC control, and gamma correction (non-linear processing). The video signal processed by the pre-processing unit 34 is written into the frame memory 35.

A video signal read from the frame memory 35 is converted into a two-dimensional image signal of two lines via a line memory (1H delay line) 36 and converted into a multi-dimensional image signal by a luminance signal processing unit 37 and a color signal processing unit 38. Enter each. The luminance signal processing unit 37 performs horizontal and vertical contour corrections,
The color signal processing unit 38 performs color separation, color correction, and generation of a color difference signal. The color difference signal subjected to the color processing is input to the UV converter 39, where the signal band is reduced and a serial digital U, V signal is output in a time division manner.

[0004] A timing generator 40 outputs a driving signal of the solid-state image sensor 31 and a write / read pulse of the frame memory 35 from the solid-state image sensor 31 to a luminance signal processing unit 37 and a UV converter 39 based on the continuous wave clock signal CK. Generates and supplies clock pulses required for processing of each block up to.

In the above-mentioned conventional video camera, driving of a solid-state image pickup device for reading a video signal, analog signal processing for noise reduction (CDS) / gain adjustment (AGC) of a video signal, A / D conversion, digital video Signal preprocessing,
The 1 or 2H delay and the luminance signal processing / color signal processing using the line memory have all been simultaneously operated in parallel using the timing pulse generated by the timing generator 40. For this reason, it has been impossible to reduce peak power consumption and reduce power consumption.

A video camera uses a broadcast system (P) of 25 or 30 frames (50 or 60 fields) / sec.
AL / NTSC)
Y / C output in 25 or 30 frames even when only a photographed image of about a dozen frames / second is required.
(Luminance / color) Use by thinning out the signal.

[0007] The reason is that it is difficult to lower the driving frequency itself of the solid-state image pickup device in terms of the operation and characteristics of the device, and also, it constitutes an automatic sensitivity adjustment (AES: electronic shutter iris) circuit or a fluorescent lamp flicker correction circuit. In that case, the system becomes complicated. In analog signal processing for performing noise reduction / gain adjustment of video signals and A / D conversion, power consumption is substantially determined by a signal band (frequency characteristics) passing therethrough. Therefore, in a circuit designed on the premise of a broadcast system, Simply sample and hold pulse or A / D
Even if the clock frequency for conversion is reduced, reduction in power consumption cannot be realized.

[0008]

In the above-mentioned conventional video camera apparatus, it was not functionally possible to stop a part of the processing in order to save power.

SUMMARY OF THE INVENTION The present invention provides a video camera apparatus which enables time-division processing with clock signals having different frequencies and temporarily stops desired functions to save power.

[0010]

In order to solve the above-mentioned problems, a video camera device according to the present invention converts an analog signal into an optically captured analog video signal based on a first clock frequency. A pre-stage signal processing unit that converts the analog video signal into a digital video signal at a clock frequency and performs digital signal processing that requires minimum writing in a frame (or field) memory; A post-signal processing unit that reads out the digital video signal written in the memory and performs at least luminance signal processing and chrominance signal processing, and performs the time-division operation on the pre-stage and post-stage signal processing units; 2 with a different clock frequency to obtain a desired frame rate and peak power consumption. Achieving a reduction.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described in detail below with reference to the circuit diagram of FIG. 1. The same components as those in FIG. explain.

In FIG. 1, a one-dimensional analog video signal extracted from a solid-state image sensor 31 is input to an analog signal processing unit 32. The analog signal processing unit 32 is a CDS
And GCA to perform noise removal and gain adjustment. The output of the analog signal processing unit 32 is converted into a digital video signal via an A / D converter 33 and input to a pre-processing unit 34. The processing performed by the pre-processing unit 34 includes a black clamp,
Fluorescent flicker correction, lens shading correction, flaw correction, color carrier amplification, high luminance color carrier suppression, AES
+ AGC control and gamma correction. The preprocessed video signal is written into the frame memory 35.

The video signal read from the frame memory 35 is converted into a multi-dimensional video signal for two lines via a line memory (1H delay line) 36 and transmitted to a luminance signal processing unit 37 and a color signal processing unit 38. Enter each. The luminance signal processing unit 37 performs horizontal and vertical contour corrections,
The digital luminance signal Y is output from the output. The color signal processing unit 38 performs color separation, color correction, and generation of a color difference signal. The color difference signal subjected to the color processing is input to the UV converter 39, where the signal band is reduced and a serial digital U, V signal is output in a time division manner.

The timing generator 401 generates and supplies a clock pulse required for signal processing at a preceding stage from the solid-state image sensor 31 to writing to the frame memory 35 based on the continuous wave clock signal CK1. Also,
The timing generator 402 generates and supplies a clock pulse required for signal processing in a subsequent stage from reading of the frame memory 35 to the luminance signal processing unit and the UV converter 39 based on the continuous wave clock signal CK2.

The operation of FIG. 1 will be described with reference to the timing chart of FIG. FIG. 2A shows one vertical period (one screen).
5A shows a video signal after A / D conversion, which is written in the frame memory 35, and FIG. 4B shows a video signal read from the frame memory 35 for one vertical period (one screen). FIG.
(C) shows a clock pulse for driving the A / D converter 33 generated based on the continuous wave clock signal CK1, and (d) shows a clock pulse generated based on the continuous wave clock signal CK2. 7 shows clock pulses for driving the luminance and color signal processing units 37 and 38.

In the example of FIG. 2, the clock frequency of (c) is set to be three times that of (d). That is, the frequency of the clock signal CK1 is 3 times the frequency of the clock signal CK2.
It is set to double. Therefore, the reading time is three times as long as the writing time to the frame memory 35.

Therefore, the clock signal CK2 is stopped during the period in which the clock pulse shown in FIG.
If the clock signal CK1 is stopped during the period in which the clock pulse of (d) is generated, low power consumption can be achieved.

FIG. 2 shows a state in which the solid-state imaging device 31 is driven.
During the clock pulse period corresponding to (d), the solid-state imaging device 3
If the power supply 1 is turned on and the clock signal CK1 is stopped, the maximum accumulation (photoelectric conversion) time in the solid-state imaging device 31 during the period when the clock signal CK1 is stopped can be extended, and high sensitivity can be realized.

According to this embodiment, the signal processing unit at the preceding stage before writing to the frame memory 35 and the signal processing unit at the subsequent stage after reading out are time-division multiplexed, and the clock frequency for the signal processing unit at the previous stage and the subsequent stage is Are set to different values, it is possible to reduce the power consumption according to the peak power consumption and the desired frame rate.

[0020]

As described above, according to the video camera apparatus of the present invention, the power consumption is reduced according to the peak power consumption and the frame rate of the video camera. A circuit can be adopted, and the size and price of the video camera can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram for describing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a circuit configuration diagram for explaining a conventional digital signal processing video camera device.

[Explanation of symbols]

31: solid-state imaging device, 32: analog signal processing unit, 33
... A / D converter, 34 ... pre-processing unit, 35 ... frame memory, 36 ... line memory, 37 ... luminance signal processing unit, 3
8: color signal processing unit, 39: UV converter, 401, 402
... timing generator.

Claims (6)

[Claims] An analog signal is converted into an optically captured analog video signal based on a first clock frequency, the analog video signal is converted into a digital video signal at the clock frequency, and a frame (or field) is converted. A pre-stage signal processing unit that performs digital signal processing that requires minimum writing to the memory; and reads the digital video signal written to the frame memory based on a second clock frequency, and performs at least luminance signal processing and color signal processing. A post-stage signal processing unit that performs a time-division operation on the pre-stage and post-stage signal processing units, and sets the first and second clock frequencies to different values, so that the peak power consumption and the desired frame rate can be reduced. A video camera device characterized by reduction. 2. The video camera device according to claim 1, wherein in the time-division operation, a clock that does not require a clock or a clock in a period is stopped to reduce power consumption. 3. The video camera device according to claim 1, wherein a power supply of a function or a period that is not required is turned off. 4. When the first clock frequency is fck, the second clock frequency is fck / n (n is arbitrary), and the signal processing time for one frame (field) and the maximum accumulation ( The video camera device according to any one of claims 1 to 3, wherein a (photoelectric conversion) time is made n + 1 times. 5. The video camera according to claim 4, wherein when the illuminance of the object is reduced, a desired frame rate is automatically reduced, and long-time accumulation is realized to achieve high sensitivity. apparatus. 6. A pre-stage signal processing unit that drives an image sensor based on a first clock frequency and writes a video signal that has been subjected to one-dimensional signal processing to a memory, and stores the video signal in the memory based on a second clock frequency. A video camera device comprising: a post-stage signal processing unit that reads out the written video signal and extracts the video signal as a video signal subjected to multidimensional signal processing.