JP3373382B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [0001] The present invention relates to the manufacture of semiconductor devices.
And, more particularly, to a wiring pattern of a semiconductor device.
This is related to the design of the [0002] 2. Description of the Related Art Semiconductor device manufacturing using multilayer wiring technology
In the process, the lower wiring
If the steps remain due to the influence of
Problem, and normal patterning cannot be performed. For example, as shown in FIG.
During exposure to 1, focus on the top and bottom of the step
A difference occurs, and the line width is
Or differences in shape. Further, as shown in FIG.
Is formed under the resist 51 near the boundary of
An inclination occurs in the layer wiring layer 52, and the above-mentioned inclined portion is irradiated.
The reflection or reflection of the light may cause the resist 51 to collapse or narrow.
May occur. Further, as shown in FIG.
The thickness of the lower resist 51 is thicker than the upper part of
In the portion where the thickness of the resist 51 is large, sufficient exposure is not performed.
And the resist 51 may remain even after development.
You. In this state, an etching process for forming the upper wiring
Is performed, the upper wiring material under the remaining resist 51 is removed.
Is not completely removed by the
It becomes easier. [0004] In order to prevent the above-mentioned problem, the steps of the lower-layer wirings are reduced.
Insert a dummy layer to make up for the concave part, and flatten the upper layer
There is a way to do it. Conventionally, dummy insertion method for flattening
As the method, for example, JP-A-6-349730 and
There is a method disclosed in JP-A-8-6231.
You. [0005] Japanese Patent Application Laid-Open No. 6-349730 discloses the above.
This method will be described with reference to FIG. First, as shown in FIG.
The lower wiring 54 is formed on the substrate 53. In FIG. 15 (b)
As shown, an interlayer insulating film 55 is formed on the lower wiring 54.
Form. Next, as shown in FIG.
Having a thickness corresponding to the unevenness of the interlayer insulating film 55
Forming an insulating film 56 for pattern formation; And FIG.
As shown in FIG. 5D, a photo for forming a dummy pattern is formed.
The concave portions of the lower wiring 54 and the interlayer insulating film 55 are formed by the lithography mask.
Is patterned so as to cover the resist 51, and FIG.
(E) As shown in FIG.
By etching 56, the lower wiring 54 and the layer
The dummy pattern having the thickness of the step difference of the insulating film 55 is formed.
It is formed in the recess of the step. Further, FIG.
As shown in FIG. 15 (g), the resist 51 is peeled off,
An interlayer insulating film 55 is formed, and the lower wiring 54 and the interlayer insulating film 5 are formed.
The unevenness of No. 5 is reduced and flattening is performed. [0007] Subsequently, Japanese Patent Application Laid-Open No. Hei 8-6231 discloses the above.
The disclosed method is described below. First, multilayer wiring is applied to all wiring patterns.
The wiring patterns of each layer are compared with each other. At this time,
There is a closest pattern in the upper wiring pattern,
The space of the lower wiring pattern immediately below is twice the wiring pitch
If there is a gap above the dummy putter in the space
Generate Then, place the dummy pattern in the lower layer
By combining with the line pattern, it becomes the lower part of the step
Dummy pattern is inserted in the space of the lower wiring layer
Create a photolithography mask. Then, as shown in FIG.
By using a photolithography mask,
By performing patterning with the me pattern 57, FIG.
As shown in (b), an interlayer insulating film 5 is formed on the lower wiring 54.
5 is formed, and as shown in FIG.
By forming the upper wiring layer 58, the lower wiring
The effect of the step due to this is reduced, and the
The layer wiring layer 58 can be formed. [0010] However, the above-mentioned Japanese Patent Application Laid-Open
In the method disclosed in JP-A-6-349730, the step is eliminated.
However, in order to insert a dummy pattern,
Steps for forming turns (use for dummy pattern formation)
Edge film formation, exposure / development, etching, and resist
Peeling off) increases. Also, expose the dummy pattern layer
Also requires a photolithography mask to manufacture
There is a problem that the cost increases. Further, Japanese Patent Application Laid-Open No. H8-6231 discloses
Method increases the number of steps and photolithography masks
Problem does not occur, but photolithography
When designing a disk, the wiring pattern of each layer of the multilayer wiring layer
Data processing, such as the need to compare
There is a problem that it is rough. Further, a dummy putter for eliminating a step is provided.
Space for the lower wiring pattern
It is necessary to have an interval of at least twice the wiring pitch. this
Therefore, the space of the lower wiring pattern is twice the wiring pitch
The dummy pattern cannot be inserted in a place less than
There is a limitation on the range of application. That is, Japanese Patent Application Laid-Open No. 8-623
In the method disclosed in Japanese Patent Application Laid-Open No. H11-209, as shown in FIG.
The space between the lower wirings 54 that does not cause
If it is less than twice the space between the lower wirings 54,
Slightly less than twice the line pitch (see Fig. 17 (a))
Therefore, even after the formation of the interlayer insulating film 55,
A step remains (see FIG. 17B). Therefore, the above layer
The flatness of the upper wiring layer 58 formed on the interlayer insulating film 55
There is a problem that it cannot be obtained (see FIG. 17C). The present invention has been developed to solve the above problems.
The purpose was to determine the number of processes and photolithography.
Without increasing the number of masks,
Without limiting the scope of application
Obtain flatness enough to successfully pattern upper wiring
And can design wiring patterns efficiently.
An object of the present invention is to provide a method for manufacturing a conductor device. [0014] According to the present invention, there is provided a semiconductor device comprising:
The manufacturing method is such that an upper layer wiring is formed on the lower layer wiring via an interlayer insulating film.
Line is formed and has at least two or more wiring layers.
A method for manufacturing a semiconductor device having a layer wiring structure,
In order to solve the problem, the minimum allowable space width and
And the minimum line width are MinS and MinL, respectively.
When designed to obtain the desired device characteristics
For the initial lower wiring pattern, the initial lower wiring pattern
(Min)
First step of increasing by L + MinS × 2) / 2
Of the wiring pattern obtained in the first step.
Data part and the data-less part are inverted to create a dummy pattern.
The second step of obtaining and the second step
The size of the dummy pattern is set to
And a third step of increasing by / 2Along with
Patterning of upper layer wiring without inserting dummy pattern
The maximum space width of the lower wiring layer that does not cause defects during
S ₁ And given by MinL + MinS × 2
Space where dummy pattern can be inserted is S _Two Then
Come, S ₁ ≧ S _Two Is obtained in the third step above.
And the initial lower wiring pattern
Wiring using the exposure mask of the wiring pattern obtained by
Patterning, S ₁ <S _Two In the case of
Adjust the size of each lower layer wiring of the initial lower layer wiring pattern
One of the left and right sides and one of the left and right sides
About MinS and S ₁ Increased by the following sizes
Obtained in the fourth step and the third step
The size of the dummy pattern is set to
The fifth step, and the fourth step
And the wiring pattern obtained in the fifth step.
A sixth step of synthesizing a dummy pattern to be synthesized;
The data part and the data of the pattern obtained in the sixth step
And the seventh step of reversing the dataless part.
And the dummy pattern obtained in the third step.
7 and the initial lower wiring pattern
Exposure mask of the wiring pattern obtained by combining
Patterning of lower wiring usingCharacterized by
I have. [0015]S ₁ ≧ S _Two In Case of,The first and second
Depending on the step, the minimum
A dummy pattern with a line width is placed between each lower layer wiring.
Can be formed with a minimum space width
Dummy patterns can be obtained only in an appropriate lower wiring space.
Further, by the third step, the second step
The size of the dummy pattern obtained in
To increase the initial lower layer arrangement by increasing MinL / 2.
Dummy with MinS lower wiring space between lines
A pattern is obtained. [0016] Dummy pattern obtained in the third step
And the initial lower wiring pattern
Patterning of underlying wiring using a turn exposure mask
By doing so, the pattern between the lower wiring and the dummy pattern
Can be performed in the same step. Therefore,
The number of steps and the number of exposure masks are not increased. [0017] [0018] S₁<S_TwoIn the case of
Therefore, the lower wiring space required around the lower wiring is not required.
A corresponding area is provided. In the fifth step,
Therefore, the lower wiring space where the dummy pattern can be inserted is
Given. Therefore, in the sixth step,
And the wiring pattern obtained in the fourth step
Combining the dummy pattern obtained in the fifth step.
In this case, the lower wiring space cannot be
There is no data where no pattern can be inserted
It remains as a club. In the seventh step, the sixth step
Data part and non-data part of the pattern obtained by step
And the area where the lower layer wiring is thickened
can get. Dummy pattern obtained in the third step
And the pattern obtained in the seventh step,
The exposure pattern of the wiring pattern obtained by combining the
By patterning the lower wiring using a mask,
And the patterning of the lower wiring and the dummy pattern are the same.
Can be performed. Therefore, the number of processes and exposure
It does not increase the number of masks. Further, in the method of manufacturing a semiconductor according to the above configuration,
Defines the lower layer wiring pattern design as upper layer wiring and lower layer wiring.
Can be designed without comparing these patterns. Furthermore, puta
Data processing at the time of layout design, data size change and inversion
And can be performed with relatively simple processing such as synthesis.
Wiring patterns can be designed efficiently. Further, the maximum value S of the lower wiring space₁Yo
Space S that is large enough to insert a dummy pattern
_TwoIn the following lower wiring space, make the lower wiring thicker.
By doing so, the lower wiring space becomes S₁Less than
The initial lower-layer wiring pattern and manufacturing process
The upper layer wiring can be properly patterned without
Flatness as much as possible can be obtained. [0023] FIG. 1 is a diagram showing an embodiment of the present invention.
1 to 11 are as follows.
You. Semiconductors manufactured using a multilayer wiring process
In the body device, as shown in FIG.
The interlayer insulating film 3 is formed on the
The upper wiring 4 is patterned on the interlayer insulating film 3.
You. Further, a step for eliminating a step due to the lower wiring 2 is provided.
A dummy pattern 5 is formed in the same layer as the lower wiring 2.
You. In the present embodiment, after the interlayer insulating film 3 is formed,
Surface step angle is 30 ° or more, or step amount is 2500
と き Above the above, normal patterning of upper wiring 4 cannot be performed.
I suppose. Here, the step angle is defined as shown in FIG.
Of the lower wiring 2 with respect to the surface of the semiconductor substrate 1
From the center point to the center point of the space next to the wiring
Is the maximum value a of the inclination angle of the surface of the interlayer insulating film 3. Ma
In addition, the above-mentioned step amount is based on the surface of the semiconductor substrate 1.
Space from the center point of the lower wiring 2
Of the surface height of the interlayer insulating film 3 up to the center point
You. First, from the plot shown in FIG.
Lower wiring space with a difference angle of 30 ° (adjacent lower wiring
(The distance between 2 and 2) and the amount of the step is 2500 °
Find the lower wiring space. At this time, the above two lower layers
The smaller value of the wiring space
Defects occur during patterning of upper layer wiring even without insertion
The maximum space width of the lower wiring layer that does not
(Referred to as line space) S₁Becomes In the plot of FIG.
Means that the lower wiring space where the step angle is 30 ° is 1.65.
μm, and the lower wiring space with a step height of 2500 °
1.2 μm, the maximum lower wiring space S₁
Is 1.2 μm. The lower wiring space, the step angle and the step
The relationship with the difference depends on the manufacturing process,
Wiring space S₁Also depends on the manufacturing process. example
For example, in the plot shown in FIG. 5, the step angle is 30 °.
The lower wiring space is 3.3 μm and the level difference is 250
Since the lower wiring space where 0 ° is 2.1 μm,
Maximum lower wiring space S₁Is 2.1 μm. The above
Lot diagrams are determined by prior measurement in the relevant process.
Desired. Due to the processing limit of the lower wiring or the design
The minimum space width (Mi
nS) and the minimum line of the lower wiring and the dummy pattern
When the width (MinL) is 0.7 μm,
Pattern of the lower layer wiring including the dummy pattern
Is designed. FIG. 6 shows a pattern of the lower layer wiring in an initial state.
(Hereinafter referred to as an initial lower wiring pattern) 6 is shown. Here, MinL + MinS × 2
The given space width must be
S_TwoAnd Space where the above dummy pattern can be inserted
S_TwoIs a dummy pattern having a minimum line width MinL
5 between the lower wiring 2 and the minimum wiring width MinS.
Represents a space that can be formed.
In the present embodiment, the minimum line width MinL and the minimum
Since both the pace widths MinS are 0.7 μm,
ー Pattern insertion space S_TwoIs 2.1 μm. A method for manufacturing a semiconductor device according to the present embodiment.
Then, 2.1 μm (S_Two) Larger lower wiring space
In the above, the dummy pattern 5 is provided in the lower wiring space.
Inserted. The design procedure of the dummy pattern 5 is shown in FIG.
This will be described below with reference to FIG. First, as shown in FIG.
The layer wiring pattern 6 is set to 2.1 μm (S_Two) Plus resize
I do. That is, the entire periphery of the initial lower wiring pattern 6
In the above, a region having a width of 2.1 / 2 μm is formed.
Become. Subsequently, the data of the pattern diagram shown in FIG.
Data part (hatched part in FIG. 1 (a)) and the part without data
By inverting, the pattern diagram shown in FIG.
can get. In the pattern diagram shown in FIG.
Is 2.1 μm (S_Two) For larger lower wiring space
Only the dummy pattern 5 (the hatched portion in FIG. 1B) is provided.
Have been. However, the dummy pattern 5 at this time is
The space between the initial lower wiring pattern 6 is 2.1 / 2.
μm (S_Two/ 2 = MinL / 2 + MinS).
In order to make the space of the minimum space width MinS,
0.7 μm (MinL) plus the dummy pattern 5
Resize. As a result, as shown in FIG.
0.7 μm (Min) between the initial lower wiring pattern 6
The dummy pattern 5 having the space (S) is obtained. The dummy pattern 5 obtained by the above procedure is
2.1 μm (S_Two) For lower wiring space larger than
Only 2.1 μm (S_Two) Lower wiring below
There is no dummy pattern 5 in the space. here
In this manufacturing process, the lower wiring space and the step
The relationship between the difference angle and the step amount is shown in the plot of FIG.
Let's say At this time, the maximum lower wiring
Pace S₁Is 1.2 μm. The maximum lower wiring space S₁Is 2.1
μm (S_Two), 2.1 μm (S_Two) Less than
There is no effect of steps due to the lower wiring space.
No problem. However, in this case,
Line space S₁Is 1.2 μm and 2.1 μm
(S_Two) Is smaller than 1.2 μm (S₁)than
Adverse effects due to steps in large lower wiring space
I will. Therefore, 1.2 μm (S₁) And larger
2.1 μm (S_Two) About the following lower wiring space
To reduce the lower wiring space to 1.2 μm (S₁)
Need to be In such a case, the wiring is not placed in the lower wiring space.
Instead of inserting the me pattern 5, the lower wiring itself
By increasing the thickness, the space for the lower layer wiring can be reduced.
You. The design procedure for the part where the lower wiring is thickened is described with reference to FIG.
This will be described below. First, as shown in FIG.
1.2 μm on the lower side and the left side of the wiring pattern 6
m (S₁) In order to form a region of width,
The line pattern 6 is resized. The newly formed territory
The area indicates the area where the lower wiring space is formed.
You. In the present embodiment, the width of the region is 1.2 μm
, But the minimum space width is MinS or more,
Wiring space S₁Any value can be set if it is below. FIG. 7 (b) and FIG. 1 (c)
Dummy pattern 5 is further 1.4 μm (MinS × 2)
FIG. 4 shows a plus-resized pattern diagram. FIG. 7 (b) above
Data portion in the pattern diagram of FIG.
Part) is 2.1 μm (S_Two) Larger lower wiring space
In other words, the lower layer wiring
Is shown. The data portion of FIG. 7A and the data portion of FIG.
The pattern shown in FIG. 7C showing the logical sum of the data part shown in FIG.
The area diagram shows all areas where the underlying wiring does not need to be fat.
It is. Therefore, the data portion shown in FIG.
By inverting the blank part, as shown in FIG.
As a result, the pattern of the area that makes the lower wiring thicker is obtained.
You. As described above, the initial lower wiring pattern shown in FIG.
7, the dummy pattern 5 shown in FIG.
The logic of the pattern of the region where the lower wiring is thickened as shown in FIG.
When the sum is taken, as shown in FIG.
Is obtained. The lower wiring pattern obtained as described above
Photolithography mask (exposure mask)
By forming the lower wiring using
Can obtain enough flatness to be able to pattern properly
it can. Using the above photolithography mask
As a result, as shown in FIG. 9A and FIG.
The dummy pattern 5 and the lower wiring are formed on the semiconductor substrate 1.
2 is formed. The above figure
9 (a) shows a dummy pattern 5 between adjacent lower wirings 2;
Is provided, and FIG.
Is the case where a part of the lower wiring 2 is made thick to form the lower wiring 6
Is shown. In both cases, the lower wiring space is
To the extent that there is no step that adversely affects upper wiring 4
Formed. FIG. 9 (b) and FIG. 10 (b)
As shown, the interlayer insulating film 3 is formed on the lower wiring pattern.
Is formed, the upper wiring 4 can be normally patterned.
The surface of the interlayer insulating film 3 having only flatness can be obtained.
Wear. Also, as shown in FIG. 9 (c) and FIG. 10 (c)
Then, an interlayer insulating film 3 is further formed on the interlayer insulating film 3
By doing so, even more flatness can be obtained. The lower wiring pattern shown in FIG.
As described above, the maximum lower wiring space S₁Is 2.1μm
This is the final lower-layer wiring space in the case where it is smaller than I
However, the maximum lower wiring space S₁Is a manufacturing professional
The maximum lower wiring space S₁But
Dummy pattern insertable space S_TwoMay be more than
is there. For example, lower wiring space, step angle and step
Manufacturing with the relationship between the quantity and the plot shown in FIG.
In the process, the maximum lower wiring space S₁Is 2.
1 μm. As described above, the maximum lower wiring space S₁But
2.1 μm (S_Two), 2.1 μm (S_Two)
Thick the lower layer wiring in the following lower layer wiring space
Since there is no need, the initial lower wiring pattern 6 shown in FIG.
And the logical sum of the dummy pattern 5 shown in FIG.
Then, the final lower wiring pattern as shown in FIG.
can get. Then, the FO having the lower wiring pattern is formed.
The underlying wiring using a photolithographic mask
In this way, upper layer wiring can be
Can be obtained. When the manufacturing process is changed,
If the design dimensions allowed on the
The data of the step amount and the step angle shown in FIG.
Large lower wiring space S₁Should be asked again. In this embodiment, the arrangement of the semiconductor device is described.
Although the case where the number of wiring layers is two is illustrated, three or more wiring layers
The present invention is also applicable to the case of manufacturing a semiconductor device having
Is applicable. As described above, the semiconductor according to the present embodiment
In the device manufacturing method, S₁≧ S_TwoIn case of
(C) Dummy pattern 5 shown in FIG.
Photolithography of a wiring pattern obtained by synthesizing
Pattern the lower layer wiring using a luffy mask,
S₁<S_TwoIn the case of, the dummy pattern shown in FIG.
7 and the pattern shown in FIG.
Photolithography of wiring pattern obtained by synthesizing turn 6
Patterning of lower wiring using lithography mask
U. Therefore, the maximum value S of the lower wiring space
₁A space that is larger and allows the dummy pattern 5 to be inserted
S_TwoIn the following lower wiring space, the lower wiring
To make the lower wiring space S₁Less than
The initial lower wiring pattern 6 and the manufacturing process
Upper layer wiring successfully without being limited by
Flatness sufficient for patterning can be obtained.
Also, patterning of the lower wiring and the dummy pattern 5 is performed.
Since it can be performed in the same process, the number of processes and photolithography
It does not increase the number of lithography masks. The method of manufacturing a semiconductor according to the present embodiment
In the method, the pattern design of the lower layer wiring is
It can be designed without comparing the pattern with the line. further,
Data processing at the time of pattern design, data size change,
It can be done with relatively simple processing such as inversion and synthesis
Therefore, the wiring pattern can be efficiently designed. [0051] The method of manufacturing a semiconductor device according to the first aspect of the present invention.
Is the minimum allowable space width and maximum
The small line widths are MinS and MinL, respectively.
When the initial designed to obtain the predetermined device characteristics
For the lower wiring pattern, the initial lower wiring pattern
The size of each lower layer wiring is set to (MinL +
A first step of increasing by MinS × 2) / 2;
Data of the wiring pattern obtained in the first step
To obtain a dummy pattern by inverting the area and the area without data
The second step and the dam obtained in the second step.
-The size of the pattern is MinS / 2 over the entire circumference.
And a third step of increasingDami
-When patterning upper wiring without inserting a pattern
The maximum space width of the lower wiring layer where no failure occurs ₁
And the damage given by MinL + MinS × 2
-Space where the pattern can be inserted is S _Two And S ₁
≧ S _Two In the case of, the dummy obtained in the third step
-Pattern and initial lower wiring pattern
Pattern of the lower wiring using the exposure mask of the wiring pattern
And S ₁ <S _Two In the case of
The size of each lower layer wiring of the layer wiring pattern
Side and one of the left and right sides
And MinS and S ₁ No. to increase by the following size
Step 4 and the dummy obtained in the third step.
Increase the size of the pattern by MinS over the entire circumference
The fifth step of adding
Wiring pattern obtained in the fifth step.
A sixth step of synthesizing a me pattern and the sixth step;
Of the pattern obtained in the step
Performing the seventh step of reversing the setting part and the third step.
The dummy pattern obtained in the step
The pattern obtained by the step and the initial lower wiring pattern
Using the exposure mask of the wiring pattern obtained by combining
Perform lower layer wiring patterningConfiguration. Therefore, the lower wiring and the dummy pattern
Patterning can be performed in the same process,
There is no increase in the number of photolithography masks. Ma
In addition, data processing during pattern design also
Can be performed with relatively simple processing such as update, inversion and synthesis
Therefore, the wiring pattern can be efficiently designed.
This has the effect. [0053] [0054]further,S₁<S_TwoIn the case of₁Greater than
K and S_TwoIn the lower wiring space below,
By making the layer wiring thicker, the space for the lower layer wiring is reduced by S.
₁The initial lower wiring pattern and manufacturing process
Correct the upper layer wiring without being limited by the process coverage.
Can always obtain flatness enough to pattern
It has the effect of

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates one embodiment of the present invention, and is an explanatory view illustrating a procedure for designing a dummy pattern in a lower wiring pattern of a semiconductor device. FIG. 2 is a cross-sectional view illustrating a schematic configuration of the semiconductor device. FIG. 3 is an explanatory diagram showing a step angle and a step amount generated on a surface of an interlayer insulating film of the semiconductor device. FIG. 4 is an explanatory diagram showing an example of a relationship between a lower wiring space of the semiconductor device and the step angle and the step amount; FIG. 5 is an explanatory diagram showing another example of the relationship between the lower wiring space of the semiconductor device and the step angle and the step amount; FIG. 6 is an explanatory diagram showing an example of an initial lower wiring pattern of the semiconductor device. FIG. 7 is an explanatory diagram showing a design procedure of a region where the lower wiring is thickened in the lower wiring pattern. FIG. 8 is an explanatory diagram showing a final lower wiring pattern obtained from the initial lower wiring pattern shown in FIG. 6 when S ₁ <S ₂ . FIG. 9 is a cross-sectional view showing a manufacturing process when a semiconductor device is manufactured using a photolithography mask having the final lower wiring pattern, and showing a manufacturing process of a portion where a dummy pattern is inserted. FIG. 10 is a cross-sectional view showing a manufacturing process when a semiconductor device is manufactured using a photolithographic mask having the final lower wiring pattern, and showing a manufacturing process of a portion where the lower wiring is thickened. FIG. 11 is an explanatory diagram showing a final lower layer wiring pattern obtained from the initial lower layer wiring pattern shown in FIG. 6 when S ₁ ≧ S ₂ ; FIG. 12 is a cross-sectional view showing an example of a problem caused by the influence of a step due to a lower wiring. FIG. 13 is a cross-sectional view showing another example of the problem caused by the influence of the step due to the lower wiring. FIG. 14 is a cross-sectional view showing another example of the problem caused by the influence of the step due to the lower wiring. FIG. 15 is a cross-sectional view showing an example of a conventional semiconductor manufacturing process. FIG. 16 is a cross-sectional view showing a semiconductor manufacturing process using a photolithography mask created by a mask designing method in a conventional semiconductor manufacturing method. FIG. 17 is a cross-sectional view showing a problem that occurs in the semiconductor manufacturing process. [Description of Signs] 2 Lower wiring 3 Interlayer insulating film 4 Upper wiring 5 Dummy pattern 6 Initial lower wiring pattern S ₁ Maximum lower wiring space S ₂ Dummy pattern insertable space MinS Minimum space width MinL Minimum line width

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 G03F 1/08 H01L 21/82

Claims (1)

(1) A semiconductor for manufacturing a semiconductor device having a multi-layer wiring structure having an upper wiring formed on a lower wiring via an interlayer insulating film and having at least two wiring layers. In the method of manufacturing a device, when an allowable minimum space width and an allowable minimum line width are MinS and MinL, respectively, the initial lower wiring pattern designed for obtaining predetermined device characteristics is compared with the initial lower wiring pattern. (MinL + MinL)
A first step of increasing by S × 2) / 2, a second step of inverting a data portion and a non-data portion of the wiring pattern obtained in the first step to obtain a dummy pattern, Third, the size of the dummy pattern obtained in the second step is increased by MinL / 2 over the entire circumference.
Patanin of while chromatic and steps, without inserting the dummy pattern upper wiring
The maximum space width of the lower wiring layer that does not cause defects during
S ₁ and given by MinL + MinS × 2
And can be inserted space of the dummy pattern and S ₂
When S ₁ ≧ S ₂ , the sum obtained in the third step is obtained.
Combining the me pattern and the initial lower wiring pattern
Using the exposure mask of the wiring pattern
When S ₁ <S ₂ , the size of each lower layer wiring of the initial lower layer wiring pattern is
One of the left and right sides and one of the left and right sides
For door, it is increased by S ₁ following of greater than or equal to the size MinS
And the size of the dummy pattern obtained in the third step.
Fifth step that increases MinS over the entire circumference
A step, a wiring pattern obtained in the fourth step, the first
Step 5 of combining the dummy pattern obtained in step 5
Step 6, and the data portion of the pattern obtained in the sixth step.
Performing a seventh step of inverting the non-data portion and the dummy pattern obtained in the third step;
The pattern obtained in the seventh step and the initial lower wiring pattern
Exposure mask of wiring pattern obtained by combining with turn
A method for manufacturing a semiconductor device, comprising patterning a lower layer wiring by using the method.