JP3367519B2 - Semiconductor memory device and test method therefor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a memory cell array composed of the same memory cells as a DRAM (Dynamic Random Access Memory). The present invention relates to a semiconductor memory device that operates under the same specifications as the above). In particular, the present invention is an SR in which a write enable signal that determines a write timing for a memory cell is asynchronously applied to a write address.
The present invention relates to a semiconductor memory device compatible with AM.

[0002]

2. Description of the Related Art SRAM and DRAM are the most typical semiconductor memory devices capable of random access. When compared with DRAM, SRAM is generally faster, and if the power is supplied and the address is input, the internal sequential circuit operates by catching the change in the address,
Read / write is possible. in this way,
Since the SRAM operates by giving a simpler input signal waveform than the DRAM, it is possible to simplify the configuration of the circuit that generates such an input signal waveform.

In addition, SRAM does not require refreshing for holding the data stored in the memory cell like DRAM, so that it is easy to handle and does not require refreshing, so data in a standby state is not required. It has the advantage that the holding current is small. For these reasons, SRAM is widely used for various purposes. However, since SRAM generally requires 6 transistors per memory cell,
The chip size is inevitably larger than M, and the price is inevitably higher than DRAM.

On the other hand, the DRAM gives a row address and a column address as addresses separately and separately, and RA as a signal for defining the fetch timing of these addresses.
Since the S (row address strobe) signal and the CAS (column address strobe) signal are required and the control circuit for periodically refreshing the memory cell is required, the timing control becomes complicated as compared with the SRAM. Will end up.

There is also a problem that the DRAM consumes a large amount of current because the memory cell needs to be refreshed even when there is no external access.
However, since a DRAM memory cell can be configured with one capacitor and one transistor, it is relatively easy to increase the capacity with a small chip size. Therefore, if a semiconductor memory device having the same storage capacity is configured, the DRAM is cheaper than the SRAM.

By the way, SRAM has been the mainstream so far as a semiconductor memory device adopted in a portable device typified by a portable telephone. This is because the conventional mobile phones were equipped with only simple functions, so that a large-capacity semiconductor memory device was not required, and timing control and the like compared to DRAMs made SRA.
The reason is that M is easy to handle, and because SRAM has a small standby current and low power consumption, it is suitable for mobile phones that want to extend continuous talk time and continuous standby time as much as possible.

However, mobile phones equipped with extremely rich functions have recently appeared, and the function of sending and receiving e-mails and accessing various sites to obtain town information of nearby restaurants and the like. Such functions are also realized. Not only that, but the most recent mobile phones are also equipped with a function to access the WEB server on the Internet and display the contents of the homepage in a simplified manner. In the future, similar to the current desktop personal computer In addition, it will be possible to freely access homepages on the Internet.

In order to realize such a function, it is not enough to display a simple text like a conventional mobile phone, and a graphic display for providing various multimedia information to the user is indispensable. Becomes For that purpose, it becomes necessary to temporarily store a large amount of data received from a public network or the like on a semiconductor memory device in a mobile phone. In other words, it is considered that a semiconductor memory device to be mounted on future mobile devices must have a large capacity like a DRAM. Moreover, since it is absolutely necessary that the portable device be small and lightweight, it is inevitable that the device itself becomes large and heavy even if the capacity of the semiconductor memory device is increased.

As described above, the SRAM is preferable as the semiconductor memory device mounted on the portable device in view of its easy handling and power consumption, but from the viewpoint of increasing the capacity, the DR is preferable.
AM will be preferred. That is, it can be said that the semiconductor memory device which incorporates the advantages of the SRAM and the DRAM is the most suitable for the portable device in the future. As a semiconductor memory device of this type, what is called a "pseudo-SRAM", which has the same specifications as an SRAM when viewed from the outside while using the same memory cell as that used in a DRAM, has already been considered. It is being used.

Unlike the DRAM, the pseudo SRAM does not need to divide the address into the row address and the column address and give them separately, and therefore, does not need the timing signals such as RAS and CAS. In the pseudo SRAM, general-purpose SRA
Similar to M, it is only necessary to give an address at a time, and the chip enable signal corresponding to the clock of the clock-synchronous semiconductor memory device is used as a trigger to fetch the address inside to perform reading / writing.

However, the pseudo SRAM is a general-purpose SRAM.
It is not always completely compatible with, and most of them have a refresh control terminal for externally controlling the refresh of the memory cell, and the refresh must be controlled outside the pseudo SRAM. . Therefore, most of the pseudo SRAMs are not easy to handle as compared with the SRAMs, and an extra circuit for refresh control is required. For this reason, as described below, it is not necessary to control refreshing outside the pseudo SRAM, and the general-purpose SRAM is
A pseudo SRAM designed to operate with exactly the same specifications as above has been considered. However, this type of pseudo SRAM also has various drawbacks as described below.

[0012]

First, as a first conventional example, Japanese Patent Laid-Open No. 61-5495 and Japanese Patent Laid-Open No. 62-188.
The semiconductor memory device disclosed in Japanese Patent Publication No. 096 is cited. The former semiconductor memory device internally has a refresh timer for measuring the refresh interval, and when a time corresponding to the refresh interval has elapsed, a refresh start request is generated and an amplification operation of a bit line pair in a read operation is performed. After completion of the above, the word line corresponding to the refresh address is activated to perform self refresh. By doing so, it is not necessary to control the refresh of the memory cell from outside the semiconductor memory device.

The latter semiconductor memory device specifically discloses the detailed structure of the operation timing control circuit for realizing the former semiconductor memory device.
Basically, it is similar to the former semiconductor memory device. Next, as a second conventional example, there is a semiconductor memory device disclosed in JP-A-6-36557. This semiconductor memory device also has an internal refresh timer,
A refresh start request is generated when a predetermined refresh time has elapsed, and self refresh is performed after the reading is completed.

However, the first conventional example and the second conventional example do not consider at what timing the write enable signal that determines the write timing is given, and the following problems may occur. is there. That is, when it is attempted to operate the pseudo SRAM with the same specifications as the general-purpose SRAM, the write enable signal is given asynchronously to the change in address. Self-refresh by a refresh start request also occurs asynchronously with respect to a change in address. Therefore, if the write enable signal is input later than the refresh start request and is activated in the second half of the memory cycle, for example, if self-refreshing has already started, it must be done after this self-refreshing is completed. If you can not write.

However, in that case, the writing performed after the self-refresh will be significantly delayed.
In order to avoid such a situation, it is necessary to give priority to writing over self-refresh. However, if this is done, there is no room for self-refresh to occur when writing continues in succession after a refresh start request occurs, and self-refresh may become impossible in practice. .

Further, in the first conventional example and the second conventional example, there is a problem that the access is delayed when the address includes a skew. That is, when the address has a skew, it is necessary to delay the word line selecting operation by the skew. This is because the memory cells of the DRAM used in the pseudo SRAM are generally destructive read, so when a certain word line is activated and read by a sense amplifier, all the memory cells connected to this word line are read. This is because it is necessary to rewrite the data originally stored in the memory cells from the sense amplifier to these memory cells.

Therefore, once the reading is started, the word lines cannot be switched in the middle until the rewriting corresponding thereto is completed. However,
If the address includes a skew, it is equivalent to a change in the address value, and as a result, the activated word line is switched. Therefore, a plurality of word lines are activated at the same time, the data of the memory cells connected to these word lines are read onto the same bit line, and the data of the memory cells are destroyed. become.

In order to prevent such a situation, it is necessary to delay activation of the word line by the skew included in the address as described above. Therefore, if the refresh is performed after the read, especially in the case where the skew is large, the start of the refresh is delayed by the delay of the word line selection operation due to the skew, and the read operation after the refresh is delayed. It will be.

Next, as a third conventional example, JP-A-4-24
The semiconductor memory device disclosed in Japanese Patent No. 3087 is cited. In this conventional example, the pseudo SRAM itself does not have a refresh timer, but a timer is provided outside the pseudo SRAM. Then, when the first access request is made after the refresh time has elapsed, the pseudo SRA
Create an OE (output enable) signal outside of M,
After refreshing according to the OE signal, reading or writing corresponding to the access request is performed.

However, the power consumption becomes too large in the configuration of the third conventional example, and it can be applied to a low power consumption product such as a mobile phone which is supposed to be used for a long time by a battery drive. There is a problem that you cannot do it. This is because in the third conventional example, the pseudo SRAM operates by latching the address input from the outside when the chip enable (CE) signal becomes valid. That is, in the third conventional example, since the chip enable signal needs to be changed every time the pseudo SRAM is accessed, the power consumption increases due to the charge / discharge current of the bus line of the chip enable signal wired on the mounting substrate. I will end up.

In addition to this, as a fourth conventional example, Japanese Patent No. 25
29680 (JP-A-63-206994)
The semiconductor memory device disclosed in US Pat. In this conventional example, a configuration similar to that of a conventional pseudo SRAM in which refresh is controlled from the outside is disclosed, and a configuration in which the configuration of this pseudo SRAM is applied and further improved is shown.

In the former configuration, the address change detection signal is generated in response to the valid output enable signal, self refresh is performed according to the refresh address generated in the pseudo SRAM, and then the output enable signal is invalid. Then, the address change detection signal is generated again, and the external address given from the outside of the pseudo SRAM is also refreshed. However, if the output enable signal is periodically generated at every refresh interval, the latter refresh targeting the external address is not originally necessary, and power is wasted as much as the external address is refreshed. It's closed.

On the other hand, in the latter configuration, the change of the external address is detected to generate the address change detection signal, the address change detection signal is used as a trigger to refresh the refresh address generated in the pseudo SRAM, and then the refresh address is generated. After a certain period of time has passed, an address change detection signal is generated again to perform normal read / write for an external address. However, such a configuration causes a problem when the external address includes a skew.

That is, when the external address includes a skew, each bit of the address changes at different timings. Therefore, an address change is detected at each timing and a plurality of address change detection signals are generated. It For this reason, even if the refresh is activated by the first address change detection signal, the normal access to the external address which should be originally performed after the completion of the refresh is activated by the second and subsequent address change detection signals. . That is, in this case, an access request is made to the external address even though the refresh is being performed. Therefore, as pointed out in the description of the first conventional example and the second conventional example, a plurality of word lines are activated at the same time, and the data of the memory cells connected to these word lines have the same bit. Since the data is read out on the line, the data in the memory cell is destroyed.

In addition to the above, the existing pseudo SRAM has the following problems. That is, a general-purpose SRAM or the like is often provided with a standby mode in which power supply to internal circuits is stopped and power consumption is extremely reduced. However, since the memory cell itself of the pseudo SRAM is the same as that of the DRAM, refreshing is always required to hold the data stored in the memory cell. For this reason, the conventional pseudo SRAM is not provided with a standby mode, which is adopted in a general-purpose SRAM, although it operates similarly to the SRAM.

However, the pseudo SRAM is a general-purpose SRA.
From the viewpoint of ease of use, it is desirable to prepare a low power consumption mode equivalent to the standby mode of the general-purpose SRAM as long as it is operated with the same specifications as M. Also, considering the recent remarkable improvement in functions of mobile phones and the like, it is expected that the pseudo SRAM will be applied to various uses in the future.

Therefore, it is naturally expected that the control such as the general-purpose SRAM that can be simply set to the standby state will be insufficient. Therefore, it is necessary to proactively provide a standby mode unique to the pseudo SRAM, which is not found in existing general-purpose SRAMs. To that end, it is considered to be extremely useful if the power consumption in the standby state can be finely and stepwise controlled according to the user's needs and applications.

Further, since the general-purpose DRAM is naturally premised on refreshing, the concept of standby itself does not exist, but the general-purpose DRAM naturally has a demand for low power consumption. Therefore, if the concept of standby mode is incorporated into general-purpose DRAM and power consumption can be reduced by finely controlling the power consumption in the standby state according to the user's needs and applications, a new application field for general-purpose DRAM will be created. It is thought that there are merits such as being able to cultivate.

The present invention has been made in view of the above points, and an object of the present invention is not to cause a problem that a normal access is affected by refreshing or to be unable to be refreshed due to continuation of writing, and to address. Even if the skew is included, no problems such as access delay and memory cell destruction occur, and the chip size is small and the power consumption is low even if the memory operates with a general-purpose SRAM specification and has a large capacity. Another object is to provide an inexpensive and inexpensive semiconductor memory device.
Another object of the present invention is to provide a semiconductor memory device having a standby mode equivalent to that employed in a general-purpose SRAM and a unique low power consumption mode not found in existing semiconductor memory devices. The objects of the present invention other than those described here will be apparent from the description of the embodiments below.

[0030]

In order to solve the above problems, the invention according to claim 1 provides a semiconductor memory device having a plurality of memory cells which need refreshing,
Refresh address generation means for generating a refresh address signal corresponding to the memory cell to be refreshed, address change detection means for generating an address change detection signal in response to an input address signal, and response to the address change detection signal And refreshing the memory cell corresponding to the refresh address signal, and then accessing the memory cell corresponding to the input address signal.

According to a second aspect of the present invention, in the first aspect of the present invention, the address change detection means generates the address change detection signal in response to a predetermined upper bit of the input address signal. , The control means,
For a plurality of memory cells in which the upper predetermined bits of the input address signal are the same, the page address composed of bits other than the upper predetermined bits of the input address signal is changed to successively output to the plurality of memory cells. It is characterized by access to. According to a third aspect of the present invention, in the first or second aspect of the invention, the address transition detection means generates the address transition detection signal in response to the input address signal or the activation signal, and activates the activation signal. The activation signal is a selection signal which is activated when the semiconductor memory device is accessed.

Further, the invention according to claim 4 is based on claim 1
In the invention described in any one of Item 3, the address change detection signal is a one-shot pulse. The invention according to claim 5 is the invention according to claim 4, wherein the control means performs the access after performing the refresh, with the generation of the one-shot pulse as one trigger. I am trying.
According to a sixth aspect of the present invention, in the invention according to the fourth or fifth aspect, the address transition detecting means is configured to output each bit of the input address signal used for generating the address transition detection signal or an activation signal. The one-shot pulse is generated by generating pulses having a predetermined width in response to the change and synthesizing the pulses.

The invention according to claim 7 is the invention according to claims 4 to 4.
In the invention described in any one of 6), the address change detection means has a one-shot having a pulse width exceeding the maximum value of the skew included in the input address signal or the activation signal as the address change detection signal. It is characterized by generating a pulse. The invention according to claim 8 is the invention according to any one of claims 4 to 7, wherein the address change detection means changes the input address signal or the activation signal as the address change detection signal. It is characterized in that a one-shot pulse having a pulse width corresponding to a waiting period from the start of the operation until the determination of the input address signal or the activation signal is generated.

The invention according to claim 9 is the same as claims 4 to
The invention according to any one of items 8 to 8 is characterized in that the control means performs the refresh within a period in which the one-shot pulse is generated. Also,
According to a tenth aspect of the present invention, in the invention according to any one of the first to ninth aspects, the control unit performs the refresh by a write enable signal that activates a write operation to the memory cell. When input within the period, in response to the write enable signal,
It is characterized in that input write data is taken into a write bus and the write data is written from the bus to the memory cell after the refresh is completed.

The invention described in claim 11 is the same as claim 1.
In the invention described in any one of 10 to 10, the control means activates self-refresh when the address transition detection signal is not generated for a predetermined time,
It is characterized in that an internal refresh request is generated at regular time intervals to perform the refresh. According to a twelfth aspect of the present invention, in the eleventh aspect of the present invention, the control means performs the refresh when the address change detection signal is generated during the refresh by the self-refresh. After that, the access to the input address signal is performed. According to a thirteenth aspect of the present invention, in the invention according to any one of the fourth to ninth aspects, the one-shot pulse is a first change point and a second change point that trigger the refresh and the access, respectively. Have a change point,
The refresh address generation means updates the refresh address signal by using the second change point as a trigger.

The invention according to claim 14 is the same as claim 1
13. The invention according to any one of 1 to 13 above, wherein a refresh control means including a circuit portion in the control means for controlling the refresh and the refresh address generation means, and a predetermined circuit in the semiconductor memory device. Voltage generating means for generating a voltage to be supplied to the refresh control means and the first mode for supplying power to both the refresh control means and the voltage generating means. Switching to any one of a second mode for supplying power and a third mode for stopping the supply of power to both the refresh control means and the voltage generation means, and the refresh control means and the refresh control means according to the switched mode. Mode switching means for controlling whether or not to supply power to the voltage generating means, respectively. It is characterized by comprising the al.

The invention according to claim 15 is the same as claim 1
In the invention described in 4, the mode switching means switches the modes in response to a request to write data predetermined for each mode to a predetermined address. According to a sixteenth aspect of the present invention, in the invention according to any one of the first to fifteenth aspects, the control means responds to an input test mode signal by input refresh request or the address. One of the internal refresh requests generated on the basis of the change detection signal is selected, and the refresh is performed according to the selected refresh request.

The invention according to claim 17 is the same as claim 1.
In the sixth aspect of the invention, the input refresh request is input through a pin that is not used during the refresh. Further, the invention according to claim 18 is characterized in that, in the invention according to any one of claims 1 to 17, the refresh address generating means updates the refresh address signal each time refresh is performed. . According to a nineteenth aspect of the present invention, in the invention according to any one of the first to eighteenth aspects, the control unit is responsive to the address change detection signal and corresponds to the refresh address signal. It is characterized in that the memory cell corresponding to the input address signal is read or written after the refresh is performed.

The invention according to claim 20 is the same as claim 1
In the invention described in any one of (1) to (18), when the write request is input, the control unit responds to the address change detection signal to refresh the memory cell corresponding to the refresh address signal. Write to the memory cell corresponding to the input address signal, and when a read request is input, the memory cell corresponding to the input address signal is read in response to the address change detection signal. The memory cell corresponding to the refresh address signal is refreshed. According to a twenty-first aspect of the present invention, in the twenty-first aspect of the invention, when the control unit has a predetermined time elapse after the input address signal changes, the input access request is a read request or a write request. It is characterized by determining which of the requests.

The invention according to claim 22 is the same as claim 1
22. A test method for testing a semiconductor memory device according to any one of items 1 to 21, wherein a step of writing a predetermined test pattern in a memory cell array composed of the plurality of memory cells; A step of prohibiting all refreshes by a refresh request, a timing of changing the input address signal and a timing of giving an input refresh request to the semiconductor memory device are set in a predetermined time relationship, and while changing the input address signal, Give input refresh request,
The method is characterized by comprising the steps of refreshing the memory cell array and determining whether the semiconductor memory device is good or defective by collating the data read from the memory cell array with the test pattern.

The invention according to claim 23 is the same as claim 2
In the invention described in 2, the method further comprises the step of varying the time relationship between the timing of the change and the timing of giving the input refresh request over a predetermined time range. In addition, claim 24
In the invention described in claim 22 or 23, the method further comprises the step of sequentially performing the refresh on all the word lines on the memory cell array while keeping the time relationship constant. I am trying. The invention of claim 25 is the same as claims 22 to 2.
In the invention described in any one of 4), when changing the input address signal, all bits of the input address signal are inverted at the same time.

The invention according to claim 26 is the same as claim 1
In the invention according to any one of the sections to 13, whether or not to operate the respective circuit before Symbol the apparatus required for refresh in the standby state is selected from among the modes of a plurality of types which are defined for each circuit mode Accordingly, when the standby state is entered, the operation control means for operating each circuit in the device required for the refreshing or for stopping the operation thereof is provided. According to a twenty-seventh aspect of the present invention, in the twenty-sixth aspect, whether or not the memory cell array including the plurality of memory cells is refreshed when the standby state is set is independently controlled. Are divided into a plurality of memory cell areas according to the mode set for each memory plate including the memory cell area and a peripheral circuit necessary for refreshing the memory cell area. ,
Each of the memory plates is operated, or the operation is stopped.

The invention according to claim 28 is the same as claim 2
7. In the invention described in 7, each of the memory plates is
Power supply means for supplying power to the memory cell area and the peripheral circuits forming the memory plate is further provided, and the operation control means is provided for each memory plate according to the mode set for each memory plate. It is characterized in that the provided power supply means is operated or the operation is stopped. In addition, claim 29
According to a twenty-seventh aspect of the present invention, in the twenty-seventh aspect of the present invention, the power source means is shared by the plurality of memory plates to supply power to the plurality of memory plates.
The operation control means includes a plurality of switch means for controlling, for each memory plate, whether to supply power from the power supply means to each of the memory plates according to the mode set for each memory plate. It is characterized by doing.

The invention according to claim 30 is the same as claim 2
The invention described in any one of 7 to 29 is characterized by comprising a program means for setting the mode for each of the memory plates in response to an input mode signal. The invention of claim 31 is the same as claim 3
In the invention described in 0, the program means specifies a memory plate having a memory cell area corresponding to the input address based on the input address, and specifies the mode specified by the input mode signal. The feature is that it is set as a mode for the memory plate.

[0045]

[0046] Also, an invention according to claim 32, wherein a control circuit for supplying an address signal to the selecting means for selecting a memory cell that requires a refresh, refresh address signal in response to a change in input address signal Is provided, and address switching means for outputting the refresh address signal to the selecting means and then outputting the input address signal to the selecting means.

The invention of claim 33 is the same as that of claim 3
In the invention described in 2 , the address switching unit continuously accesses a plurality of memory cells having the same upper predetermined bits while changing a page address composed of bits other than the upper predetermined bits of the input address signal. An address signal for doing so is output to the selecting means. The invention according to claim 34 ,
In a thirty-second or thirty-third aspect of the invention, the refresh address generating means is characterized in that the refresh address signal is generated in response to the input address signal or the activation signal.

[0048] The invention of claim 35, wherein the claim 3
In the invention described in any one of items 2 to 34, the address switching unit outputs the refresh address signal to the selecting unit by using a change of the input address signal as one trigger, and then the input address signal. Is output to the selecting means. Further, claim 3
According to a sixth aspect of the present invention, in the invention according to any one of the thirty-second to thirty-fifth aspects, the refresh address generation means activates self-refresh when the input address signal has not changed for a predetermined time, and the refresh address is kept constant. The refresh address signal is generated at time intervals.

The invention of claim 37 is the same as that of claim 3
In the invention described in 6 , the address switching means causes the input address signal to be passed to the selecting means after the refresh is performed when the input address signal changes during the refresh by the self-refresh. It is characterized by outputting. Also, the claims
A thirty- eighth aspect of the present invention is the invention according to any one of the thirty- two to thirty-seventh aspects, wherein the refresh address generating means is included at least, and the refresh control means controls the refresh, the refresh control means, and the memory. A first mode in which power is supplied to both a cell and a voltage generating means for generating a voltage to be supplied to a predetermined circuit including the selecting means, power supply to the refresh controlling means is stopped, and power is supplied to the voltage generating means. Mode control means for generating a mode switching signal for switching to any one of a second mode for supplying power and a third mode for stopping the supply of power to both the refresh control means and the voltage generation means. It is characterized by further including and.

Further, the invention according to claim 39 is the invention according to claim 3
In the invention described in 8 , the mode control means is characterized in that the mode switching signal is generated in response to a write request for writing predetermined data for each mode to a predetermined address. The invention according to claim 40 is the invention according to any one of claims 32 to 39 , which is based on an input refresh request or a change in the input address signal in response to an input test mode signal. Refresh request selecting means for selecting any of the generated internal refresh requests is further provided, and the address switching means outputs the input address signal as the refresh address signal to the selecting means in response to the selected refresh request. Alternatively, the refresh address signal is directly output to the selecting means.

The invention according to claim 41 is the invention according to claim 4
The invention described in 0 is characterized in that the input refresh request is input through a pin that is not used during the refresh. The invention according to claim 42 is characterized in that, in the invention according to any one of claims 32 to 41 , the refresh address generating means updates the refresh address signal each time the refresh is performed. There is. The invention according to claim 43 is the invention according to any one of claims 32 to 42 , wherein the address switching means is irrespective of whether a write request or a read request is input. A signal is output to the selecting means and then the input address signal is output to the selecting means.

The invention according to claim 44 is the same as claim 3
In the invention described in any one of 2 to 42, the address switching unit, when a write request is input,
In response to the address change detection signal, the refresh address signal is output to the selecting means and then the input address is output to the selecting means. When a read request is input, the address change detection signal is responded to. Then, the input address signal is output to the selecting means, and then the refresh address signal is output to the selecting means. According to a forty- fifth aspect of the invention, in the fourty- fourth aspect of the invention, when the predetermined time elapses from the time when the input address signal changes, the address switching unit determines that the input access request is a read request, It is characterized in that it is judged which of the write requests.

The invention according to claim 46 is the same as claim 3
In the invention according to any one of the terms 2-37, among the notes <br/> Riseru plural kinds modes whether operated to the standby state each time path required for refresh is defined for each circuit According to the mode selected from the above, each circuit required for the refresh is operated or stopped when the standby state is entered. In addition, claim 47
According to a 46th aspect of the present invention, in the 46th aspect of the present invention, a memory cell area in which whether or not the refresh is performed is independently controlled when the standby state is set, and a peripheral circuit required for refreshing the memory cell area. Each of the memory plates is operated according to the mode set for each memory plate consisting of
The feature is that the operation is stopped.

The invention according to claim 48 is the same as claim 4
In the invention according to 7, the power supply means provided for each memory plate is operated to supply power to the memory cell area and the peripheral circuit according to the mode set for each memory plate, or , It is characterized by stopping its operation. Also, the claims
According to a 49th aspect of the invention, in the 47th aspect of the invention, according to the mode set for each of the memory plates,
A plurality of switch means for controlling whether or not to supply power to each of the memory plates from a power supply means shared among the plurality of memory plates for supplying power to the plurality of memory plates. Is characterized by.

The invention according to claim 50 is the invention according to claim 4
The invention described in any one of 7 to 49 is characterized by comprising a program means for setting the mode for each of the memory plates in response to an input mode signal. Further, the invention of claim 51 is the same as claim 5
In the invention described in 0 , the program means specifies a memory plate having a memory cell area corresponding to the input address based on the input address, and specifies the mode specified by the input mode signal. The feature is that it is set as a mode for the memory plate.

[0056]

[0057]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the embodiments described below, and, for example, the constituent elements in these embodiments may be combined appropriately.

[First Embodiment] FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to the present embodiment. In the figure, an address Address is an access address supplied from the outside of the semiconductor memory device. The address Address includes a row address and a column address, corresponding to a memory cell array to be described later arranged in a matrix. The address buffer 1 buffers this address Address and outputs it.

In the latch 2, the latch control signal LC is "L".
While it is at the level (that is, from the time when the latch control signal LC falls to the time when it rises next), the address supplied from the address buffer 1 is output as it is as the internal address L_ADD. Further, the latch 2 takes in the address supplied from the address buffer 1 at the rising edge of the latch control signal LC and outputs the latch control signal LC.
Is held at the "H" level, and the held address is output as the internal address L_ADD.

ATD (Address Transition Detector)
Address change detection) circuit 3 uses chip select signal / CS
Address is valid (“L” level), the internal address L_ADD
If any one of these bits changes, a one-shot pulse signal is output as the address change detection signal ATD. The ATD circuit 3 also generates a one-shot pulse in the address transition detection signal ATD even when the chip select signal / CS is validated. The chip select signal / CS is a select signal that is validated when accessing the semiconductor memory device shown in FIG. The symbol "/" added to the beginning of the signal name means that it is a signal of negative logic.

Here, the chip select signal / CS will be described in more detail. The chip select signal / CS is a signal for determining selection / non-selection of a semiconductor memory device (chip), and particularly for selecting a desired semiconductor memory device in a system including a plurality of semiconductor memory devices. It is an activation signal used for. In the explanation below,
A chip select signal is used as an activation signal for determining chip selection / non-selection. However, the activation signal usable in the present invention is not limited to the chip select signal, and any signal having a function equivalent to this may be used. Any signal may be used.

Therefore, it is possible to use, for example, a chip enable signal instead of the chip select signal.
However, some so-called chip enable signals have an address latch timing control function in addition to the chip activation function like the chip enable signal in the existing pseudo SRAM. That is, as described in [Problems to be Solved by the Invention], in the existing pseudo SRAM, the chip enable signal is input every cycle like a clock signal in order to control the timing of address fetching. However, the increase in power consumption has become a problem.

On the other hand, one feature of the semiconductor memory device of the present invention is that it can operate without inputting a signal that triggers an internal operation every cycle like a clock signal. For this reason, when the chip enable signal is used as the activation signal in the present invention,
A signal that has a chip activation function and does not have an address latch timing control function will be used.

The refresh control circuit 4 incorporates an address counter (refresh counter) and a refresh timer. The refresh control circuit 4 receives the address change detection signal ATD and the write enable signal / W.
By controlling the refresh inside the semiconductor memory device using E, the refresh address and the refresh timing are automatically generated inside the semiconductor memory device, and the same refresh operation as the self-refresh in the general-purpose DRAM is realized. . Here, the address counter sequentially generates a refresh address R_ADD for refreshing the DRAM memory cell. The refresh address R_ADD has the same bit width as the row address included in the address Address.

The refresh timer measures the elapsed time from the last access request from outside the semiconductor memory device, and when the elapsed time exceeds a predetermined refresh time, the refresh timer is internally operated. This is to activate self-refresh. for that reason,
The refresh timer is configured to be reset and restart time counting each time the address transition detection signal ATD becomes valid.

In addition, the refresh control circuit 4 generates refresh control signals REFA and REFB for controlling the refresh timing. The meaning of these refresh control signals will be described later with reference to FIG. 2, and the detailed timing of these refresh control signals will be clarified in the operation description.

The multiplexer 5 (“MUX” in the drawing) has the address transition detection signal ATD at the “L” level and the refresh control signal RE according to the levels of the address transition detection signal ATD and the refresh control signal REFB described later.
If FB is at "H" level, the row address included in the internal address L_ADD (because it is complicated,
It may be called "L_ADD". ) Is selected and this is output as the address M_ADD. On the other hand, when the address transition detection signal ATD is at "H" level or the refresh control signal REFB is at "L" level, the multiplexer 5 selects the refresh address R_ADD and selects the address M_A.
Output as DD.

Next, the memory cell array 6 is a general-purpose DRA.
A memory cell array similar to that used in M, in which word lines and bit lines (or bit line pairs; the same applies hereinafter) run in the row direction and the column direction, respectively.
Similar to AM, memory cells each including one transistor and one capacitor are arranged in a matrix at the intersections of word lines and bit lines.

The row decoder 7 receives the row enable signal RE.
When address is “H” level, address M_ADD is decoded,
The word line specified by this address M_ADD is activated. When the row enable signal RE is at "L" level, the row decoder 7 does not activate any word line.

The column decoder 8 receives the internal address L_ when the column enable signal CE is at "H" level.
A column address included in ADD is decoded, and a column selection signal for selecting the bit line designated by this internal address L_ADD is generated. The column enable signal C
When E is at "L" level, the column decoder 8 does not generate a column selection signal corresponding to any bit line.

The sense amplifier / reset circuit 9 is composed of a sense amplifier, a column switch, and a precharge circuit which are not shown. Among them, the column switch connects the sense amplifier designated by the column selection signal output from the column decoder 8 and the bus WRB. The sense amplifier is activated when the sense amplifier enable signal SE is at "H" level, senses and amplifies the bit line potential connected to the memory cell specified by the address Address and outputs it to the bus WRB, or , Write the write data supplied to the bus WRB to the memory cell via the bit line. The precharge circuit is activated when the precharge enable signal PE is at "H" level, and precharges the potential of the bit line to a predetermined potential (for example, 1/2 of the power supply potential).

The I / O (input / output) buffer 10 buffers read data on the bus WRB by the output buffer if the signal is at "H" level in accordance with the level of the control signal CWO, and then the bus I / O buffer 10 outputs. To the outside of the semiconductor memory device. Further, the I / O buffer 10 has the same signal "L".
If it is at the level, the output buffer is set in a floating state and write data supplied to the bus I / O from outside the semiconductor memory device is buffered in the input buffer and sent to the bus WRB. That is, if the control signal CWO is at "H" level, reading is performed, and if it is at "L" level, writing is performed.

Next, the R / W (Read / Write) control circuit 11
Generates a control signal CWO based on the chip select signal / CS, the write enable signal / WE and the output enable signal OE. Here, in the specification of the semiconductor memory device according to the present invention, data writing (capturing) starts at the falling edge of the write enable signal / WE, and data is determined and writing (capturing) at the rising edge of the write enable signal / WE. ) Ends.
The switching timing of the control signal CWO will be described in the operation.

The latch control circuit 12 generates the above-mentioned latch control signal LC that determines the latch timing of the address Address based on the address transition detection signal ATD and the column enable signal CE. The row control circuit 13 has a refresh control signal REFA and a refresh control signal RE.
Based on FB, the address transition detection signal ATD and the write enable signal / WE, the row enable signal RE,
The sense amplifier enable signal SE, the precharge enable signal PE and the control signal CC are generated. The column control circuit 14 generates a column enable signal CE based on this control signal CC.

The boost power supply 15 is a power supply for supplying the boosted potential applied to the word line in the memory cell array 6 to the row decoder 7. The substrate voltage generating circuit 16 is a circuit for generating a substrate voltage applied to a well in which each memory cell of the memory cell array 6 is formed or a semiconductor substrate. Further, the reference voltage generation circuit 17 uses a reference voltage (for example, 1/2 = 1/2 of the power supply potential) used by the memory cell array 6, the sense amplifier in the sense amplifier / reset circuit 9, and the precharge circuit / equalize circuit.
Vcc) is generated. The use of this reference voltage is mainly of the following three types (to), but at present, the main use is to provide no dummy cell.

Reference voltage (1/2 Vcc) applied to the counter electrode of the capacitor forming the memory cell. When a dummy cell is provided, the potential read from the memory cell onto one bit line of the bit line pair and the potential read from the dummy cell onto the other bit line (1/2 V
Reference potential when the sense amplifier determines whether the data held in the memory cell is “0” / “1” from cc). Reference voltage used as a precharge / equalize voltage for a bit line pair when no dummy cell is provided. In this case, the read voltage from the memory cell appears on one bit line, and the other bit line is set to the precharge voltage (1/2 Vcc) immediately before the start of the sensing operation.

Here, the refresh control circuit 4, the boost power supply 15, the substrate voltage generating circuit 16 and the reference voltage generating circuit 17 are supplied with a power down control signal PowerDown. This power down control signal PowerDown
Is a signal for designating from outside the semiconductor memory device the mode in which the semiconductor memory device is brought into the power-down state (standby state). The refresh control circuit 4, the boost power supply 15, the substrate voltage generation circuit 16, and the reference voltage generation circuit 17 control power supply to themselves according to a power down control signal PowerDown, as described later.

In this embodiment, the memory cell itself is a DRAM.
Since it is similar to the above, it is not possible to simply stop the power supply to each circuit portion in the semiconductor memory device in the standby state unlike the SRAM. In order to retain the data in the memory cell even in the standby state, it is necessary to continue supplying power to the circuit required for the refresh operation. In other words, the semiconductor memory device of this embodiment cannot be completely compatible with the SRAM in the standby state. However, according to this embodiment, some modes in the standby state are provided for the sake of compatibility with the SRAM as much as possible, and a mode that does not exist in the existing semiconductor memory device is provided.

That is, in this embodiment, the refresh control circuit 4, the boost power supply 15, the substrate voltage generation circuit 16,
Three types of standby modes are prepared depending on which of the reference voltage generation circuits 17 is operated. In this specification, these standby modes are referred to as standby modes 1 to 3 for convenience. The standby mode 1 is a mode in which power is supplied to all four types of circuits, and the standby mode 2 is a mode in which power is supplied only to the refresh control circuit 4 out of the four types of circuits and power is supplied to the other three types of circuits. The standby mode 3 is a mode in which power supply to all four types of circuits is stopped.

From the above, as a circuit for supplying the power down control signal PowerDown, for example, the first power supply line for supplying power to the refresh control circuit 4, the boost power supply 15, the substrate A second power supply line for supplying power to the voltage generation circuit 16 and the reference voltage generation circuit 17 may be used.

Next, each standby mode will be described in more detail. Standby mode 1 is a power supply mode equivalent to a normal DRAM and has the largest current consumption among the three types of standby modes. However, in this case, power is still supplied to all circuits necessary for self-refreshing the memory cells. Therefore, the data in the memory cell immediately before the transition to the standby state is held, and the time until the semiconductor memory device transitions from the standby state to the active state is the shortest among the three types of standby modes. In order to set the standby mode 1, the first power supply line and the second power supply line
It suffices to supply power to both of the power supply lines.

On the other hand, in standby mode 2, power is not supplied to the circuits required for self refresh. Therefore, although the data in the memory cell cannot be held in the standby state, the current consumption can be reduced as much as that in the standby mode 1. In other words, this standby mode is a concept change from the existing concept of holding data in the standby state. After the transition from the standby state to the active state, the entire memory cell array can be written. The assumption is that it only needs to be in a state. Therefore, at the time of returning to the active state, the data in the memory cell at the time of shifting to the standby state is not retained. Therefore, the standby mode 2 and the standby mode 3 described below are modes suitable when the semiconductor memory device is used as a buffer. To set the standby mode 2, power is not supplied to the first power supply line and power supply to the refresh control circuit 4 is stopped.

On the other hand, in the standby mode 3, it is necessary to raise the boost voltage, the substrate voltage, and the reference voltage, so the time from the standby state to the active state is the longest among the three standby modes. Therefore, the consumption current in the standby mode can be minimized. Note that in any of the standby modes 1 to 3, it is sufficient to supply power only to necessary circuits for circuits other than the four types described above. For example, if you just do self-refresh,
Address buffer 1, latch 2, ATD circuit 3, column decoder 8, I / O buffer 10, R / W control circuit 1
1, the latch control circuit 12, the column control circuit 14, etc. are not used, so the power supply may be stopped. To set the standby mode 3, power is not supplied to either the first power supply line or the second power supply line, and the refresh control circuit 4, the boost power supply 15, and the substrate voltage generation circuit 16 are provided. The power supply to the reference voltage generation circuit 17 is all stopped.

By providing the standby mode as described above, depending on the equipment to which the semiconductor memory device is applied and the usage environment thereof, the necessity of holding data in the standby state, the return time to the active state, and the current consumption amount It becomes possible to finely control the above from the outside of the semiconductor memory device. Note that the power-down control signal PowerDown is not an essential function and may be omitted. By doing so, it is possible to completely maintain compatibility between general-purpose SRAM and I / O pins. Become.

Next, referring to FIG. 2, the ATD shown in FIG.
Detailed circuit configurations of the circuit 3, the latch control circuit 12, the row control circuit 13, and the column control circuit 14 will be described. In FIG. 2, the same components and signal names as those shown in FIG. 1 are designated by the same reference numerals.

First, the ATD circuit 3 will be described. The inverter 31 inverts the chip select signal / CS to generate the chip select signal CS. Inverter 32,
Delay circuit 33 and NAND gate (NAND) 34
Generates a negative one-shot pulse having the same width as the delay time given by the inverter 32 and the delay circuit 33 from the rise of the chip select signal CS.

Next, the internal address L_ADDi is a specific 1 bit of the internal address L_ADD shown in FIG. The NAND gate 35 supplies the internal address L_ADDi to the circuit including the inverter 37, the delay circuit 38 and the NAND gate 39 through the inverter 36 when the chip select signal CS is valid. This allows the internal address L_AD
Inverter 37 and delay circuit 3 from the rise of Di
A negative one-shot pulse having the same width as the delay time given by 8 is generated. Similarly, the inverter 40,
The circuit composed of the delay circuit 41 and the NAND gate 42 operates from the fall of the internal address L_ADDi to the inverter 4
0 and a negative one-shot pulse having the same width as the delay time given by the delay circuit 41 is generated.

The NAND gate 43 and the inverter 44 are
Rise of chip select signal CS, internal address L_
It outputs a positive one-shot pulse obtained by synthesizing one-shot pulses generated by either rising or falling of ADDi. The delay circuit 45, the NOR gate 46 and the inverter 47 are for extending the pulse width of each one-shot pulse output from the inverter 44 by the delay time given by the delay circuit 45. Then, the above circuit blocks are provided by the number of bits of the internal address L_ADD. The OR gate 48 synthesizes the one-shot pulses generated for all the bits of the internal address L_ADDi and outputs this as the address transition detection signal ATD.

Thus, in this embodiment, the internal address
One-shot pulse is generated from the change of each bit of L_ADDi, and the one-shot pulse is ORed and combined. The reason for doing this is as follows. Now suppose
When a one-shot pulse is generated in the address transition detection signal ATD every time any bit of the address Address changes, a plurality of address transition detection signals are generated when the address Address includes a skew. I will end up.

Then, as described in [Problems to be Solved by the Invention], a plurality of word lines are simultaneously activated by these address transition detection signals ATD. Therefore, writing is performed to a plurality of memory cells, or reading from a plurality of memory cells is performed at the same time and rewriting is performed, and as a result, data in the memory cells is destroyed.

Therefore, in this embodiment, the address Address
One bit of each of the bits that has changed first is first generated by a one-shot pulse, and if there is a change in other bits during the period when this first one-shot pulse is generated, it has already occurred. The one-shot pulse generated and the newly-generated one-shot pulse are combined. By doing so, even if the address Address includes a skew, the pulse width of the one-shot pulse is increased by the skew included in the address Address, and a plurality of one-shot pulses are generated by one address change. It will not be lost. Therefore, there is no possibility that the above-mentioned problem such as the destruction of the data in the memory cell will occur.

The conditions for making the above are delay circuits 33, 38, 41, 45 so that the skew included in the address Address falls within the pulse width range of the address transition detection signal ATD. It is sufficient to determine the delay time such as. Incidentally, when the skew is large, it is necessary to widen the pulse width of the one-shot pulse generated. Therefore, there is a concern that the fall of the address transition detection signal ATD will be delayed by the amount of skew and the access time will increase. However, general-purpose S
Since the access time is a value based on the time when the address Address is fixed in the specifications of the RAM, as long as the access time from the last changed bit of each bit of the address Address is guaranteed, it operates. It won't be late.

As will be described later in the description of the operation, refresh is performed while the one-shot pulse of the address transition detection signal ATD is being generated, so the pulse width of this one-shot signal is one word line refresh. It is desirable to set more than the time required to complete. Therefore, the delay times of the delay circuits 33, 38, 41, 45 may be determined so that the condition considering the refresh is satisfied in addition to the condition considering the skew described above. Further, if the one-shot pulse of the address transition detection signal ATD is made to fall immediately after the refresh is completed, the read / write access to the address Address is subsequently performed.

Explaining the row control circuit 13, the inverter 30 inverts the address transition detection signal ATD to generate the address transition detection signal / ATD. Further, the delay circuit 49, the NOR gate 50, the inverter 5
1, a circuit including a delay circuit 52, a NAND gate 53, and a NAND gate 54 has a write enable signal / WE.
Alternatively, based on the address change detection signal ATD, a row enable signal RE, a sense amplifier enable signal SE, a column enable signal CE, a precharge enable signal PE, and a latch control signal LC required for access requested from outside the semiconductor memory device. Is a circuit for generating.

Among them, the circuit composed of the delay circuit 49, the NOR gate 50, and the inverter 51 has a write enable signal before the address change detection signal ATD becomes "H" level due to the change of the internal address L_ADDi or the chip select signal / CS. Even when / WE is at "L" level, pulses are sequentially generated in the row enable signal RE, the sense amplifier enable signal SE, the column enable signal CE, the precharge enable signal PE, and the latch control signal LC. This is to ensure that there are no defects.

To this end, the address transition detection signal AT
When D rises, the inverter 30 moves to the NAND gate 54
After the “L” level is supplied to the NAND gate 54, the write enable signal / WE may be supplied to the NAND gate 54 through the NOR gate 50, the inverter 51, and the NAND gate 53. Therefore, write enable signal / W
The signal obtained by delaying E by the delay circuit 49 and the write enable signal / WE are logically ORed by the NOR gate 50 and the inverter 51, and the delay time of the delay circuit 49 is adjusted to such an extent that the above-mentioned trouble does not occur. The fall of WE is delayed. In the circuit described above, the output of the inverter 51 also rises in response to the rising edge of the write enable signal / WE.
It is possible to immediately shift to the reset operation when is at the "H" level.

Next, the delay circuit 52 and the NAND gate 5
3, the circuit composed of the NAND gate 54 detects address change when not writing (that is, when the write enable signal / WE is at “H” level and the inverter 51 supplies “H” level to the NAND gate 53). A one-shot pulse is generated as the row enable signal RE from the falling edge of the signal ATD. In addition, when the address change detection signal ATD is at the "L" level, the circuit enables the row enable signal R
It also functions to maintain E, the sense amplifier enable signal SE, the column enable signal CE, the precharge enable signal PE, and the latch control signal LC at "H" level. That is, when the address transition detection signal ATD is at "L" level, the inverter 30 supplies the "H" level to the NAND gate 53 and the NAND gate 54. Therefore, if the write enable signal / WE output from the inverter 51 at this time is at "L" level,
NAND gate 53, NAND gate 54, NAND gate 6
Through 5, the row enable signal RE remains at "H" level.

The output of the NAND gate 54 is delayed by the inverters 55 to 58 and then output as the control signal CC. The control signal CC is further delayed by the inverters 59 to 61 forming the column control circuit 14 to become the column enable signal CE. Also, the row control circuit 1
3, a circuit including an inverter 62, a delay circuit 63, and a NAND gate 64 is a circuit for generating a row enable signal RE, a sense amplifier enable signal SE, and a precharge enable signal PE required for refreshing. That is, this circuit is a negative one-shot pulse having a pulse width corresponding to the delay time given by the inverter 62 and the delay circuit 63 from the rising of the address transition detection signal ATD when the refresh control signal REFA is at the “H” level. To generate. Then, the NAND gate 65 receives the refresh control signal REF.
The outputs of the B, NAND gate 54 and NAND gate 64 are combined and output as a row enable signal RE.

The refresh control signal REFA is a signal for controlling whether or not refresh is performed in association with an access request from the outside of the semiconductor memory device. That is, when the signal is at "H" level, a one-shot pulse is generated in the row enable signal RE at the rising edge of the address transition detection signal ATD generated by the access request, and refresh is activated. On the other hand, if the signal is at "L" level, the address transition detection signal ATD
Even if a one-shot pulse is generated in the row enable signal RE, no one-shot pulse is generated in the row enable signal RE.

In this embodiment, the refresh operation triggered by the generation of the address transition detection signal ATD will be described based on the following implementation. That is, in the present embodiment, when the refresh operation associated with reading or writing is continuous, the entire memory cell is refreshed by continuously performing the refresh in each of these memory cycles. Then, when all the memory cells have been refreshed, the refresh is temporarily disabled. After that, when it approaches a limit state (cell hold limit) in which the data of the memory cell can be held, this is detected, and the state is shifted to the state where the refresh is continuously performed in successive memory cycles.

When the refresh control signal REFA falls, the refresh for one refresh cycle is completed by the refresh due to the access request from the outside, but there is still some time before the refresh of the next refresh cycle is activated. Alternatively, the self-refresh is activated, so that it is not necessary to perform the refresh due to the access request from the outside until the completion of the self-refresh.

Here, in order to generate the refresh control signal REFA, a latch circuit for holding the refresh control signal REFA is provided inside the refresh control circuit 4.
A configuration in which set / reset of the latch circuit is controlled by the address change detection signal ATD and the output signal of the refresh timer can be considered. Specifically, a refresh timer is used to generate a timing slightly before the cell hold limit (refresh operation is required), and a set signal for the latch circuit is generated in the refresh control circuit 4 based on the output signal. Set the latch circuit,
The "H" level is output to the refresh control signal REFA. The timing of generating the set signal is determined by using the maximum cycle time as a guide. After that, the row control circuit 13 causes the address change detection signal AT
D or the refresh control signal REFB generated based on the refresh control signal REFA is used as a trigger to refresh the memory cells in units of word lines. Then, when the refresh operation of all the memory cells is performed, a reset signal of the latch circuit is generated inside the refresh control circuit 4 to reset the latch circuit, and "L" level is output to the refresh control signal REFA.

The latch circuit may be reset in a refresh cycle for refreshing the last word line in accordance with the end time of the refresh operation. Alternatively, when the refresh operation is completed, the row control circuit 13 generates the refresh operation completion signal, and when the refresh control circuit 4 receives this refresh operation completion signal in the refresh cycle for the last word line, the latch circuit. May be reset. However, in consideration of the case of FIG. 7 which will be described later, the address transition detection signal ATD is generated from the time when the refresh control signal REFA is raised to the time when the first refresh after this rising is completed. (See FIG. 8) or write enable signal / W
Unless E is input (see FIGS. 10 and 11), the latch circuit is reset after the completion of this first refresh.

On the other hand, the refresh control signal REFB is a signal for self refresh. That is, by applying a negative one-shot pulse to the refresh control signal REFB, the NAND gate 54 and the NAND gate 64 are provided.
It is possible to forcibly generate a one-shot pulse in the row enable signal RE to activate self-refresh regardless of the output of the.

Here, in order to generate the refresh control signal REFB, a delay circuit for delaying the refresh control signal REFA and a pulse generating circuit for generating a negative one-shot pulse are provided inside the refresh control circuit 4 to generate a pulse. A configuration is conceivable in which the timing for generating a negative one-shot pulse from the circuit is controlled by the refresh control signal REFA delayed by the delay circuit and the address transition detection signal ATD.

Normally, the refresh control signal REFB is "
When the refresh control signal REFA is raised to "H" level in this state, the rising edge of the refresh control signal REFA is delayed by a delay circuit for a predetermined time, and during this delay When the address transition detection signal ATD is not generated, the pulse generation circuit is activated at the rising edge of the delayed refresh control signal REFA, and the refresh control signal REFB outputs a negative one-shot pulse.

The above-mentioned delay of the predetermined time is for measuring the time until the limit time required for refreshing the memory cell is reached because the trigger for generating the address transition detection signal ATD is not given from the outside. is there. Further, as will be described later (see FIG. 11), when the write enable signal / WE falls during the above delay, self-refreshing is performed after writing, so the time required for this writing is also taken into consideration. Then, the timing of raising the refresh control signal REFA and the delay of the predetermined time are set.

The present invention is not limited to the above-described embodiment of the refresh operation. For example, the memory cells are arranged in a predetermined cycle every predetermined number of word lines (that is, every one word line or every plural word lines). It may be in a form of refreshing with. In this case, the circuit configuration for generating the refresh control signal REFB may be the same as that described above, but the circuit configuration for generating the refresh control signal REFA is as follows, for example. First, the refresh timer generates a trigger signal for activating refresh at a constant cycle. Next, similarly to the above case, a latch circuit is provided inside the refresh control circuit 4, and based on the trigger signal output from the refresh timer, a set signal generated at a timing slightly before the refresh operation is required is performed. The latch circuit is set to set the refresh control signal REFA to "H" level.
Also in this case, the timing of setting the latch circuit is determined by using the maximum value of the cycle time as a guide.

Then, at the timing when the row control circuit 13 receiving the address transition detection signal ATD or the refresh control signal REFB completes the refresh operation for the memory cell, the refresh control circuit 4 operates the latch circuit by the generated reset signal. It is reset and the refresh control signal REFA is set to "L" level. In addition,
In this case, the latch circuit may be reset at a timing delayed by a certain time from the time when the latch circuit is set. Alternatively, the row control circuit 13 may generate a refresh operation completion signal when the refresh operation is completed, and the refresh control circuit 4 may reset the latch circuit when the refresh operation completion signal is received. By the way, in this embodiment, when the refresh operation triggered by the address transition detection signal ATD is completed, the refresh control signal REF is returned in each memory cycle.
A will fall. The signal waveform of the refresh control signal REFA becomes the same as the signal waveform in the refresh cycle shown in FIG. 4, for example.

Next, the inverters 66 to 69 delay the row enable signal RE to generate the sense amplifier enable signal SE. Further, the inverters 70 and 71 further delay the output of the inverter 68 to generate a negative one-shot pulse in which the row enable signal RE is delayed by five stages of inverters. The circuit including the inverter 72, the delay circuit 73, the NAND gate 74, and the inverter 75 outputs the row enable signal RE to the inverter 5
A one-shot pulse having a pulse width corresponding to the delay time given by the inverter 72 and the delay circuit 73 is generated from the rising edge of the signal delayed by one stage, and this is output as the precharge enable signal PE. That is, the one-shot pulse of the precharge enable signal PE is generated in response to the fall of the row enable signal RE.

Next, in the latch control circuit 12, the circuit consisting of the inverter 76, the inverter 77, the delay circuit 78, the NAND gate 79 and the inverter 80, the inverter 77 from the fall of the column enable signal CE.
And a positive one-shot pulse having a width corresponding to the delay time of the delay circuit 78 is generated. The one-shot pulse is supplied from the inverter 80 to the n-channel transistor 81 to connect the latch control signal LC to the ground potential and set it to the “L” level. Further, the inverters 82 and 83 connected in a loop form a latch 84 for holding the latch control signal LC, and when the transistor 81 is turned on, the value held by the latch 84 is reset to "0". It

In addition, the inverter 85, the inverter 86,
Delay circuit 87, NAND gate 88 and inverter 8
The circuit composed of 9 generates a positive one-shot pulse having a width corresponding to the delay time of the inverter 86 and the delay circuit 87 from the fall of the address transition detection signal ATD. The one-shot pulse is supplied from the inverter 89 to the n-channel transistor 90, thereby connecting the input terminal of the inverter 82 to the ground potential. As a result, the latch control signal LC becomes "H" level and the value held by the latch 84 is set to "1". That is, the latch control signal LC is the address transition detection signal ATD.
From the fall of the column enable signal to the time of the fall of the column enable signal CE.

Next, the operation of the semiconductor memory device having the above structure will be sequentially described by dividing it into cases. <Reading with Refresh> First, with reference to the timing chart of FIG. 3, an operation in the case where refreshing is performed with reading by sequentially changing read addresses will be described. Note that FIG. 3 shows the timing when the refresh operation triggered by the generation of the address transition detection signal ATD is continuously performed in each memory cycle. Therefore, the refresh control signals REFA, RE
FBs are all fixed at "H" level, and these signals are not shown in FIG. Further, in this case, since the reading is performed, the write enable signal / WE is "
It remains at the "H" level. Furthermore, "Rx_Wo" shown in FIG.
"rd" is the word line corresponding to the refresh address R_ADD, and "Ax_Word" is the word line corresponding to the address Address. Also, in the figure, the value of the refresh address R_ADD is "R" before the value shown in FIG.
It is assumed to be 1 ".

First, at time t1, the address Address
Starts changing from the previous value to "A1" and the chip select signal / CS is validated. At this time,
As will be apparent from the description below, the latch control signal LC is at "L" level. Therefore, the address Addres
s is buffered by the address buffer 1 and passes through the latch 2 through to become the internal address L_ADD and AT
It is supplied to the D circuit 3. However, since the address Address may include skew, general-purpose SRAM
As in the case of, the value of the address Address is not always fixed at this point.

Therefore, the address cannot be taken into the latch 2 at the time t1, but after that, the value is "A" until the latch control signal LC becomes "H" level.
Since it is set to 1 ", the latch 2 is loaded at that time. Therefore, in the present embodiment, the address Ad supplied from the outside of the semiconductor memory device is used.
In the general-purpose SRAM, the standby period in which the internal operation is not performed is effectively used by dedicating the standby period in which the value of dress has not been fixed.

Next, address Address (= internal address L
_ADD) changes, so that at time t2, the ATD circuit 3 generates a one-shot pulse in the address transition detection signal ATD. When the address transition detection signal ATD rises, the multiplexer 5 refreshes the refresh address R_ADD.
The side is selected, and the value of the address M_ADD becomes "R1" at time t3. Further, the address change detection signal AT
The rise of D causes the row control circuit 13 to move to time t4.
Therefore, the one-shot pulse is generated in the row enable signal RE.

Then, since the row enable signal RE rises, the row decoder 7 decodes the value "R1" of the address M_ADD, and at time t5, the word line Rx_W.
Activates ord. As a result, in the memory cell array 6, the data held in the memory cells connected to the word line Rx_Word will appear as the potential on the bit line. on the other hand,
Since the one-shot pulse is generated in the row enable signal RE, the one-shot pulse is also generated in the sense amplifier enable signal SE at time t6. As a result, the sense amplifier in the sense amplifier / reset circuit 9 is activated, and each memory cell connected to the word line Rx_Word is refreshed. The refresh itself is the same as that performed in the DRAM and is a well-known technical matter, and therefore it will not be described in detail here.

Thereafter, at time t7, the row enable signal R
When the one-shot pulse generated at E falls, the row decoder 7 deactivates the word line Rx_Word, so that the word line Rx_Word is deactivated at time t8. At time t9, the row control circuit 13 causes the sense amplifier enable signal SE to fall in response to the fall of the row enable signal RE at the previous time t7. For this reason, the sense amplifiers in the sense amplifier / reset circuit 9 that have finished refreshing are deactivated. Also, the row control circuit 1
3 receives the fall of the row enable signal RE and generates a one-shot pulse as the precharge enable signal PE at time t10.

As a result, the precharge circuit in the sense amplifier / reset circuit 9 precharges the bit line in preparation for the next access. Since it is not necessary to output the data of the memory cell to the outside of the semiconductor memory device in the refresh process, unlike the case of reading, even if a one-shot pulse is generated in the row enable signal RE, the column enable signal CE is generated. Does not generate a one-shot pulse. Therefore, the column decoder 8 keeps all the column selection signals in the inactive state,
As shown in the figure, for example, the column selection signal Yj (Ax) remains at "L" level.

Next, at time t11, when the one-shot pulse of the address transition detection signal ATD falls, the output enable signal OE becomes valid although it is not shown in FIG.
Therefore, the R / W control circuit 11 sets the control signal CWO to the “H” level in preparation for reading from the memory cell. The I / O buffer 10 also sends the data output from the sense amplifier / reset circuit 9 to the bus I / O via the bus WRB. However, at this time, the data on the bus WRB has not been decided yet. Further, in response to the fall of the address transition detection signal ATD, the refresh control circuit 4 updates the refresh address R_ADD at the time t12 and sets its value to "R1 + 1".
To

Although it has been assumed that the value of the refresh address R_ADD is "R1", this value is also set at the time of reset at the falling edge of the address transition detection signal ATD as described above. The data has been sequentially updated from the data “0”. Further, upon receiving the trailing edge of the address transition detection signal ATD, the multiplexer 5 selects the internal address L_ADD side at the same time t12. At this point, the address as described above
Since the value of Address is fixed, the value "A1" is output as the address M_ADD.

Next, at time t13, the previous time t7
The one-shot pulse of the precharge enable signal PE falls in response to the fall of the row enable signal RE in the above, and the precharge circuit in the sense amplifier / reset circuit 9 ends the precharge. on the other hand,
In response to the fall of the address transition detection signal ATD at the time t11, the latch control circuit 12 sets the time t14.
Then, the latch control signal LC is raised. for that reason,
After that, even if the address Address changes, the latch 2 holds the value of the internal address L_ADD (and therefore the address M_ADD) until the latch control signal LC falls again.

Similarly, the address transition detection signal ATD
The row control circuit 13 receives the falling edge of
Then, a one-shot pulse is generated in the row enable signal RE. As a result, the row decoder 7 activates the word line Ax_Word corresponding to the address “A1” at time t16 so that the data held in the memory cell connected to the word line appears as the potential on the bit line. Become. Next, in response to the rise of the row enable signal RE, the row control circuit 13 generates a one-shot pulse in the sense amplifier enable signal SE at time t17. Therefore, the sense amplifier in the sense amplifier / reset circuit 9 senses the data of each memory cell connected to the word line Ax_Word and sets the potential on the bit line to “0” /
"1" logic level (that is, ground potential or power supply potential)
Amplify up to.

Further, the row control circuit 13 generates a one-shot pulse for the control signal CC and outputs it to the column control circuit 14 so as to correspond to the one-shot pulse of the row enable signal RE. The column control circuit 14 controls the control signal C.
Based on C, a one-shot pulse is generated in the column enable signal CE at time t18. When the column enable signal CE becomes "H" level in this way, the column decoder 8 decodes the column address included in the internal address L_ADD, and at time t19, the column select signal [Yj (shown in FIG. 3) corresponding to the column address. Ax)], a one-shot pulse is generated. As a result, the sense amplifier
Of the sense amplifiers in the reset circuit 9, the output of the sense amplifier corresponding to the column address is selected and the bus WR is selected.
Connected to B.

Next, at time t20, the row control circuit 1
3 causes the row enable signal RE to fall, so that the row decoder 7 deactivates the word line AX_Word at time t21. At time t22, the sense result of the previously selected sense amplifier appears on the bus WRB. At the same time, in response to the fall of the row enable signal RE earlier, the row control circuit 13 lowers the sense amplifier enable signal SE and ends the sense operation by the sense amplifier in the sense amplifier / reset circuit 9. Let

Further, the row control circuit 13 outputs the control signal C in response to the fall of the row enable signal RE first.
When C is dropped, the column control circuit 14 drops the column enable signal CE. Therefore, the column decoder 8 receives the column selection signal [Yj (A in the figure] at time t23.
x)] is invalidated, the sense amplifier in the selected sense amplifier / reset circuit 9 and the bus WRB are disconnected. At approximately the same time, the I / O buffer 10 outputs the data Dout (A1) of the memory cell read onto the bus WRB to the outside of the semiconductor memory device via the bus I / O.

Next, at time t24, the row control circuit 13 raises the precharge enable signal PE in response to the fall of the row enable signal RE first, and again prepares the bit line in preparation for the next access. Precharge. At the same time, the latch control circuit 12 sets the latch control signal LC to the “L” level in response to the fall of the column enable signal CE. Next, time t2
At 5, the row control circuit 13 causes the precharge enable signal PE to fall at time t25 so as to correspond to the fall of the row enable signal RE at time t20. Therefore, the precharge circuit in the sense amplifier / reset circuit 9 ends the precharge of the bit line.

The operation thereafter is from time t1 to t2 described above.
This is exactly the same as the operation in 5, and the cycle operation with the time Tcycle as a unit is repeatedly performed. That is, when "A2" is given as the address Address, the address change detection signal AT is generated in response to the change in the address Address.
A one-shot pulse is output to D and the address "R1 +
After "1" is refreshed, the refresh address is updated to "R1 + 2", the memory cell corresponding to the address "A2" is read, and the data Dout (A2) is output to the outside through the bus I / O. To be done.

After that, "A3" is set as the address Address.
Is given, a one-shot pulse is output as the address transition detection signal ATD corresponding to the change of the address Address, the address “R1 + 2” is refreshed, and then the refresh address is updated to “R1 + 3”. The memory cell corresponding to the address "A3" is read and the data Dout (A3) is transferred to the bus I / O.
Is output to the outside through.

As described above, in the present embodiment, the address Ad
When the dress changes, the refresh address determined by the internal address counter is refreshed first and then the address Address is normally accessed. This is because the case of writing, which will be described later, is taken into consideration. That is, in the asynchronous general-purpose SRAM, the write enable signal / WE
Becomes effective asynchronously after the change of the address Address.

Therefore, according to the first conventional example and the second conventional example, the structure in which the normal access is processed and then the refresh is performed, the write enable signal / WE is validated at an early timing. If so, there is no particular problem because the refresh is started after the writing is completed. However, when the write enable signal / WE is activated with a further delay, the write operation and the refresh operation may overlap. Therefore, in such a case, writing must be delayed until the refresh is completed. However, doing so complicates the timing control, increases the circuit scale, and makes the logic design so difficult. Therefore, in order to complete the refresh and the writing within the predetermined time Tcycle, the refresh should be performed before the writing, which can reduce the circuit scale and the logic design itself.

<Reading without Refreshing> Next, an example of operation in the case of controlling refreshing by the refresh timer in the refresh control circuit 4 is shown in the timing chart of FIG. In the figure, the address change detection signal A
The timing of switching from the state where the refresh operation triggered by the occurrence of TD is continuously performed in each memory cycle to the state where such refresh operation is not performed is shown. Therefore, in FIG. 3, the refresh control signal REFA remains at the “H” level, while
In FIG. 4, the latch circuit in the refresh control circuit 4 is reset and the refresh control signal REFA falls during the time t12 to t14 when the refresh for one refresh cycle is completed. Note that the refresh for one refresh cycle means refreshing once for all word lines. Incidentally, the refresh control signal REFB is kept at "H" level as in the case of FIG.

Although it depends on the structure and capacity of the memory cell array, the refresh for one refresh cycle is several meters.
It may be performed within a predetermined time of about s to several tens of ms, and it is not always necessary to refresh every time the address Address changes. Therefore, as shown in FIG. 3, if refresh for one refresh cycle is performed by performing refresh with external access, refresh control is performed until the refresh of the next refresh cycle is started. The signal REFA is lowered to stop the refresh.
By doing so, extra refresh is not performed and power consumption can be reduced.

As can be seen from the above, FIG. 4 shows the timing waveforms before and after the refresh for one refresh cycle is completed by the refresh for the address "R1". When the refresh control signal REFA goes to “L” level, the row control circuit 13 causes the address transition detection signal A
Even if TD rises, the one-shot pulse is not generated in the row enable signal RE. Therefore, the row control circuit 13 does not generate the sense amplifier enable signal SE and the precharge enable signal PE corresponding to the row enable signal RE.

Also, the row decoder 7 uses the word line Rx_Word.
Will not be activated, so in the end, the word line Rx_W
Refresh for ord will no longer be performed. In addition, the address counter in the refresh control circuit 4 stops its counting operation when the refresh control signal REFA goes to the “L” level. Therefore, the value of the refresh address R_ADD is the value “R” updated at the time t12.
1 + 1 "remains. Also, the value of the address M_ADD also remains" R1 + 1 "when the refresh address R_ADD side is selected. After that, when the refresh of the next refresh cycle is started, the refresh is performed. The control circuit 4 causes the refresh control signal RE
Since FA is returned to "H" level, the operation shown in FIG. 3 is performed again.

The refresh counter is not reset when the refresh operation is restarted,
The increment operation is performed on the value held in the refresh counter until then. That is, for example, even if the self-refresh operation is interrupted in the middle of a refresh cycle (that is, a cycle of refreshing all word lines), the refresh counter is not reset, and the next refresh (refresh accompanying normal access for reading or writing, It may be self-refresh.) When the operation is restarted,
The value remaining in the refresh counter is incremented.

<Write with Refresh> Next, with reference to the timing chart shown in FIG. 5, the operation in the case of refresh with write will be described. In this case as well, as in the case of FIG. 3, since the refresh control signals REFA and REFB are both fixed to the “H” level, these signals are not particularly shown in FIG. Further, FIG. 5 shows a case where writing is performed instead of reading shown in FIG. 3, and is based on the operation shown in FIG. Therefore, at time t31 shown in FIG.
The operation from t38 to t38 is the same as the operation from time t1 to t25 shown in FIG. 3 except for the following points.

As described above, the write enable signal / WE is asynchronously input in the memory cycle regardless of the change of the address Address. Therefore, here, at time t32 after the refresh is completed, “Din (A1)” is supplied to the write data to be loaded on the bus I / O, and the write enable signal / WE falls at time t33. Suppose. Then, when a negative pulse is input to the write enable signal / WE and it falls at time t33, the row control circuit 13 delays and inverts the write enable signal / WE and outputs it as a row enable signal RE.

In this case, however, the one-shot pulse is generated in the row enable signal RE even at the falling edge of the address transition detection signal ATD as in FIG. Will be done. When the one-shot pulse is generated in the row enable signal RE in this manner, the word line "Ax_Word" corresponding to the address "A1" is activated as in the case of FIG. At the same time, the sense amplifier enable signal SE and the column enable signal C
One-shot pulses are sequentially generated for E, the column selection signal Yj (Ax), and the precharge enable signal PE.

On the other hand, when the write enable signal / WE becomes valid, the R / W control circuit 11 becomes time t3.
At 4, the control signal CWO falls. As a result, the I / O buffer 10 transfers the write data on the bus I / O to the bus WR.
The data is sent to the B side, and at time t35, the data on the bus WRB changes. After that, at time t36, when the column selection signal Yj (Ax) becomes the “H” level, writing is performed to the memory cell specified by the address Address. After the writing is completed, the bit line is precharged as in the previous case.

After that, at time t37, when the write enable signal / WE rises, the write data is determined, and then the row control circuit 13 causes the row enable signal R to rise.
Turn down E. Further, when the row enable signal RE falls, the address transition detection signal AT in FIG.
The sense amplifier enable signal SE, the column enable signal CE, the column select signal Yj (Ax), and the precharge enable signal PE sequentially fall by time t38, as in the case where D falls. Further, the R / W control circuit 11 raises the control signal CWO at time t39 in response to the rise of the write enable signal / WE at the previous time t37.

After this, reading from the address "A2" is carried out. This operation is performed by the address "A2" described in FIG.
This is exactly the same as when reading from 2 ". Following this reading, writing to address" A3 "is performed. In this case, times t41 to t48.
The operation in is also in accordance with the writing to the address "A1" just described. However, in this case, the write enable signal / WE is input at a timing earlier than when writing to the address "A1". That is, in this case, the write enable signal / WE falls at the timing of refreshing, and some operations differ from the above-described writing.

That is, in this case, the write enable signal / WE falls at the time t42 during refreshing, and at the time t43, the write data "Din (A3)" is supplied onto the bus I / O. Then R / W
The control circuit 11 causes the control signal CWO to fall at time t44 in response to the fall of the write enable signal / WE. As a result, at time t45, the data “Din
(A3) "is transmitted from the I / O buffer 10 onto the bus WRB. At this point, the word line Ax_Word,
Column enable signal CE, column select signal Yj (A
Since x) is not activated, no data is written in the memory cell.

Of course, the semiconductor memory device of this embodiment is also similar to the general-purpose SRAM in that the write enable signal / W is used.
The specification defines the period during which write data can be taken in after E is input. Therefore, even if the write data is taken in at the time of actually writing to the memory cell after the refresh is completed, the value of the write data may not be guaranteed at that time. Therefore, in the present embodiment, the write data is fetched onto the bus WRB while the write enable signal / WE is valid during the refresh, and after the refresh is completed, the bus WRB outputs the write data to the memory cell at the address Address. Write.

That is, since the write data on the bus WRB is at the logic level of "0" / "1" (that is, the ground potential or the power supply potential), the word line Ax_Wor is added after this.
By sequentially activating d, the sense amplifier enable signal SE, the column enable signal CE, and the column selection signal Yj (Ax), writing can be performed from the bus WRB to the memory cell. Then, after this, the address "A1"
Is similar to the case of writing to the row enable signal R from the fall of the address transition detection signal ATD.
If the one-shot pulse of E is generated, the address "A
Writing to 3 "and subsequent bit line precharge are performed.

In this process, the write enable signal / WE rises at time t46, and in response thereto, the R / W control circuit 11 raises the control signal CWO at time t47. At the time when the write enable signal / WE falls at time t42, the address change detection signal ATD is already at the “H” level, so the row enable signal RE is not immediately generated and the address change detection signal ATD is not immediately generated. After the ATD goes to "L" level, it is delayed in the row control circuit 13 and output as a row enable signal RE. In this case, however, as in the case of writing the address "A1", a one-shot pulse is generated in the row enable signal RE even at the falling edge of the address transition detection signal ATD, so that a combination of the two is output as the row enable signal RE. Will be done.

<Write without Refresh> Next, as an example of the operation of controlling the refresh by the refresh timer in the refresh control circuit 4, the case of writing is shown in the timing chart of FIG. The difference between FIG. 5 and FIG. 5 is exactly the same as the difference between FIG. 3 and FIG. That is, in FIG. 6, the refresh control signal REFA
Is dropped after the refresh is completed, the refresh address R_ADD is not updated from "R1 + 1" in FIG. 6, and the refresh address "R" is shown in FIG.
It is different from the case of FIG. 5 that refresh is not performed for 1 + 1 ”and“ R1 + 2 ”.

<Self-Refresh> Next, an operation will be described in which an access request from the outside of the semiconductor memory device is not given for a predetermined time (hereinafter referred to as “refresh time”) and self-refresh is performed by the refresh timer. This "predetermined time"
May be set based on the data retention characteristics (for example, data retention time) of the memory cell. As described above, in the present embodiment, when an address change occurs due to an access request from the outside, refresh is performed before processing the access request. However, since it is possible that an access request from the outside will not occur for a long time, the data in the memory cell array 6 cannot be held only by refreshing when the access request is made. Therefore, in the present embodiment, the refresh timer in the refresh control circuit 4 is used to activate the self-refresh when the refresh time elapses from the last access request from the outside.

FIG. 7 shows the operation timing at this time. At times t51 to t52 in the figure, a change in the address Address due to a read request from the outside is detected and refreshing and reading are performed. The operation during this period is exactly the same as the reading for the address "A1" shown in FIG. 4, and the refresh control signal REFA becomes "L" level after this operation. The refresh control circuit 4 resets the value of the refresh timer when the one-shot pulse is generated in the address transition detection signal ATD.

After that, when there is no access request from the outside of the semiconductor memory device, the refresh control circuit 4 raises the refresh control signal REFA at time t53 to make a transition to the refreshable state. If no access request continues despite such a state, the refresh control circuit 4 causes the refresh control signal R
At the time t5, the pulse generation circuit is activated by using the rising edge of the signal obtained by delaying EFA by the delay circuit as a trigger.
At 4, a negative one-shot pulse is generated in the refresh control signal REFB. As a result, the row control circuit 13 generates a one-shot pulse in the row enable signal RE at time t55 to activate self refresh.

At this time, the multiplexer 5 selects the refresh address R_ADD side because the refresh control signal REFB is at the "L" level, and outputs "R1 + 1" as the address M_ADD. And
This self-refresh and the subsequent precharge are exactly the same as those shown in FIG. Thus, at time t59, the precharge enable signal PE falls to complete self refresh and precharge. Even at this time, the access request from the outside is still the same, and therefore, unlike the times t51 to t52, the address Address is not accessed.

After that, the pulse generation circuit in the refresh control circuit 4 refreshes the refresh control signal REF at time t56.
Start up B. Next, when the refresh control circuit 4 receives the rising edge of the refresh control signal REFB,
At time t57, the refresh address R_ADD is updated and its value is set to "R1 + 2". In this case, the address change detection signal ATD has not been generated since the refresh control signal REFA was raised at the time t53, and the state does not shift to the state where the refresh operation is continuously performed due to the address change. Therefore, the refresh control circuit 4 receives the refresh control signal REF at time t58.
A is changed to "L" level, and thereafter, the refresh timer continues to control the refresh operation. Further, the multiplexer 5 receives the rising edge of the refresh control signal REFB and selects the internal address L_ADD side from time t59.

At time t53 to t54, there is an access request from outside the semiconductor memory device and the address Addres
If a change is found in s, the operation becomes as shown in the timing chart of FIG. That is, when the address Address changes to "An" at time t60 and the ATD circuit 3 generates a one-shot pulse in the address change detection signal ATD at time t61, the refresh control circuit 4 performs refresh control as in FIG. The signal REFB is maintained at the "H" level without falling. Therefore, after the time t61, the refresh for the address "R1 + 1" and the reading from the address "An" are performed similarly to the time t51 to t52. As a result, at time t62, the stored data "Dout (An)" at the address "An" is output to the bus I / O. It is assumed in FIG. 8 that the refresh control signal REFA rises at time t53, approaching the cell hold limit timing. Therefore, the refresh control signal REFA is maintained at the "H" level because the refresh is continuously performed with the subsequent memory cycles.

<Writing when the Write Enable Signal is Input Late> Next, writing when the write enable signal / WE is input with a delay will be described with reference to the timing chart of FIG. In this case, since the memory cycle becomes long, this operation is called "Long Write operation" in this specification as shown in FIG. In this case also, the refresh control signal REFA,
REFB remains at the "H" level.

First, at time t71, the value of the address Address changes to "A1", so that the refresh address "R1" is refreshed in exactly the same manner as described above. However, since the write enable signal / WE is still at the "H" level even after this refresh is completed, the read for the address "A1" is performed following the refresh as in FIG. 3 and the like.
As a result, at time t72, "Dout (A1)" which is the storage data of the address "A1" is output to the bus I / O. However, since the side accessing the semiconductor memory device is considering writing to the memory cell, the read data at this point is not actually used on the accessing side. However, the access side may fetch the read data, perform some calculation, and then write the data. That is, the read-modify-write operation can be realized within one memory cycle by intentionally delaying the write enable signal.

Thereafter, at time t73, the write enable signal / WE finally falls to start the writing, and the operation similar to that in the second writing cycle shown in FIG. 6 is performed. Become. However, in this case, there is no change in the address Address due to the fall of the write enable signal / WE and its value is "A
Therefore, the ATD circuit 3 does not generate a one-shot pulse in the address transition detection signal ATD, and the address transition detection signal ATD remains at "L" level. The address L_ADD side will continue to be selected, and the address M_A
The value of DD remains "A1" in preparation for the subsequent writing.

When the write enable signal / WE is input with a delay, the row enable signal RE generated at the falling edge of the address transition detection signal ATD between times t71 and t72 is generated by the completion of the read operation following the refresh. It has returned to the "L" level. Therefore, in this case, the row control circuit 13 generates the row enable signal RE based on the write enable signal / WE.

That is, since the address transition detection signal ATD is at the "L" level at this time, the "H" level is supplied from the inverter 30 shown in FIG. 2 to the delay circuit 52, the NAND gate 53, and the NAND gate 54. . Therefore, at time t73, the write enable signal /
When WE falls, this write enable signal / W
E is delayed by the delay circuit 49, then passes through the NOR gate 50 and the inverter 51, and its level is inverted through the NAND gate 53, the NAND gate 54, and the NAND gate 65, and then output as the row enable signal RE at time t77. . In this case, since the one-shot pulse is not generated in the address transition detection signal ATD, the latch control signal LC also returns to "L" level. However, there is no particular problem because the operation of fetching the address Address into the latch 2 has already been performed at the time of reading the dummy following the refresh.

At time t74, the bus I /
The write data "Din (A1)" is supplied to O, and when the R / W control circuit 11 receives the fall of the write enable signal / WE and falls the control signal CWO at time t75, the time t76. I /
Write data “D” from the O buffer 10 onto the bus WRB.
in (A1) ”is sent out. Therefore, writing is started by the one-shot pulse of the row enable signal RE, and writing is performed to the address“ A1 ”as described with reference to FIG. Be seen.

As described above, in the present embodiment, like the asynchronous SRAM, it is unclear whether the external access request is a read / write at the start of the memory cycle where the address Address starts to change. In addition, it is not possible to predict when the write enable signal / WE is input in the case of writing. For this reason, in the present embodiment, it is assumed that the access request is read for the time being, and the address change detection signal ATD.
The read is performed from the falling edge of, and the write is performed when the write enable signal / WE is subsequently input.

<Case where Writing is Performed After Refresh by Refresh Timer Due to Late Input of Write Enable Signal> Next, another timing of the Long Write operation will be described with reference to the timing chart of FIG. In this figure, the write enable signal /
Since the self-refresh is activated by the refresh timer before WE is input, the write enable signal / WE is activated during the self-refresh.
It corresponds to the case of a fall.

First, the refresh and the dummy reading from time t81 to t83 are exactly the same as the operation shown in FIG. 9 except for the following points. That is, time t
The refresh starting from 81 completes the refresh for one refresh cycle. For this reason, the refresh control circuit 4 causes the refresh control signal REFA to fall at time t82, and stops refreshing until it is necessary to refresh the next refresh cycle. After that, if there is no access request from the outside of the semiconductor memory device, the refresh control circuit 4 raises the refresh control signal REFA at time t84.

However, since there is no subsequent access request even after this, the refresh control circuit 4 generates a negative one-shot pulse in the refresh control signal REFB at time t85. Then, since the refresh control signal REFB becomes the “L” level, the multiplexer 5 selects the refresh address R_ADD side, and the row control circuit 13
Generates a one-shot pulse in the row enable signal RE to activate self-refresh for the address "R1 + 1". Thereafter, at time t86, the write enable signal / WE falls, but self refresh and writing in this case are performed at time t41 in FIG.
~ T48 is the same as that shown.

That is, at time t88, write data is supplied from the outside of the semiconductor memory device onto the bus I / O. From bus WR
Transfer to B. In addition, the multiplexer 5 operates at time t8.
Since the internal address L_ADD side is selected in response to the rising edge of the refresh control signal REFB in 7, the “A1” is output as the address M_ADD at the time t89. After this, when the self refresh is completed, the write data “Di” is written to the memory cell at the address “A1” according to the row enable signal RE generated from the refresh control signal REFB.
n (A1) "is written from the bus WRB.

<When the write enable signal is input late, but refresh is performed by the refresh timer after writing> Next, another timing example of the Long Write operation will be described with reference to the timing chart of FIG. . This drawing shows a case where a refresh request is made by the refresh timer after the write enable signal / WE is input and writing is started, and corresponds to the case where self-refresh is performed after the writing is completed.

First, refreshing and dummy reading at times t91 to t92 are exactly the same as in the case of FIG. After that, if there is no access request from the outside of the semiconductor memory device, the refresh control circuit 4 raises the refresh control signal REFA at time t93.
When the write enable signal / WE falls at time t94 before the refresh timer measures the refresh time, the data "Di" for the address "A1"
n (A1) "is written prior to self-refreshing. Note that this writing itself is the same as the Long Write operation shown in FIG. 9 or 10. Further, the refresh control circuit 4 uses the write enable signal / WE. In case of falling, the internal delay circuit prevents the negative one-shot pulse from being generated in the refresh control signal REFB until the time required for the writing to the memory cell array 6 and the subsequent precharge has elapsed. The rising edge of the refresh control signal REFA is delayed.

When the writing is completed in this way, the pulse generating circuit in the refresh control circuit 4 generates a negative one-shot pulse in the refresh control signal REFB at time t95. This causes the multiplexer 5 to select the refresh address R_ADD side. The row control circuit 13 also generates a one-shot pulse in the row enable signal RE to activate self-refresh for the address “R1 + 1” output from the multiplexer 5. Upon completion of such self-refresh, the refresh control circuit 4 updates the value of the refresh address R_ADD to "R1 + 2" at time t96 in response to the rising of the refresh control signal REFB, and the multiplexer 5 selects the internal address L_ADD side at time t97. To do.

[Second Embodiment] This embodiment is a general-purpose DR.
It realizes the same function as the page mode adopted in AM and the like. FIG. 12 is a block diagram showing the configuration of the semiconductor memory device according to the present embodiment, and the same components and signal names as those shown in FIG. 1 are assigned the same reference numerals. In this embodiment, the address Address described in the first embodiment is replaced with the address UAddr on the upper bit side.
By dividing into ess and lower page address PageAddress, bits that have the same address UAddress can be input / output in burst by changing the address PageAddress.

For example, in this embodiment, the address PageAddr
Since ess has a 2-bit width, the address PageAddress
Is variable within the range of "00" B to "11" B (where "B" means a binary number), continuous four-address data can be burst-accessed. The width of the address PageAddress is not limited to 2 bits and may be any number of bits as long as it is within the range of "2 bits" to "the number of bits of the column address included in the address Address". In this embodiment, the address
Since 4-bit data can be selected by PageAddress, four sets of buses WRBi (here, i = 0 to 3) are provided instead of the bus WRB shown in FIG. Therefore, the value of the address PageAddress is "00" B to "1".
When it is 1 "B, each bit data of the memory cells designated by these addresses are respectively transferred to the buses WRB0 to WR.
It will be input and output through B3.

Next, the address buffer 141 and the latch 1
42, the ATD circuit 143, the column decoder 148, and the sense amplifier / reset circuit 149 have the same configuration as the address buffer 1, the latch 2, the ATD circuit 3, the column decoder 8, and the sense amplifier / reset circuit 9 shown in FIG. In the present embodiment, the address Ad in the first embodiment
Since the address UAddress is used instead of dress,
The configurations of these circuits differ by the difference in the bit width of these addresses. In addition, the sense amplifier / reset circuit 149 has some differences.

That is, in this embodiment, the internal address L_
For each column address included in ADD, 4-bit data is input / output on the buses WRB0-WRB3. Therefore, the sense amplifier / reset circuit 149 simultaneously selects four adjacent bit lines in the memory cell array 6 according to the column selection signal output from the column decoder 148, and the four sets connected to these bit lines are selected. , And the buses WRB0 to WRB3 are connected. Since the address PageAddress is not input to the ATD circuit 143, the address PageAddre
When ss is changed and a burst access is performed, a one-shot pulse is not generated in the address transition detection signal ATD.

Besides, the address buffer 151 is the same as the address buffer 1 except that the bit width of the address is different.
It has the same configuration as the above and buffers the address PageAddress. Further, the bus decoder 152 decodes a 2-bit page address output from the address buffer 151 and outputs four bus selection signals. Further, the bus selector 153 connects any one of the buses WRB0 to WRB3 and the I / O buffer 10 by the bus WRBA in accordance with these bus selection signals.

Next, the operation of the semiconductor memory device having the above configuration will be described with reference to the timing chart of FIG. Since the operation of the figure is based on the operation of FIG. 4 described in the first embodiment, the difference from the operation in FIG. 4 will be mainly described here. Note that "Y1" shown in FIG.
"Y4" is any value from "00" B to "11" B. For the sake of simplicity, here, the values of "Y1" to "Y4" are "00" B to "11" B, respectively. Suppose there is.

First, at time t101, "A1" is given to the address Address as in FIG. At this time, the address Pag
The eAddress is "Y1". As a result, refresh and read corresponding to the address “A1” are performed, and at time t102, the four memory cells specified by the address A1 (that is, the lower address is “00”).
The data stored in B to "11" B) are read onto the buses WRB0 to WRB3, respectively. At this time, the value of the address PageAddress is “00” B, and the bus decoder 152 receives the value “00” B of the address PageAddress “Y1” received through the address buffer 151.
To decode. As a result, the bus selector 153 selects the bus WRB0 and outputs the bit data output there to the bus WRBA. As a result, time t103
Becomes, the value of address A1 [Dout
(A1)] is output.

After that, by appropriately changing the address PageAddress, the address UAddre of the address "A1" is changed.
The data of the memory cell having the same ss portion can be read. That is, at time t104, the address PageAddr
When "Y2" (= "01B") is given to ess, the bus selector 153 selects bit data on the bus WRB1 at time t105 and outputs it to the bus WRBA. At time t106, the lower address is "01" B. The data "Dout (Y2)" stored at the address of is output to the bus I / O.

Similarly, at time t107, the address Pa
When “Y3” (= “10” B) is given to geAddress, the bus WRB2 is connected to the bus WRBA at time t108,
At time t109, the data “Dout (Y3)” stored in the lower address “10” B is transferred to the bus I / O.
Output to O. Also, at time t110, the address PageAd
When "Y4" (= "11B") is given to the dress, time t
At 111, the bus WRB3 is connected to the bus WRBA, and at time t112, the data “Dout (Y4)” stored at the lower address “11” B is output to the bus I / O. In the above description of the second embodiment, the case of application to FIG. 4 has been described, but it goes without saying that it may be applied to each case shown in FIGS. 5 to 11.

[Third Embodiment] In each of the above-described embodiments, the address Addres is added regardless of whether the access request supplied from the outside is a read request or a write request.
Read or write is performed after refresh is triggered by a change in s (including the case where the chip select signal / CS is validated).

On the other hand, in the present embodiment, when there is a read request, the read is performed and then the refresh is performed, which improves the read speed (access We are trying to reduce the time). When there is a write request, refresh is performed before writing as in the above-described embodiments.

FIG. 14 is a block diagram showing the structure of the semiconductor memory device according to the present embodiment. Since the configuration of the semiconductor memory device shown in the figure is basically the same as the configuration of the first embodiment (FIG. 1), the same components as those in FIG. 1 are denoted by the same reference numerals in FIG. Although the present embodiment is described below based on the semiconductor memory device of the first embodiment, the technical idea of the present embodiment may be applied to the semiconductor memory device of the second embodiment.

According to the specifications of the general-purpose SRAM, the write enable signal is asynchronously applied to the change of the address. Here, in the present embodiment, the processing order of the refresh operation and the access operation to the memory cell is opposite between the case of reading and the case of writing. Therefore, in the present embodiment, it is necessary to determine at a certain timing whether the externally supplied access request is read / write, and determine the processing order based on this determination result.

Therefore, in this embodiment, the address Address
From the time when the write enable signal / WE is validated (for example, the time corresponding to the time tAW shown in FIG. 16) (hereinafter, this maximum value is referred to as tAWm).
ax) is specified as a specification of the semiconductor memory device. That is, on the system side using the semiconductor memory device, when writing to the semiconductor memory device, it is necessary to validate the write enable signal / WE within a time tAWmax from the time when the address Address is changed. The value of the time tAWmax may be appropriately determined according to the required specifications on the system side.

The ATD circuit 163 shown in FIG. 14 has substantially the same function as the ATD circuit 3 shown in FIG. However, since the read / write operation is not determined until the time tAWmax elapses after the address starts changing, the ATD circuit 163 detects the address change until the time tAWmax elapses after the address change is detected. The signal ATD is not generated.

Here, the maximum value of the skew included in the address Address is set to the time tskew (see FIG. 15, for example).
Then, depending on the system, it may be shorter than the time tskew indicated by the value of the time tAWmax. As described above, since the value of the time tAWmax is originally determined according to the required specifications on the system side, it can be set independently of the time tskew.

However, from the time when the address Address starts to change until the time tskew elapses, the address Ad
Since the value of dress is not fixed, access to the memory cell array must not be started until then. Therefore, when the time tAWmax is shorter than the time tskew, the value of the time tAWmax is set to the time tskew so that the access is performed after the address Address is fixed.

However, what has just been described may be considered in the case of reading. In the case of writing, since writing is performed after refreshing also in the present embodiment, even if the refresh operation is started after the time tAWmax has elapsed from the address change point and it is determined whether the read / write is performed. There is no hindrance. Furthermore, if the write enable signal / WE becomes valid before the time tAWmax elapses, it can be determined that the write operation is performed at that time. Therefore, the time tAWma
The refresh operation may be started without waiting for the elapse of x.

The refresh control circuit 164 has the same function as the refresh control circuit 4 of FIG. However, the refresh control circuit 164 refers to the write enable signal / WE when the address transition detection signal ATD rises, and if it is a read request, updates the refresh address R_ADD by using the rise of the address transition detection signal ATD as a trigger, and writes. If it is a request, the fall of the address transition detection signal ATD is used as a trigger to update the refresh address R_ADD.

Next, the multiplexer 165 has substantially the same function as the multiplexer 5 shown in FIG. However, in the present embodiment, in the case of reading, it is necessary to perform the reading prior to the refresh. Therefore, in order to determine whether the reading / writing is performed, the write enable signal / WE is input to the multiplexer 165. There is. When the write enable signal / WE is at “L” level (write), the operation of the multiplexer 165 is the same as that of the multiplexer 5.

On the other hand, write enable signal / W
When E is at "H" level, the multiplexer 165 performs a selection operation opposite to that for writing. Specifically, the multiplexer 165 selects the internal address L_ADD side when the address transition detection signal ATD is at “H” level and the refresh control signal REFB is at “H” level,
If the address transition detection signal ATD is at "L" level or the refresh control signal REFB is at "L" level, the refresh address R_ADD side is selected.

Next, the row control circuit 173 has substantially the same function as the row control circuit 13 shown in FIG. 1, and performs the same operation as the row control circuit 13 in the case of writing. On the other hand, in the case of reading, the row control circuit 173 activates the row enable signal RE, the sense amplifier enable signal SE, the control signal CC and the precharge signal PE for the read operation by using the rising edge of the address transition detection signal ATD as a trigger. . Further, the row control circuit 173 uses the falling edge of the address transition detection signal ATD as a trigger, and the row enable signal R for the refresh operation.
E, the sense amplifier enable signal SE and the precharge enable signal PE are activated.

Next, the operation of the semiconductor memory device according to the present embodiment will be explained. Here, the read operation will be described first with reference to the timing chart shown in FIG. 15, and then the write operation will be described with reference to the timing chart in FIG.

First, when the address Address changes at time t120 shown in FIG. 15, this address change is transmitted to the ATD circuit 163 through the address buffer 1 and the latch 2. However, since the read / write is undetermined at this point, the ATD circuit 163 does not immediately generate the one-shot pulse of the address transition detection signal ATD.

After this, from time t120 to time tAWma
At time t122 after x has elapsed, it is determined whether the writing / reading is performed, so that the ATD circuit 163 generates a one-shot pulse in the address transition detection signal ATD at time t123. In this case, the write enable signal / WE is at the “H” level because it is a read request, and the multiplexer 165 selects the internal address L_ADD side and selects the address M at time t124.
_ADD (= address “A1”) is supplied to the row decoder 7. The row control circuit 173 uses the rising edge of the address transition detection signal ATD as a trigger to enable the row enable signal RE, the sense amplifier enable signal SE, and the control signal CC.
And the precharge signal PE is sequentially generated. As a result, the read operation is performed in the same manner as the case indicated by “Read Cycle” in FIG. 3, and the word line Ax_Word corresponding to the address “A1” is activated at time t125, and at time t126 the memory cell Data “Dout (A
1) "is read onto the bus I / O.

After that, when the address transition detection signal ATD falls at time t127, the multiplexer 165 comes to select the refresh address R_ADD side, and at time t128, the address M_ADD (= address "R1 +
1 ") is supplied to the row decoder 7. Further, the row control circuit 173 uses the fall of the address transition detection signal ATD as a trigger to sequentially output the row enable signal RE, the sense amplifier enable signal SE, and the precharge signal PE. As shown in Fig. 3, "RefreshCycl" is generated.
The refresh operation is performed in the same manner as the case indicated by "e", and for example, the word line corresponding to the address "R1 + 1"
Rx_Word is activated at time t129.

Next, the operation when there is a write request will be described. In the case of writing, time t1 shown in FIG.
At the time t from when the address Address starts changing at 40
The write enable signal / WE is enabled by time t143 after the lapse of AWmax. In FIG. 16, it is assumed that the write enable signal / WE has fallen at time t142 after time tAW from time t140.

Next, the ATD circuit 163 receives the address change and the fall of the write enable signal / WE,
At time t144, a one-shot pulse is generated in the address transition detection signal ATD. At this time, since the write enable signal / WE is at the “L” level, the multiplexer 165 selects the refresh address R_ADD side for the refresh operation and outputs “R1” as the address M_ADD to the row decoder 7 at time t145. Further, the row control circuit 173 sequentially generates a row enable signal RE, a sense amplifier enable signal SE, and a precharge signal PE. As a result, after the time t31 in FIG.
The refresh operation is performed in the same manner as in the case of "fresh Cycle".

Thereafter, at time t146, the write data value "Din (A1)" is supplied to the bus I / O. Next, at time t147, the ATD circuit 163
When the address transition detection signal ATD falls, the multiplexer 165 selects the internal address L_ADD side, and at time t148, the address M_ADD is set to "A1".
And outputs the row address portion of the row decoder 7 to the row decoder 7. Also,
The row control circuit 173 sequentially generates a row enable signal RE, a sense amplifier enable signal SE, a control signal CC and a precharge signal PE. As a result, the write operation is performed in the same manner as the case indicated by the "Write cycle" in FIG.

As described above, in this embodiment, the read operation can be started when the time tAWmax elapses after the address changes. Therefore, the read speed can be increased and the access time can be shortened as compared with the first embodiment and the second embodiment. In particular, the time required for the refresh operation is long in each of the above-described embodiments, and the time tAW in the present embodiment is long.
The smaller the value of max, the greater the effect of improving the access time.

[Fourth Embodiment] In each of the above-described embodiments, the standby mode is switched based on the power-down control signal PowerDown supplied from outside the semiconductor memory device. On the other hand, in this embodiment, the same standby mode switching as in each of the above-described embodiments is realized by writing the data for the mode switching instruction to the specific address on the memory cell array 6 which is determined in advance. ing. Here, in the semiconductor memory device according to the present embodiment, the address "0" (the lowest address) on the memory cell array 6 is used as a data storage area dedicated to mode switching. Further, in the present embodiment, the data for setting the standby mode 2 is “F0” h (here, “h” means a hexadecimal number), and the data for setting the standby mode 3 is “0F”. It is assumed to be h. Therefore, in this embodiment, the bus width of the bus WRB is 8 bits.

FIG. 17 is a block diagram showing the structure of the semiconductor memory device according to the present embodiment. The same components and signal names as those shown in FIG. 1 are designated by the same reference numerals. 17 is different from FIG. 1 in that there is no pin for inputting the power down control signal PowerDown, that the standby mode control circuit 201 is newly added, the refresh control circuit 204, and the boost power supply 215. The substrate voltage generation circuit 216 and the reference voltage generation circuit 217 are partially different from the refresh control circuit 4, the boost power supply 15, the substrate voltage generation circuit 16, and the reference voltage generation circuit 17 shown in FIG. 1, respectively. Can be mentioned. Therefore, hereinafter, FIG.
Details of each of these units will be described with reference to FIG. In these figures, the same components and signal names as those shown in FIG. 1 or FIG. 17 are designated by the same reference numerals.

First, in FIG. 17, the standby mode control circuit 201 uses the internal address L_ADD, the chip select signal / CS, the write enable signal / WE, and the bus WRB.
Based on the write data above, the mode setting signal MD2
Generate MD3. Of these, the mode setting signal MD2
Is a signal which becomes “H” level when the standby mode 2 is set, and is supplied to the refresh control circuit 204. On the other hand, the mode setting signal MD3 is a signal that becomes the “H” level when the standby mode 2 or the standby mode 3 is set, and is supplied to the boost power supply 215, the substrate voltage generation circuit 216, and the reference voltage generation circuit 217. The standby mode 1 is when both the mode setting signals MD2 and MD3 are at "L" level.

FIG. 18 is a circuit diagram showing the detailed structure of the standby mode control circuit 201. In the figure, data WRB0 to WRB3 and WRB4 to WRB7 are bits 0 to 3 and 4 to 7 of write data supplied onto the bus WRB from outside the semiconductor memory device. And
The circuit composed of the AND gate 221, the NOR gate 222, and the AND gate 223 outputs the "H" level only when the write data is "F0" h.
Similarly, the circuit including the NOR gate 224, the AND gate 225, and the AND gate 226 outputs the "H" level only when the write data is "0F" h. Further, the OR gate 227 is an AND gate 233, 2.
By taking the logical sum of the outputs of 26, "H" level is output when either "F0" h or "0F" h is input as the write data.

Next, the addresses X0B to Y7B are address values obtained by inverting each bit forming the internal address L_ADD. For example, the address X0B is the inverted value of bit 0 of the row address, and the address Y7B is the inverted value of bit 7 of the column address. Therefore, the AND gate 228 outputs the "H" level only when all the bits of the internal address L_ADD detect "0" B (that is, the address "0"). And AND gate 229
Is data “F0” h or “0F” h for address “0”
Write enable signal / WE only when writing
Is output as is as a clock. Further, the AND gate 230 outputs the write enable signal / WE as a clock as it is only when writing the data "0F" h to the address "0".

Next, the circuit consisting of the inverters 231 to 236 and the AND gate 237 is operated by the chip select signal /
The one-shot pulse is generated in the signal CEOS by catching the falling edge of CS. Next, when the output of the AND gate 229 rises and the clock is input to the C terminal, the latch 238 sets the “H” level corresponding to the power supply potential supplied to the D terminal as the Q mode setting signal MD2.
Output from the terminal. Further, the latch 238 resets itself and outputs the "L" level to the mode setting signal MD2 when a one-shot pulse is generated in the signal CEOS supplied to the R terminal. The latch 239 also has the same configuration, and outputs "H" level to the mode setting signal MD3 when the output of the AND gate 230 rises and outputs "H" level to the mode setting signal MD3 when a one-shot pulse occurs in the signal CEOS. The L "level is output.

As described above, when the standby mode 2 is set, the output of the AND gate 229 rises in synchronization with the rising of the write enable signal / WE, the D type latch 238 is set, and the mode setting signal MD2 is set. It becomes "H" level. In addition, when the standby mode 3 is set, the write enable signal / WE
The outputs of the AND gates 229 and 230 rise in synchronism with the rise of the latches 238 and 239, and both the mode setting signal MD2 and the mode setting signal MD3 are set to the “H” level.

Next, the refresh control circuit 204 shown in FIG. 17 uses the chip select signal / CS and the mode setting signal MD2 instead of the power down control signal PowerDown.
Are used to generate the refresh address R_ADD and the refresh control signals REFA and REFB. here,
FIG. 19 is a circuit diagram showing a detailed configuration of the refresh control circuit 204. In the figure, a P-channel transistor 24
The gate terminal 0, the source terminal, and the drain terminal 0 are connected to the output of the AND gate 241, the power supply potential, and the power supply pin of the refresh control circuit 4, respectively. For this reason,
If the output of the AND gate 241 is "L" level, the transistor 240 is turned on to supply power to the refresh control circuit 4, and if the output is "H" level, the transistor 240 is cut off and power supply is stopped. Let

The AND gate 241 operates when the semiconductor memory device is in a non-selected state (chip select signal / CS is at "H" level) and in standby mode 2 or standby mode 3 (mode setting signal MD2 is at "H" level). ,
The transistor 240 is cut off. Next, the inverter 242 generates an inverted signal of the mode setting signal MD2, and its output becomes "H" level in the standby mode 1. The AND gate 243 directly outputs the refresh address R_ADD generated by the refresh control circuit 4 in the standby mode 1, while
In the standby mode 2 or the standby mode 3, the same address is fixed to "0".

AND gate 244 is in standby mode 1
Then, the refresh control signal REFA generated by the refresh control circuit 4 is output as it is, while in the standby mode 2 or the standby mode 3, the signal is fixed to the “L” level. Further, since the inverter 245 inverts the output of the inverter 242, it outputs the “L” level in the standby mode 1. In the standby mode 1, the OR gate 246 outputs the refresh control signal REFB generated by the refresh control circuit 4 as it is, while in the standby mode 2 or the standby mode 3, the OR gate 246 fixes the signal at the “H” level.

20 to 22 are circuit diagrams showing the detailed structures of the boost power supply 215, the substrate voltage generation circuit 216 and the reference voltage generation circuit 217, respectively.
In the boost power supply 215, the P-channel transistor 250 and the AND gate 251 have the same functions as the transistor 240 and the AND gate 241 shown in FIG. 19, respectively. That is, when the semiconductor memory device is in the non-selected state (chip select signal / CS is at "H" level) and in standby mode 3 (mode setting signal MD3 is at "H" level), the transistor 250 is cut off to boost. The power supply to the power supply 15 is stopped, and in other cases, the boost power supply 15 is supplied with power. The above is exactly the same for the substrate voltage generation circuit 216 and the reference voltage generation circuit 217.
Transistors 252 and 254 configuring these circuits correspond to the transistor 250 in the boost power supply 215,
The AND gates 253 and 255 correspond to the AND gate 251 in the boost power supply 215.

Next, the operation at the time of switching the standby mode in the semiconductor memory device having the above configuration will be as follows.

Standby Mode 1 To set the semiconductor memory device to the standby mode 1, the chip select signal / CS may be lowered. By doing so, the standby mode control circuit 201 generates a one-shot pulse from the falling edge of the chip select signal / CS to reset the latches 238 and 239, and sets the mode setting signals MD2 and MD3 to "L" level. And

Thus, the refresh control circuit 204
Then, the transistor 240 is turned on to supply power to the internal refresh control circuit 4, and the refresh address R_ADD and the refresh control signals REFA and REFB generated by the refresh control circuit 4 are output as they are. The boost power supply 215, the substrate voltage generation circuit 216, and the reference voltage generation circuit 217 also supply power to the internal boost power supply 15, substrate voltage generation circuit 16, and reference voltage generation circuit 17, respectively. By performing the above operation, the operation described in the first and second embodiments can be performed.

Standby Mode 2 To set the standby mode 2, it is sufficient to write the data “F0” h to the address “0” as described above. As a result, the standby mode control circuit 201 sets the mode setting signal MD2 to "H" level from the rising edge of the write enable signal / WE. If the semiconductor memory device is not selected at this point or is no longer selected, the chip select signal / CS becomes "H" level, so that the refresh control circuit 204 supplies power to the internal refresh control circuit 4. Stop.

Since the output of the refresh control circuit 4 becomes indefinite due to the power supply to the refresh control circuit 4 being cut off, the refresh control circuit 204 fixes the refresh address R_ADD to "0" and outputs the refresh control signals REFA and REFB. Each level is "L"
Level, fixed at "H" level. Since the chip select signal / CS is at "H" level at this point,
Even if the internal address L_ADDi (see FIG. 2) changes, the ATD circuit 3 does not generate the one-shot pulse in the address change detection signal ATD and keeps it at the “L” level.

Therefore, the row control circuit 13 fixes the row enable signal RE, the sense amplifier enable signal SE, the precharge enable signal PE, and the control signal CC to the "L" level. Therefore, the column enable signal CE and the latch control signal LC also remain at "L" level. On the other hand, since the refresh control signal REFB is fixed at "H" level and the address transition detection signal ATD is fixed at "L" level, the multiplexer 5 continues to select the internal address L_ADD side.

As described above, the refresh operation is interrupted and the current consumption is reduced. At this time, since the mode setting signal MD3 remains at the "L" level, power is continuously supplied to the boost power supply 15, the substrate voltage generation circuit 16, and the reference voltage generation circuit 17 (see FIGS. 20 to 22). .

Standby Mode 3 To set the standby mode 3, it is sufficient to write the data “0F” h to the address “0” as described above. As a result, the standby mode control circuit 201 sets both the mode setting signal MD2 and the mode setting signal MD3 to "H" from the rising edge of the write enable signal / WE.
Level. Therefore, when the chip select signal / CS becomes "H" level, the refresh control circuit 204 stops the power supply to the internal refresh control circuit 4 as in the standby mode 2. At the same time, the boost power supply 215, the substrate voltage generation circuit 21
6. The reference voltage generation circuit 217 stops the power supply to the internal boost power supply 15, substrate voltage generation circuit 16, and reference voltage generation circuit 17, respectively. As a result, in the same manner as in the standby mode 2, the refresh control is interrupted, and the current of the power supply system control circuit is also cut to further reduce the current consumption.

As described above, in this embodiment, it is not necessary to give a signal such as the power-down control signal PowerDown described in the first embodiment from the outside of the semiconductor memory device.
The number of pins can be reduced accordingly. Although the fourth embodiment has been described based on the first embodiment in the above description, the same thing may be applied to the second embodiment and the third embodiment as they are.

[Fifth Embodiment] In each of the above-described embodiments, the refresh operation of the entire memory cell array in the semiconductor memory device is controlled according to one of the three standby modes selected. There is. Therefore, for example, the memory cell array 6 shown in FIG. 1 has a plurality of regions (hereinafter, “memory cell area”).
Even in the case where the memory cell area is divided into all the memory cell areas, the self-refresh operation in the standby state is commonly controlled in the same standby mode.

However, depending on the application to which the semiconductor memory device is applied, it is necessary to hold data in a standby state for a certain memory cell area (memory space), but only data to be used temporarily is placed. In the memory cell area (the memory cell area used as a buffer as described above), it may not be necessary to hold data in the standby state. For example, when considering a mobile terminal system typified by a mobile phone, information such as a home page downloaded from the Internet has a property of temporarily holding it only while the user is watching it.

That is, with respect to the memory cell area used for the purpose as just described, it is not necessary to perform the self-refresh in the standby state, so that the standby current can be reduced accordingly. To that end, if it is possible to specify whether to self-refresh and hold data for each memory cell area, it becomes possible to efficiently control the standby current according to the user's needs and applications. For example, by allocating the memory cell area according to the mobile terminal system,
It is also possible to keep the standby current to the minimum consumption.

From this background, in the present embodiment, when the memory cell array is composed of a plurality of memory cell areas, the standby mode can be set individually for each memory cell area. FIG. 23 is a block diagram showing a configuration of a main part of the semiconductor memory device according to the present embodiment, which realizes the present embodiment based on the configuration of FIG. However, for convenience of illustration, FIG. 23 shows only the circuit around the memory cell area, and the address buffer 1, the latch 2, the ATD circuit 3, the refresh control circuit 4, the multiplexer 5, and the R / R shown in FIG.
Although the W control circuit 11, the latch control circuit 12, and the signals related to them are omitted, they are the same as those in FIG.

FIG. 23 exemplifies a case where the memory cell array 6 shown in FIG. 1 is divided into _two memory cell areas 6 ₁ and 6 ₂ , but it goes without saying that the number of memory cell areas is not limited. good. Here, in the following explanation,
The memory cell area and peripheral circuits provided in each memory cell area corresponding to the memory cell area will be collectively referred to as a "memory plate". For example, in the configuration example shown in FIG. 23, the memory cell area 6 ₁ and its peripheral circuits such as a row decoder 7 ₁ , a column decoder 8 ₁ , a sense amplifier / reset circuit 9 ₁ , a boost power supply 15 ₁ , a substrate voltage generation circuit 16 ₁ , The reference voltage generation circuit 17 ₁ is defined as one memory plate.

However, as will be described later, the row control circuit 3
13 generates a control signal for each memory cell area.
Therefore, for example, the circuit portion in the row control circuit 313 for generating the row enable signal RE1, the sense amplifier enable signal SE1, and the precharge enable signal PE1 may be included in the peripheral circuit corresponding to the memory cell area 6 ₁ . Further, in the following description, the boost power supply 15 ₁ , the substrate voltage generation circuit 16 ₁ and the reference voltage generation circuit 17 ₁ necessary for the self-refresh operation are collectively referred to as “first power supply circuit”, and the boost power supply 15 ₂ , Substrate voltage generation circuit 16 ₂ and reference voltage generation circuit 17 ₂
Are collectively referred to as "second power supply circuit".

Next, the row decoder 7₁， Column decoder
8₁, Sense amplifier reset circuit 9 ₁, Boost power supply 1
5₁, Substrate voltage generation circuit 16₁, Reference voltage generation
Road 17₁Is memory cell area 6₁It corresponds to
, The constituent elements of FIG. 1 with the subscript “1” removed from each code
It has the same configuration as. For example, the row decoder 7₁Figure 1
It is the same as the row decoder 7 shown in FIG. Also each of these structures
Component subscript “₁"Subscript"₂Is replaced by memory
Cell area 6₂Is a component provided corresponding to.

Next, the I / O buffer 10 is the same as that shown in FIG. 1, but in the present embodiment, it is connected to both the sense amplifier / reset circuits 9 ₁ and 9 ₂ through the bus WRB. Next, the column control circuit 14 is the same as that shown in FIG. 1, but in this embodiment, the column enable signal CE is supplied to both the column decoder 8 ₁ and the column decoder 8 ₂ .

Next, the PowerDown control circuit 301 generates the control signals PD1 and PD2 in the standby state and supplies the control signals PD1 and PD2 to the first power supply circuit and the second power supply circuit, respectively, to individually perform the power cut operation of these power supply circuits. To control. In this embodiment, the control signals PD1 and PD2 are set to "H".
It is assumed that each power supply circuit supplies power when set to the level, and each power supply circuit cuts power supply when the signal is set to "L" level. In the normal operation which is not the standby state, the PowerDown control circuit 301 outputs the control signal P
Both D1 and PD2 are set to "H" level.

Here, in the present embodiment, for simplification of description, a standby mode in which memory cells are self-refreshed (“refreshing”), a standby mode in which memory cells are not self-refreshing (“no refreshing”). The case where two types of modes are provided will be described, but the same applies to the case where three types of standby modes are provided as in the above-described embodiments. Further, in the present embodiment, the control signals PD1 and P1 in the standby state are
It is assumed that the level of D2 is fixed.
Note that the configuration in which the levels of these control signals are programmable from the outside will be described in the sixth embodiment, but the levels of the control signals may also be programmable in this embodiment.

Next, the row control circuit 313 has substantially the same structure as the row control circuit 13 shown in FIG. However, since two memory plates are provided in this embodiment, the row control circuit 313 generates two-system control signals corresponding to each memory plate. That is, the row control circuit 31
3 supplies the row enable signals RE1 and RE2 to the row decoders 7 ₁ and 7 ₂ , respectively, the sense amplifier enable signal SE1 and the precharge enable signal PE1 to the sense amplifier / reset circuit 9 ₁ , and the sense amplifier enable signal SE2 and Precharge enable signal P
E2 is supplied to the sense amplifier / reset circuit 9 ₂ . The row control circuit 313 also controls the control signals PD1 and PD.
It controls whether or not to generate the control signals of the above two systems in conjunction with the level of 2. For example, if the PowerDown control circuit 301 outputs "L" level to the control signal PD2 in the standby state, the row control circuit 313 does not generate the control signals to be supplied to the memory cell area 6 ₂ side in the standby state.

Next, the semiconductor memory device having the above structure is operated.
The standby operation will be described. First, memory cell error
A6₁, 6₂If both are used with "refresh"
In this case, the PowerDown control circuit 301 goes into standby mode.
Both control signals PD1 and PD2 are set to "H" level
The same as when not in standby mode.
Supply voltage to both the circuit and the second power supply circuit
It In conjunction with this, the row control circuit 313 is connected to the row enable circuit.
Bull signals RE1 and RE2, sense amplifier enable signal
SE1 and SE2, precharge enable signal PE
1 and PE2 are sequentially generated. Because of this, raw deco
Order 7₁, 7₂Is the memory cell area 6 ₁, 6₂upper
Activates the word line and activates the sense amplifier / reset circuit
Road 9₁, 9₂Select a sense amplifier for each
Do the fresh.

Next, when both the memory cell areas 6 ₁ and 6 ₂ are used without "refresh", the PowerDown control circuit 301 is in the standby state and the control signals PD1 and P1
Both D2 are set to "L" level. Therefore, the first power supply circuit and the second power supply circuit stop supplying voltage. Further, the row control circuit 313 does not generate the row enable signals RE1 and RE2, the sense amplifier enable signals SE1 and SE2, and the precharge enable signals PE1 and PE2 in the standby state. Therefore, in this case, self refresh is not performed at all.

Next, the memory cell area 6 ₁ is "refreshed" and the memory cell area 6 ₂ is "refreshed".
In this case, the PowerDown control circuit 301 outputs "H" level and "L" level to the control signals PD1 and PD2, respectively, in the standby state. Also, the row control circuit 313 generates the row enable signal RE1, the sense amplifier enable signal SE1, and the precharge enable signal PE1 in the standby state, and does not generate the row enable signal RE2, the sense amplifier enable signal SE2, and the precharge enable signal PE2. .. In this way, only the first power supply circuit supplies the voltage, and the self refresh is performed only for the memory cell area 6 ₁ .

Next, when the memory cell area 6 _{1 is used} with “no refresh” and the memory cell area 6 ₂ is used with “refresh”, it is the exact opposite of what has just been described. That is, the PowerDown control circuit 301 sets the control signals PD1 and PD2 to "L" level and "H" level, respectively, in the standby state. In addition, the row control circuit 31
3 generates only the row enable signal RE2, the sense amplifier enable signal SE2, and the precharge enable signal PE2 in the standby state. Therefore, only the second power supply circuit supplies the voltage, and the self refresh is performed only for the memory cell area 6 ₂ .

In this embodiment, a standby current of about 100 μA is generated when both memory cell areas are set to “with refresh”. On the other hand, when only one of the memory cell areas is "refreshed", the standby current can be halved to 50 μA, which is about 1/2. On the other hand, when both memory cell areas are set to "no refresh", the standby current can be made completely zero.

Although the present embodiment has been described based on the first embodiment in the above description, the same thing may be applied to the second embodiment and the third embodiment. In FIG. 23, the memory cell areas 6 ₁ and 6 ₂ are drawn as if they have the same capacity, but the memory cell areas may have different capacities. Further, in the above description, the case of two types of standby modes has been described, but
It may be applied to the case of three kinds of standby modes as in the third embodiment.

[Sixth Embodiment] FIG. 24 is a block diagram showing the configuration of the main part of the semiconductor memory device according to the present embodiment, which realizes the present embodiment based on the configuration of FIG. Also in this embodiment, the memory cell array 6 is divided into a plurality of memory cell areas as in the fifth embodiment.
The standby mode can be set separately for each memory cell area (memory plate).

However, in this embodiment, since the semiconductor memory device having a large number of memory cell areas is kept in mind, unlike the case of FIG. 23, the number of memory cell areas is generalized to n (n: 2 or more). It is as a natural number). Therefore, the memory cell array 6 shown in FIG. 1 is divided into memory cell areas 6 _{1 to} 6 _n in FIG. Further, in FIG. 24, row decoders 7 _{1 to} 7 _n , corresponding to individual memory cell areas,
Column decoders 8 ₁ to 8 _n and sense amplifier / reset circuits 9 _{1 to} 9 _n are provided.

Next, the power supply circuit 350 is a power supply circuit common to the memory cell areas 6 _{1 to} 6 _n , and integrates the boost power supply 15, the substrate voltage generation circuit 16, and the reference voltage generation circuit 17 shown in FIG. At the same time, the power supply capability is strengthened as compared with the configuration shown in FIG. 1 so that power can be supplied to all n memory cell areas at the same time.
Since the power supply circuit is shared between the memory cell areas in the present embodiment, the memory plate is, for example, the memory cell area 6 ₁ and its peripheral circuits such as the row decoder 7 ₁ , the column decoder 8 ₁ , the sense amplifier / reset circuit. It is composed of 9 ₁ .

Next, the PowerDown control circuit 351 is shown in FIG.
It is a circuit similar to the PowerDown control circuit 301 shown in
Control signals to correspond to n memory cell areas.
Generate PD1 to PDn. Next, the switch element 352
₁~ 352_nRespectively according to the control signals PD1 to PDn
Memory cell area 6₁~ 6_nEach memory plate corresponding to
It controls the power supply to. For example, switch element 3
52₁Is on when the control signal PD1 is at "H" level
From the power supply circuit 350 to the memory cell area 6 ₁Against
In addition to supplying power to the corresponding memory plate,
When it is at “L” level, it turns off and the same memory plate is displayed.
Turn off the power supply to the device. The switch element 35
Two₂~ 352_nSwitch element 352₁Is the same as.

Next, the row control circuit 353 is a circuit similar to the row control circuit 313 shown in FIG. 23, and has row enable signals RE1 to REn, sense amplifier enable signals SE1 to SEn, and precharge enable signal PE1.
~ PEn are generated and these control signals are supplied to the corresponding memory plates. Next, the program circuit 354 can arbitrarily program whether each memory cell area is set to “with refresh” or “without refresh” according to the needs and applications of the user. Then, the program circuit 354 sends the data representing “with refresh” or “without refresh” programmed for each memory cell area to the PowerDown control circuit 351 and the row control circuit 353.

Here, the following two methods can be considered as specific examples for realizing the programming circuit 354 from the outside of the semiconductor memory device. First, as a first realization method, a program circuit 354
It may be possible to provide a fuse corresponding to the memory plate inside. In this case, the control signal PD1 in the standby state depends on whether or not each fuse is cut.
It becomes possible to individually set the levels of PDn.

Next, a method using an address supplied from the outside can be considered as a second realizing method. That is, since the memory cell areas 6 _{1 to} 6 _n are respectively assigned to different memory spaces, the address Addr is externally applied.
When ess (see FIG. 1) is given, the memory cell area corresponding to this address is uniquely determined. For example, if n = 4, the value of the upper 2 bits of the address Address is “0”.
In the case of 0 "B to" 11 "B, the memory cell areas 6 _{1 to} 6 ₄ are accessed, respectively, so that the memory cell area to be programmed can be specified by the address Address.

In order to realize the above, the structure according to the fourth embodiment (see FIGS. 17 and 18) may be adopted. First, a register for holding a standby mode set from the outside is provided in the program circuit 354 for each memory plate. Also the address Addres
s, chip select signal / CS, write enable signal / WE, and bus WRB are input to the program circuit 354.

In setting the standby mode, the memory plate to be set is specified by the upper 2 bits of the address Address, and the lower bits other than this are specified by a specific value (for example, the lower bit is set according to the fourth embodiment). Set all to "0" B). Also, data representing the standby mode to be set is placed on the bus WRB. When the write enable signal / WE is fallen in this state, the program circuit 354 fetches the data of the standby mode to be set in the memory plate specified by the upper 2 bits of the address Address from the bus WRB and responds to the memory plate. Set to register.

Next, the standby operation of the semiconductor memory device having the above structure will be described. Now, for example, only the memory cell area 6 ₁ is set to “with refresh” and all other memory cell areas are set to “without refresh”. Then, this setting is programmed in the program circuit 354 using one of the above-described two implementation methods. As a result, the standby mode setting for each memory plate is set to the PowerDown control circuit 351 and the row control circuit 3.
53 is notified.

As described above, the control signals PD1 to PDn are all at the "H" level during the normal operation. On the other hand, when it enters the standby state, PowerDown
The control circuit 351 keeps the control signal PD1 at the "H" level, and sets all other control signals PD2 to PDn to the "L" level. Thereby, the switch element 35
21 remains on, whereas switch element 352 ₂
˜352 _n are all off. Therefore, the power supply circuit 350 is provided in the memory plate corresponding to the memory cell area 6 _1.
Power continues to be supplied from the memory cell area 6 ₂ ~
Power is not supplied to the memory plate corresponding to 6 _n .

On the other hand, the row control circuit 353 generates the row enable signal RE1, the sense amplifier enable signal SE1, and the precharge enable signal PE1 to self-refresh the memory cell area 6 ₁ to which power is continuously supplied. Further, the row control circuit 353 does not generate the row enable signal, the sense amplifier enable signal, and the precharge enable signal for the memory plates corresponding to the memory cell areas 6 _{2 to} 6 _n where the power is not supplied. In this way, by controlling so that only the memory cell area 6 ₁ is self-refreshed in the standby state, the standby current is reduced to "1 /".
It can be reduced to n ″.

As described above, according to this embodiment, the same advantages as the fifth embodiment can be obtained, and the standby mode can be arbitrarily set from the outside according to the needs and applications of the user. In addition, since the power supply circuit 350 is shared between the memory plates in the present embodiment, it is not necessary to increase the power supply circuits even if the number of memory plates is increased, and the configuration is smaller than that in the fifth embodiment. can do.

In the above description, this embodiment has been described based on the configuration of the first embodiment, but the same thing can be applied to the second embodiment.
It may be applied to the embodiments to the fourth embodiment. Also, FIG.
In FIG. 4, the memory cell areas 6 _{1 to} 6 _n are drawn as if they have the same capacity, but these memory cell areas may have different capacities. Furthermore, in the above description, the case of two types of standby modes has been described.
It may be applied to the case of three kinds of standby modes as in the third embodiment.

Further, the control of the standby mode described in each of the above-mentioned embodiments (first to sixth embodiments) may be applied to the existing semiconductor memory device such as the conventional pseudo SRAM or general-purpose DRAM. However, the pseudo SRAM is not limited to the general-purpose SRAM specification pseudo SRAM described in each embodiment.

[Seventh Embodiment] First Embodiment
In the sixth embodiment, all the refresh operations of the memory cell array 6, the memory cell areas 6 ₁ , 6 ₂ , 6 _n are controlled inside the semiconductor memory device. On the other hand, in the present embodiment, the refresh operation is controlled inside the semiconductor memory device as in the above embodiments, and the refresh operation is also controllable from outside the semiconductor memory device. By adopting such a configuration, it becomes possible to select a chip having a defect during the refresh operation by a test before shipping.

Therefore, first, the specific contents of this problem and the reason why such a problem occurs will be described. In the first embodiment, for example, of the above-described respective embodiments, the refresh start timing is controlled based on the refresh control signals REFA and REFB generated by the refresh control circuit 4 (see FIG. 1). For example, at the timing shown in FIG. 7, a negative one-shot pulse is generated in the refresh control signal REFB at a time point (time point t54) after a predetermined time has passed since the refresh control signal REFA was set to the “H” level (time point t53). Self refresh is activated. Then, as described above, these refresh control signals are generated based on the output signal of the refresh timer in the refresh control circuit 4.

Here, in order for the refresh timer to generate its output signal, it is general to divide the output of a ring oscillator (not shown) provided in the semiconductor memory device to produce it. Therefore, in such a configuration, the timing of the refresh control signal depends on the cycle of the ring oscillator. However, the cycle of the ring oscillator can change depending on factors such as the power supply voltage, the external temperature, and the manufacturing process. In particular, the external temperature changes momentarily according to the environment in which the semiconductor memory device is placed. For this reason, it is virtually impossible to predict in advance when self-refresh will be started in response to the refresh control signal. In other words, self-refresh inside the semiconductor memory device starts asynchronously when viewed from the outside of the semiconductor memory device.

On the other hand, as described above, the address Addr
The timing at which ess changes (including the activation of the chip select signal / CS; the same applies hereinafter) is asynchronous when viewed from the semiconductor memory device, and the timing cannot be known in advance. Since both timings are asynchronous with each other in this way, the self-refresh start timing and the address can be determined by simply testing the semiconductor memory device normally.
It is extremely difficult to find a defect that occurs only when the change timing of Address has a specific time relationship.

The following problems can be considered as the problems depending on the timing. As described above, the one-shot pulse is generated in the address transition detection signal ATD when the address Address changes,
In some cases, generating a one-shot pulse may be a noise source inside the semiconductor memory device. That is, when the self-refresh start timing and the address Address change timing overlap, the power supply voltage may transiently drop due to the generation of the one-shot pulse. Then, the pulse of the row enable signal RE (for example, see time t55 in FIG. 7) generated from the refresh control signal REFB by the start of the self-refresh will temporarily drop in the middle (that is, a hazard will occur).

When the level of the row enable signal RE drops, the word line is deactivated, so that the required refresh time cannot be secured sufficiently and the refresh becomes halfway. Such insufficient refresh time causes a problem that the memory cell is refreshed with incorrect data as described below. That is, in order to refresh the DRAM memory cell (similarly for reading), for example, as shown in FIG. 25, the potentials of complementary bit lines (symbol BL and symbol / BL in the figure) forming a bit line pair are set. Both are 1/2 Vc
It is precharged to c and then the word line is activated to read the charge held in the memory cell connected to the word line onto the bit line BL.

By such operation, time t220 in the figure
Since a minute potential difference is generated between the bit lines BL and / BL, the minute potential difference is amplified by the sense amplifier to a potential difference (for example, ground potential / power supply potential Vcc) corresponding to the logic level of "0" / "1". The amplified potential difference is used as a potential difference for rewriting (refreshing) the memory cell. Therefore, if the refresh time becomes insufficient, the memory cell is rewritten with the potential difference (for example, the potential difference from the time t220 to t222) while the minute potential difference is not sufficiently amplified. Therefore, there is a possibility that the data of "0" will be rewritten even though the data of the memory cell should have been originally "1".

In addition to the problems just described,
The noise generated by the generation of the one-shot pulse may cause the following problems. That is, it takes a predetermined time (for example, time t22 shown in FIG. 25) from the activation of the word line to the start of the operation of the sense amplifier.
It is necessary to set a period from 0 to t221). When the noise caused by the one-shot pulse is placed on the bit line pair within this predetermined time, the minute potential difference changes due to the influence of the noise, and the magnitude relation of the potentials between the bit lines BL and / BL is inverted. Can be considered. Then, even if the sense amplifier performs the amplifying operation, the memory cell cannot be refreshed with the correct data stored in the memory cell.

Since it is not possible to ship chips having the above defects as they are, no matter what kind of time relationship the self-refresh start timing and the address change timing have, it is a problem. Must be guaranteed that no It should be noted that the fundamental solution is to eliminate the noise source, for which measures such as strengthening the power supply and dividing the power supply system into multiple parts are considered effective. However, even if such measures are taken, noise is not always completely removed. Therefore, it is naturally necessary to verify whether or not the defect has been eliminated.

Therefore, in this embodiment, according to an instruction from outside the semiconductor memory device (a tester device as a specific example),
Self refresh start timing and address Addr
The time relationship with the change timing of ess is changed to verify the presence or absence of the above defects. By the way, some general-purpose DRAMs perform self-refreshing, but the general-purpose DRAM does not adopt a configuration for generating a one-shot pulse signal in response to an address change. It never happens. In that sense, the problem of verifying such a problem is peculiar to the semiconductor memory device of the SRAM specification using the DRAM memory cell as in the present invention.

In the following, the specific configuration will be described by taking as an example the case where the technical idea of the present invention is applied to the configuration of the first embodiment. FIG. 26 is a block diagram showing the configuration of the semiconductor memory device according to the present embodiment, in which the same signal names and components as those shown in FIG. 1 are designated by the same reference numerals. Therefore, explaining the difference from FIG. 1,
In this embodiment, the multiplexer 26 is added to the configuration of FIG.
1, a NOR gate 262 and an inverter 263 are added, and a test mode signal MODE and a refresh control signal EXREFB supplied from the tester device are added as input signals. Further, the test mode signal MODE and the refresh control signal EXREFB are further supplied to the refresh control circuit 4 shown in FIG. 1 to add a function based on these signals (details will be described later).
The refresh control circuit 304 is obtained by performing the above.

Here, the test mode signal MODE is a test mode entry signal for shifting the semiconductor memory device from the normal operation mode to the test mode, and the refresh control signal EXREFB is for starting refresh from the outside of the semiconductor memory device. It is a signal. Also, FIG.
In this case, the refresh control signals REFA and REFB are supplied to the multiplexer 5 and the row control circuit 13, but in the present embodiment, instead of these, the refresh control signal R
EFA 'and REFB' are supplied to the multiplexer 5 and the row control circuit 13.

Next, when the test mode signal MODE is at the "H" level, the multiplexer 261 selects the refresh control signal EXREFB and outputs it as the refresh control signal REFB '.
If DE is at "L" level, the refresh control signal REFB is selected and output as the refresh control signal REFB 'as in the first embodiment. Next, the circuit including the NOR gate 262 and the inverter 263 forcibly sets the refresh control signal REFA ′ to the “L” level regardless of the level of the refresh control signal REFA when the test mode signal MODE is at the “H” level. .
On the other hand, if the test mode signal MODE is at "L" level, the refresh control signal REF is the same as in the first embodiment.
A is directly output as the refresh control signal REFA '. Next, when the test mode signal MODE is at “H” level, the refresh control circuit 304 counts up the internal address counter by “1” at the rising edge of the refresh control signal EXREFB and updates the refresh address R_ADD. To do.

By thus setting the test mode signal MODE to the "H" level and shifting to the test mode,
A refresh request (refresh triggered by the rise of the address transition detection signal ATD and self refresh by a refresh timer) generated in the semiconductor memory device is invalidated, and refresh control from the outside is validated. Then, in such a state, by supplying a negative one-shot pulse to the refresh control signal EXREFB from the outside, the refresh control signal RE
Refresh is activated and refresh address R_ADD is updated in the same manner as when a negative one-shot pulse is applied to FB. On the other hand, if the test mode signal MODE is set to the “L” level, refreshing is performed by the refresh request generated inside the semiconductor memory device exactly as in the first embodiment.

The test mode signal MODE and the refresh control signal EXREFB are signals used only in the test before shipment, and after shipment, the test mode signal MODE is fixed to "L" level and used. Regarding the refresh control signal EXREFB, if the test mode signal MODE is set to "L" level, it does not affect the operation of the semiconductor memory device, but it is fixed to either "H" level or "L" level before use. . However,
As described below, this does not apply if the pins of the refresh control signal EXREFB are also used as existing pins such as the output enable signal OE pin.

As a pin for inputting the test mode signal MODE and the refresh control signal EXREFB, an unused pin (NC; No Connection) may be assigned. Since most large-capacity SRAMs have unused pins, it is rarely necessary to increase the number of pins just for refresh control from the outside. Further, the refresh control signal EXREFB may be used also as a signal that is not used at the time of refreshing among existing signals. As candidates of such signals, the output enable signal OE described above and a selection signal UB (Up
per Byte), LB (Lower Byte) (Neither is shown)
And so on. Incidentally, in FIG. 26, the refresh control signals REFA and REFB are directly fed to the multiplexer 26.
Although it is input to 1 etc., a buffer may be interposed.

Next, the operation of the semiconductor memory device having the above structure will be described. Here, the operation when the test mode signal MODE is set to the “L” level is exactly the same as the operation of the first embodiment, and therefore will not be repeated. Therefore, here, the operation in the test mode when the test mode signal MODE is set to the “H” level will be described in detail. FIG. 27 shows the timing of the signal supplied from the tester device to the semiconductor memory device as the refresh address R_ADD.
3 is a timing chart shown together with FIG. Also, FIG.
8 is a flow chart showing the test procedure of the semiconductor memory device executed in the tester device.

First, if the chip originally has a fixed defect or a memory cell having poor hold characteristics,
Since it is meaningless to perform the refresh operation test, the hold test is performed in advance (step S1 in FIG. 28). The hold test itself may be performed according to the same test procedure as that performed in the general-purpose DRAM. That is, when data is written in the memory cell array 6 and read is performed after continuing the state in which the refresh is prohibited for a predetermined time, the read data matches the written data for the predetermined time (that is, refresh cycle). Is adjusted, the value of the refresh cycle that matches the memory cell with the shortest hold time is determined. At this time, in the present embodiment, the test mode signal MODE and the refresh control signal E
By setting both XREFB to the “H” level, both refresh operations by an internally generated refresh request and an external refresh request are not performed at all, so that the state in which the refresh is prohibited can be easily realized. it can.

Next, the tester device writes a test pattern in advance in the memory cell array 6 in order to verify later (specifically, in step S13) whether or not the refresh operation was performed correctly (step S13). S
2). Since the purpose here is to verify the normality of the refresh operation, all bits are "1" (that is,
A test pattern of data corresponding to a state where each memory cell holds a high potential) is used.

Next, the tester device uses the test mode signal MO.
DE is changed to "H" level to shift the semiconductor memory device to the test mode (step S3; time t in FIG. 27).
230). If the refresh control signal EXREFB is at the “L” level when the test mode signal MODE is set at the “H” level, refreshing will be performed immediately. Therefore, the tester device sets the test mode signal MODE to the “H” level. Refresh control signal E at the same time
XREFB is transited to the “H” level. However, the refresh control signal EXREFB may be set to the “H” level before the test mode signal MODE is set to the “H” level.

With this setting, the refresh control signal REFA 'becomes "L" level inside the semiconductor memory device, so that refresh is activated inside the semiconductor memory device even if a one-shot pulse is generated in the address transition detection signal ATD. It will not happen. Further, since the multiplexer 261 selects the refresh control signal EXREFB, the operation does not affect the refresh timer in the refresh control circuit 304 in any state. Then, the refresh control signal EXRE
Refresh is performed only when a negative one-shot pulse is applied to FB. The tester device continues to maintain the test mode signal MODE at the "H" level during the test period.

Next, the tester device initializes the value of the time T to, for example, "-10 ns" (step S4). The time T mentioned here is a time that defines at what timing the address Address is changed with reference to the time point when the refresh control signal EXREFB falls. If the time T is a negative value, it means that the address Address is changed at a time point "-T" before the refresh control signal EXREFB falls. On the other hand, if the time T is a positive value, it means that the address Address is changed after the time T has passed since the refresh control signal EXREFB was dropped. In the present embodiment, by changing the time T in increments of "1 ns" within the range of "-10 ns" to "+10 ns", a problem occurs due to the time relationship between the change timing of the address Address and the refresh start timing. I am investigating whether or not.

Next, the tester device initializes the value of the refresh count R to "0" (step S5). As will be described later, in the present embodiment, the value of the time T is refreshed a predetermined number of times (usually, the number of refreshes corresponding to the number of word lines) to refresh the entire memory cell array 6. That is, the refresh count R corresponds to a counter for storing the refresh count performed for each value of the time T.
In this embodiment, the number of word lines is "5" as an example.
12 "book.

Next, at time t231, the tester device changes the value of the address Address to generate a positive one-shot pulse in the address change detection signal ATD (step S6). Where the address before and after the change
Address may be any value, and any bit of address Address may be changed. However, since the address Address is changed for the purpose of generating noise, it is desirable that the change pattern of the address Address is a pattern in which noise is most likely to occur and the noise is large. Therefore, the change pattern of address Address is address A
A pattern that reverses all bits of the ddress at the same time is preferred.

Next, the tester device sets the time T initialized in step S4 (correctly, the time T may be negative, so the absolute value of the time T) in a timer (not shown) inside the tester device (step S7). ) Do. Then, the tester device does nothing and waits until this time (“10 ns” at this point) elapses (“NO” in step S8). Then, when “10 ns” has elapsed from time t231, time t
When it becomes 232 (step S8 is "YES"), the tester device shifts the refresh control signal EXREFB to "L" level to start the refresh operation (step S9). At this point, the refresh control circuit 30
The address counter in 4 is the refresh address R_ADD
"R1" as the value of R1 (0 to 511 [decimal])
Is output.

After this, when a predetermined time has passed from time t232 and time t233 is reached, the tester device returns the refresh control signal EXREFB to the "H" level to end the refresh operation (step S10). The predetermined time is, for example, from time t54 to t when the refresh control signal REFB is set to the "L" level in FIG.
It should be the same time as 56. At time t234, the refresh control circuit 304 updates the value of the refresh address R_ADD to "R1 + 1" in preparation for the next refresh in response to the rising of the refresh control signal EXREFB inside the semiconductor memory device.

Thus, the times t230 to t described above
The detailed operation during 234 is, for example, time t53 to time t53 in FIG.
The operation in 57 is basically the same. However, in the present embodiment, the refresh address R_ADD is not updated at the timing of the fall of the address transition detection signal ATD as in the first embodiment, but when the test mode signal MODE is at “H” level. The refresh address R_ADD is updated when the refresh control signal EXREFB rises.

On the other hand, the tester device uses the refresh address.
In response to the update of R_ADD, the value of the refresh count R is increased by "1" (step S11), and then it is determined whether or not refresh has been performed by the number of word lines. In this case, since the refresh has only been performed once (step S12 is "NO"), the tester device returns the process to step S6 and does not change the value of the time T, as described above. Process. That is, the address Address is changed at time t235, and then 10
At time t236 when ns has elapsed, the refresh control signal E
XREFB is transited to the “L” level and the address “R1” is set.
The refresh operation is started for +1 ". Then, after a predetermined time has elapsed, the refresh control signal EXRE
After returning FB to "H" level, the refresh address R_ADD is updated to the next address.

After that, the 512th word line (in FIG. 27, the refresh address R_ADD is "R1-
1)) is completed at time t241 (step S12 is “YES”), and the same operation is repeated. Incidentally, in FIG.
The refresh address before and after 1 is simply "R1-1",
It is written as "R1 + 1". However, to be precise, if the value of the address R1 is "0", the address "R1-1"
Is 511 (decimal number), and if the value of the address R1 is "511" (decimal number), the address "R1 +
The value of "1" becomes "0".

When the refresh of the entire memory cell array 6 is completed as described above, the tester device verifies whether or not the refresh operation is defective due to the noise caused by the address change. Therefore, the tester device sequentially verifies the test pattern written in step S2 while reading the data sequentially from the memory cell array 6 (step S13). As a result, any one of the data does not match (step S14).
Is "NG"), the tested chip is a defective product in which the above-mentioned defect has occurred, and therefore it is classified as a chip for disposal (step S15).

For convenience of illustration, in FIG. 28, all the memory cells may be collated in step S13, and then the check result may be determined in step S14. However, from the viewpoint of test time, if even one memory cell whose matching result does not match is detected, the chip is discarded without performing matching for the remaining memory cells (step S
Of course, there is no problem even if it is judged as 15).

On the other hand, if all the data match as a result of the collation in step S13 ("OK" in step S14), no problem occurs for the time T of "-10 ns". The device increases the time T by, for example, "1 ns" (step S16).
After that, it is determined whether this time T has reached a predetermined value. In the present embodiment, the test is executed up to “+10 ns”, so this predetermined value is “+11 ns”.

At this time, the time T is "-9n".
s ”(step S17 is“ NO ”), the tester device returns the process to step S5 and repeats the same process as described above (time t243 to t243).
250). The difference between the operation in this case and the above-described operation is "9 ns" from when the address Address is changed to when the refresh control signal EXREFB falls (for example, at the time t243 in the test on the first word line).
~ T244).

The tester device thus sets the time T to "1 ns".
The test is performed for each individual value of the time T while increasing the value. Then, if there is a defect in refresh due to the influence of noise due to a change in the address Address, this defect is detected by the memory check (step S13). On the other hand, if such a defect is not detected and the check result of step S14 is "OK" for all times T within the range of "-10 ns" to "+10 ns", the determination of step S17 is finally made. The result is "YES", and it can be determined that the semiconductor memory device under test is a normal chip (non-defective product) that is not affected by noise due to a change in address Address.

In the above operation, when the value of the time T is "0", the tester device changes the address Address and, at the same time, refresh control signal EXREFB.
Will be shut down. That is, in this case, the tester device omits the processes of steps S7 to S8 in FIG. 28 and simultaneously performs the processes of steps S6 and S9. On the other hand, when the time T is a positive value, the tester device first causes the refresh control signal EXREFB to fall, and then when the time T elapses, the address Address
To change. That is, in this case, the process of step S6 and the process of step S9 in FIG. 28 are replaced with each other.

As described above, in this embodiment, the timing of the refresh control signals REFA 'and REFB' can be controlled from outside the semiconductor memory device, and the refresh start timing and the normal read / write operation timing due to the address change. The time relationship between and is variable. For this reason, it is possible to verify before shipment that a defect due to the influence of noise caused by an address change does not occur over the entire time range that can be taken as the time relationship between them.

By the way, in the above description, the time T is "-".
“1n” within the range of 10 ns ”to“ +10 ns ”
The value is changed in s ″ increments, but this is merely an example until the user gets tired, and it goes without saying that the time range for varying the time T and the time value of the step width may be appropriately determined in accordance with each semiconductor memory device.

In the above description, the present invention has been described on the premise of the first embodiment, but the same applies to the case where the present invention is applied to the second to sixth embodiments. That is, in these embodiments, the refresh control circuit 304 (refresh control circuit 204), the multiplexer 5, the row control circuit 13 (the row control circuit 313, the row control circuit 35).
The connection relationship between 3) is exactly the same as in the first embodiment.
Therefore, the same modification as that of the configuration of FIG. 1 may be added to the configuration of FIG. 12, FIG. 14, FIG. 17, FIG. 23 or FIG.

In each of the above-described embodiments, the refresh is performed from the rising edge of the one-shot pulse generated in the address transition detection signal ATD, but the logic of the one-shot pulse is inverted and the refresh is started from the falling edge. You may make it refresh. This is exactly the same for each signal other than the address transition detection signal ATD.

Further, in each of the above-described embodiments, each memory cell such as the memory cell array 6 is composed of one transistor and one capacitor, but the structure of the memory cell is not limited to such a form. Certainly, such a memory cell is most preferable in terms of chip size and the like, but the semiconductor memory device of the present invention does not deny the use of memory cells other than one transistor and one capacitor. That is, if the DRAM memory cell has a smaller configuration than the memory cell of the general-purpose SRAM, one transistor 1
Even if the capacitor configuration is not used, there is an effect that the chip size can be reduced compared to a general-purpose SRAM.

In addition, the semiconductor memory device according to each of the above-described embodiments may have a configuration in which the entire circuit shown in FIG. 1, for example, is mounted on a single chip. It may be divided into some functional blocks, and each functional block may be mounted on a separate chip. An example of the latter is a mixed IC (integrated circuit) in which a control part for generating various control signals and address signals and a memory cell part are mounted on different chips (control chip and memory chip). That is, a configuration in which various control signals are supplied to the memory chip from a control chip provided outside the memory chip also belongs to the scope of the present invention.

[0291]

As described above, according to the first aspect of the present invention, the address change detection signal is generated in response to the input address signal, and the memory corresponding to the refresh address signal is generated in response to the address change detection signal. Cell refresh and memory cell access corresponding to an input address signal are performed in this order.

As described above, since the access is performed after the refresh, the refresh can be put into one memory cycle even when the writing is continuous. Further, for example, when writing to a memory cell, refresh and writing do not conflict even if the write enable signal is input with a delay, so that the timing design can be simplified and the circuit scale is not increased. Complete.

Even when the input address signal includes a skew, a plurality of address transition detection signals are generated and the data in the memory cell is destroyed because each bit of the input address signal changes at different timings due to the skew. The fear of being killed disappears. In addition, since it is not necessary to take measures such as delaying the start of access to the memory cell in order to avoid such a problem of memory cell destruction, it is possible to achieve high speed without causing delay inside the semiconductor memory device. Becomes

The semiconductor memory device according to the first aspect of the invention includes a semiconductor memory device which uses a row address and a column address generated from an input address signal to access a memory cell indicated by the input address signal. Be done.
Therefore, unlike the general-purpose DRAM, it is not necessary to take in the address in two times in accordance with the RAS / CAS timing signal, and the input address signal only needs to be given at one time. The circuit configuration for doing so can be simplified. Further, since the refresh operation is performed in one memory cycle accompanying the input of the input address signal from the outside of the semiconductor memory device, if the input address signal is applied as much as necessary to refresh all the memory cells, the semiconductor memory Since the data in the memory cell can be held continuously without performing the refresh control from the outside of the device, it is easy to handle like a general-purpose SRAM.

If a one-transistor one-capacitor device such as DRAM is used as the memory cell, a general-purpose S
Since the cell area can be significantly reduced as compared with the case where the RAM requires 6 transistors per memory cell, the chip size can be reduced and the cost can be reduced while increasing the capacity. According to the first aspect of the invention, the change of the input address signal is used as a trigger to fetch the input address signal and access the memory cell. Therefore, unlike the existing pseudo SRAM, it is not necessary to change a signal such as a chip enable signal having an address latch timing control function each time an address is taken in, so that power consumption can be reduced accordingly. .

According to the second aspect of the present invention, the upper predetermined bits of the input address signal are used for address change detection, and the upper predetermined bits of the input address signal are higher than a plurality of memory cells having the same upper predetermined bits. These memory cells are continuously accessed by changing the page address composed of bits other than the predetermined bits. This makes it possible to realize the same function as the page mode used in a general-purpose DRAM or the like.

According to the third aspect of the invention, the address change detection signal is generated in response to the activation signal activated when the semiconductor memory device is accessed. As the activation signal, a signal having a chip activation function but no address latch timing control function can be used. As a result, the input address signal is set in advance, and the activation signal is changed from the invalid state to the valid state so that the operation in the semiconductor memory device can be started.

According to the present invention, a one-shot pulse having a pulse width corresponding to a waiting period from when the input address signal starts to change until the input address signal is fixed is generated as the address change detection signal. I am letting you. Further, in the invention according to claim 9, the refresh is performed within the period in which the one-shot pulse is generated. By doing so, refreshing can be performed by effectively utilizing the period originally in the standby period in the general-purpose SRAM. Even when the refresh for one refresh cycle is completed and the refresh is not performed until the next refresh cycle, the one-shot pulse period is only the standby period as in the general-purpose SRAM. Regardless of whether or not it is necessary, the time required for reading from the memory cell can be made constant.

According to the tenth aspect of the present invention, when the write enable signal is input during the refreshing period, the input write data is fetched into the bus and the writing is performed after the refreshing is completed. Data is written to the memory cell from the bus. Further, in the twelfth aspect of the invention, when the address change detection signal is generated during the self-refresh, the input address signal is accessed after the self-refresh. By doing so, even if the input address signal is applied during the self refresh, the input address signal does not affect the self refresh, and the operation is always performed after the self refresh is performed. The logic design work required for timing control can be simplified.

According to the eleventh aspect of the present invention, the self-refresh is activated when the address transition detection signal is not generated for a predetermined time, and the refresh is performed at regular time intervals. Normally, the memory cell is refreshed accompanying the input address signal given at a certain frequency, but by doing so, in the case where the input address signal is not provided for a long time. Even if there is, it is possible to continue holding the data stored in the memory cell.

In the thirteenth aspect of the present invention, the one-shot pulse corresponds to the rising or falling edge of 2
Of the types of change points, another change point that is different from the change point that triggers the refresh is used as a trigger to update the refresh address. As a result, when the input address signal is newly changed and the next memory cycle is started, the refresh address is already set in the immediately preceding memory cycle even if the input address signal includes a skew. The selection operation of the memory cell (word line) to be refreshed is not delayed due to the influence of skew, and delay is not generated in refresh.

According to the sixteenth aspect of the invention, the refresh operation in the semiconductor memory device can be freely controlled from the outside by inputting the test mode signal and inputting the input refresh request at a desired timing. . Therefore, for example, the one-shot pulse generated from a change in the input address signal causes noise in the row enable signal that controls refresh, or the sense operation of the sense amplifier starts after the word line is activated. It is possible to verify the existence of a defect caused by noise being applied to the bit line pair in the meantime. In addition, if the test mode signal is set to supply a refresh request from the outside and the refresh request is not input from the outside, no refresh will be performed in the semiconductor memory device. It is possible to easily realize the state of prohibiting.

According to the seventeenth aspect of the invention, the input refresh request is given through a pin that is not used during refresh. By doing so, the pin for giving the input refresh request can be shared with the pin for inputting the output enable signal. Therefore, it is not necessary to allocate a new pin just to provide an input refresh request.

In the nineteenth aspect of the invention, the reading or writing is performed after refreshing. Furthermore, in the invention of claim 20, when a write request is input, refresh is performed before writing to the memory cell, and when a read request is input, read is performed and then refresh is performed. The latter makes it possible to speed up reading and improve the access time. For that purpose, it is preferable that the read / write is determined when a predetermined time has elapsed after the input address signal changes, as in the twenty-first aspect of the invention.

According to the twenty-second aspect of the present invention, a predetermined test pattern is written in the memory cell array,
Disables all refreshes due to refresh requests generated inside the semiconductor memory device, sets the timing of changing the input address signal and the timing of supplying the input refresh request to a certain time relationship, and requests the input refresh while changing the input address signal. Is supplied to refresh the memory cell array, and the test pattern written in advance is compared with the data in the memory cell array to determine the quality of the semiconductor memory device. This allows
Due to the influence of the address change detection signal (one-shot pulse) generated from the change of the input address signal, noise may occur in the row enable signal that controls refresh, or the sense operation of the sense amplifier may not be performed after the word line is activated. It is possible to verify the existence of a defect caused by noise on the bit line pair before the start.

According to the twenty-third aspect of the invention, the time relationship between the change timing of the input address signal and the supply timing of the input refresh request is made variable over a predetermined time range. For example, by setting all the time ranges considered to be possible as the time relationship between the two timings to the predetermined time range, no matter what the time relationship between these timings becomes, the problem caused by the noise is It can be guaranteed not to occur.

According to the twenty-fifth aspect of the invention, when the input address signal is changed, all the bits of the input address signal are inverted at the same time. By doing so, the row enable signal, the bit line pair, and the like are likely to have noise and the magnitude of the noise is increased, so that it is possible to verify whether or not a problem will occur even under such severe conditions.

Next, in the twenty-sixth aspect of the present invention, when in the standby state, each circuit in the device required for self-refreshing is provided for each circuit according to a mode selected from a plurality of types of modes. The operation is performed or the operation is stopped. As a result, it is not necessary to operate an unnecessary circuit for refreshing, so that power consumption can be reduced.
Therefore, a general-purpose SRAM specification memory using memory cells that need refreshing, a pseudo SRAM, a general-purpose DR
In the AM or the like, a low power consumption mode similar to the standby mode in the general-purpose SRAM can be realized. Also, since it is possible to control whether each circuit is operated for each circuit required for self-refresh, it is possible to gradually reduce the standby current according to the user's needs and applications. It is possible to realize a unique standby mode.

According to the twenty-seventh aspect of the invention, when the memory cell array is composed of a plurality of memory cell areas whose refresh operations are independently controlled, a mode is set for each memory plate consisting of the memory cell area and its peripheral circuits. Is set to operate each memory plate or stop the operation. As a result, it becomes unnecessary to perform self-refresh in the standby state for the memory cell area in which the information that should be temporarily stored is stored. Therefore, by deciding whether to operate the memory plate according to the allocation of the memory space used by the application, etc., it becomes possible to minimize the standby current in a form that is specific to the user's needs and applications. .

According to the twenty-ninth aspect of the present invention, the power source means shared by the plurality of memory plates is provided, and according to the mode set for each memory plate,
Whether to supply power to each memory plate from the power supply means is individually controlled. As a result, the scale of the power supply means does not increase in proportion to the number of memory plates, so it is possible to reduce the standby current with a small circuit configuration even when a large number of memory plates are provided. Becomes

According to the thirtieth aspect of the invention, the mode can be set for each memory plate by giving an input mode signal for standby. As a result, even if the needs of the user or the application used changes, it is possible to flexibly respond to such changes and minimize the standby current.

According to the thirty-first aspect of the present invention, the memory plate for which the mode is set is specified based on the address input for the mode setting. This allows
Compared with the case where the mode is set by cutting the fuse, the mode can be set easily, and the mode can be easily set again by the user in the same manner as normal reading and writing. Therefore, it is not necessary to externally provide a dedicated signal for mode setting, and it is not necessary to provide a pin for such a dedicated signal.

[0313] In the invention of claim 1 4 Symbol mounting, the first mode, a second mode for operating the power supply circuit stops the operation of the refresh control circuit for operating both the refresh control circuit and power supply circuit, A third mode for stopping the operations of both the refresh control circuit and the power supply circuit is provided so that one of these modes can be selected. As a result, it is possible to externally finely control the necessity of holding data in the standby state, the return time to the active state, the amount of current consumption, etc. according to the applied device and its usage environment. That is, in the first mode, power is supplied to the circuits required for self-refreshing, so that the data in the memory cells can be retained and the time required to shift from the standby state to the active state is the most among the three types of modes. Can be shortened. In addition, in the second mode, the current consumption can be reduced as much as that to be supplied to the refresh control means as compared with the first mode, and when the standby state is changed to the active state, the semiconductor is immediately turned on as in the first mode. A storage device can be used. Further, in the third mode, the current consumption can be minimized among the three types of modes. Further, in the invention of claims 1 to 5 Symbol mounting, when a predetermined data write request to each mode for a given address, or,
The mode is set when there is a predetermined change in the activation signal. As a result, it is not necessary to apply a dedicated signal to the semiconductor memory device to set the standby mode, and it is not necessary to provide a pin for such a dedicated signal in the semiconductor memory device.

A control circuit according to a thirty- fifth to fifty- first aspect of the invention supplies a control signal and an address signal from the outside of the memory chip in which the memory cell is formed, and constitutes the semiconductor memory device described above together with this memory chip. To do. Therefore, claims 32 to 34 , 36 , 37 ,
40, 41, 43 by using a control circuit according to the invention of ~ 47, 49-51, wherein each claim 1
3,11,12,16,17,19 to 21,26,2
The same effects as the above-described effects of the semiconductor memory device according to the invention described in 7, 29 to 31 can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a main part of the semiconductor memory device according to the same embodiment.

FIG. 3 is a timing chart showing an operation when refresh and subsequent read are performed in one memory cycle in the semiconductor memory device according to the same embodiment.

FIG. 4 is a timing chart showing the operation in the semiconductor memory device according to the same embodiment when refresh is not performed from the middle and only reading is performed.

FIG. 5 is a timing chart showing an operation when refresh and subsequent writing are performed in one memory cycle in the semiconductor memory device according to the same embodiment.

FIG. 6 is a timing chart showing the operation in the semiconductor memory device according to the same embodiment when refresh is not performed halfway and only writing or reading is performed.

FIG. 7 is a timing chart showing an operation when self refresh is performed by a refresh timer in the semiconductor memory device according to the same embodiment.

FIG. 8 is a timing chart showing an operation when refresh is performed by a refresh timer and reading is subsequently performed in the semiconductor memory device according to the same embodiment.

FIG. 9 is a timing chart showing refresh, dummy reading, and writing when the write enable signal is input with a delay in one memory cycle in the semiconductor memory device according to the same embodiment.

FIG. 10 shows a semiconductor memory device according to the same embodiment, in which refresh, dummy read, self-refresh and write are performed when a write enable signal is input with a delay after self-refresh is started by a refresh timer in one memory cycle. It is the timing chart shown.

FIG. 11 is a timing chart showing write and subsequent self-refresh when a write enable signal is input with a delay in one memory cycle and a refresh request is made by a refresh timer during write in the semiconductor memory device according to the same embodiment. It is a chart.

FIG. 12 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 13 is a timing chart showing an operation in the semiconductor memory device according to the same embodiment when refresh is not performed from the middle and only reading is performed.

FIG. 14 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 15 is a timing chart showing a read operation of the semiconductor memory device according to the same embodiment.

FIG. 16 is a timing chart showing a write operation of the semiconductor memory device according to the same embodiment.

FIG. 17 is a block diagram showing the structure of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 18 is a circuit diagram showing a detailed configuration of a standby mode control circuit according to the same embodiment.

FIG. 19 is a circuit diagram showing a detailed configuration of a refresh control circuit according to the same embodiment.

FIG. 20 is a circuit diagram showing a detailed configuration of a boost power supply according to the same embodiment.

FIG. 21 is a circuit diagram showing a detailed configuration of a substrate voltage generating circuit according to the same embodiment.

FIG. 22 is a circuit diagram showing a detailed configuration of a reference voltage generation circuit according to the same embodiment.

FIG. 23 is a block diagram showing a configuration of a main part of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration of a main part of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 25 is a timing chart showing how the potentials of the bit line pair BL, / BL transition with time in the sense operation of the DRAM memory cell.

FIG. 26 is a block diagram showing the structure of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 27 is a timing chart showing the timing of signals supplied from the tester device to the semiconductor memory device together with the refresh address R_ADD in the same embodiment.

FIG. 28 is a flow chart showing a test procedure of the semiconductor memory device performed in the tester device in the embodiment.

[Explanation of symbols]

1, 141, 151 Address buffer 2, 142 Latch 3, 143, 163 ATD circuit 4, 164, 204, 304 Refresh control circuit 5, 165, 261 Multiplexer 6 Memory cell array 6 _{1 to} 6 _n Memory cell area 7, 7 ₁ ... 7 _n row decoder 8, 8 ₁ to 8 _n , 148 column decoder 9, 9 _{1 to} 9 _n , 149 sense amplifier / reset circuit 10 I / O buffer 11 R / W control circuit 12 latch control circuit 13, 173, 313, 353 row control circuit 14 column control circuit 15, 15 ₁ , 15 ₂ , 215 boost power supply 16, 16 ₁ , 16 ₂ , 216 substrate voltage generation circuit 17, 17 ₁ , 17 ₂ , 217 reference voltage generation circuit 152 bus decoder 153 bus Selector 201 Standby mode control circuit 262 NOR gate 263 Inver 301, 351 PowerDown control circuit 350 Power supply circuit 352 _{1 to} 352 _n Switch element 354 Program circuit

Continuation of the front page (56) References JP-A-63-155494 (JP, A) JP-A-6-36557 (JP, A) JP-A-11-232876 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) G11C 11/401-11/4099 G11C 29/00

Claims (51)

(57) [Claims] 1. A semiconductor memory device having a plurality of memory cells that require refreshing, comprising: refresh address generating means for generating a refresh address signal corresponding to a memory cell to be refreshed; Address change detection means for generating an address change detection signal, and in response to the address change detection signal, refresh the memory cell corresponding to the refresh address signal, and then to the memory cell corresponding to the input address signal. A semiconductor memory device comprising: a control unit for accessing. 2. The address change detection means generates the address change detection signal in response to an upper predetermined bit of the input address signal, and the control means controls the upper predetermined bit of the input address signal. 7. A plurality of memory cells that are the same are sequentially accessed by changing a page address composed of bits other than the upper predetermined bits of the input address signal. 1
The semiconductor memory device described. 3. The address transition detection means generates the address transition detection signal in response to the input address signal or activation signal, and the activation signal is validated when accessing the semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a selected signal. 4. The semiconductor memory device according to claim 1, wherein the address transition detection signal is a one-shot pulse. 5. The semiconductor memory device according to claim 4, wherein the control means performs the access after performing the refresh, with the generation of the one-shot pulse as one trigger. 6. The address change detection means generates a pulse having a predetermined width in response to a change in each bit of the input address signal used for generating the address change detection signal or a change in an activation signal, and these pulses are generated. 6. The semiconductor memory device according to claim 4, wherein the one-shot pulse is generated by synthesizing 7. The address change detection means generates, as the address change detection signal, a one-shot pulse having a pulse width exceeding the maximum value of the skew included in the input address signal or the activation signal. 7. The semiconductor memory device according to claim 4, wherein: 8. The address transition detection means corresponds to a waiting period from when the input address signal or activation signal starts to change as the address transition detection signal until the input address signal or activation signal is determined. 8. The semiconductor memory device according to claim 4, wherein a one-shot pulse having a pulse width for generating is generated. 9. The semiconductor memory device according to claim 4, wherein the control unit performs the refresh within a period in which the one-shot pulse is generated. 10. The control means inputs, in response to the write enable signal, a write enable signal for activating a write operation for the memory cell, when the write enable signal is input within a period in which the refresh is being performed. 10. The write data to be written is fetched into a write bus, and the write data is written from the bus to the memory cell after the refresh is completed. 10. Semiconductor memory device. 11. The control means activates self-refresh when the address transition detection signal is not generated for a predetermined time, generates an internal refresh request at a constant time interval, and performs the refresh. The semiconductor memory device according to claim 1, wherein 12. The control means, when the address change detection signal is generated during refreshing by the self refresh, performs the self refresh and then accesses the input address signal. The semiconductor memory device according to claim 11, which is characterized in that. 13. The one-shot pulse is a first trigger for the refresh and the access, respectively.
Has a change point and a second change point, the refresh address generating means, any one of claims 4-9, characterized in that as a trigger the second change point updating the refresh address signal The semiconductor memory device according to the item. 14. A refresh control means including a circuit portion in the control means for controlling the refresh and the refresh address generating means, and a voltage for generating a voltage to be supplied to a predetermined circuit in the semiconductor memory device. Generating means, a first mode in which power is supplied to both the refresh control means and the voltage generating means, and a second mode in which power supply to the refresh control means is stopped and power is supplied to the voltage generating means , Switching to any of the third modes for stopping the supply of power to both the refresh control means and the voltage generating means, and supplying power to the refresh control means and the voltage generating means in accordance with the switched mode. And a mode switching means for controlling whether or not to perform each, The semiconductor memory device according to any one of claims 1 to 13 that. 15. The mode switching means switches the mode in response to a request to write predetermined data for each mode to a predetermined address. Semiconductor memory device. 16. The control means selects either an input refresh request or an internal refresh request generated based on the address transition detection signal in response to an input test mode signal, and the selection is performed. 16. The semiconductor memory device according to claim 1, wherein the refresh is performed according to the refresh request. 17. The semiconductor memory device according to claim 16, wherein the input refresh request is input through a pin that is not used during the refresh. 18. The semiconductor memory device according to claim 1, wherein the refresh address generation means updates the refresh address signal each time refresh is performed. 19. The control means, in response to the address change detection signal, refreshes a memory cell corresponding to the refresh address signal and then reads or writes the memory cell corresponding to the input address signal. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is performed. 20. When the write request is input, the control means responds to the address change detection signal, refreshes a memory cell corresponding to the refresh address signal, and then responds to the input address signal. When a read request is input, the memory cell corresponding to the input address signal is read in response to the address change detection signal, and then the refresh address signal is responded to. 19. The semiconductor memory device according to claim 1, wherein the memory cell is refreshed. 21. The control means determines whether the input access request is a read request or a write request when a predetermined time has elapsed since the input address signal changed. Claim 20
The semiconductor memory device described. 22. A test method for testing the semiconductor memory device according to claim 1, wherein a predetermined test pattern is written in a memory cell array composed of the plurality of memory cells. Setting a predetermined time relationship between a step of prohibiting all refreshing by a refresh request generated inside the memory device, a timing of changing the input address signal and a timing of applying the input refresh request to the semiconductor memory device, and A step of refreshing the memory cell array by giving the input refresh request while changing an input address signal; and comparing the data read from the memory cell array with the test pattern,
A method of testing a semiconductor memory device, comprising: a step of determining a defect. 23. The semiconductor memory device test according to claim 22, further comprising the step of varying the time relationship between the change timing and the input refresh request giving timing over a predetermined time range. Method. 24. The method according to claim 22, further comprising the step of sequentially performing the refresh on all the word lines on the memory cell array while keeping the time relationship constant. Test method of semiconductor memory device. 25. The semiconductor memory device testing method according to claim 22, wherein all bits of the input address signal are inverted at the same time when the input address signal is changed. . According 26. Before SL selected mode from among a plurality of types of modes whether to operate is defined for each circuit in each circuit standby state in the device required for refresh and became the standby state when the refresh operating each circuit in the apparatus required for, or any claim 1 to 13, characterized by comprising an operation control means for stopping their operation
The semiconductor memory device as described in the paragraph . 27. The memory cell array composed of the plurality of memory cells is divided into a plurality of memory cell areas in which whether or not to perform the refresh is independently controlled when in the standby state, The operation control means operates each of the memory plates according to the mode set for each memory plate including the memory cell area and a peripheral circuit necessary for refreshing the memory cell area, or The operation is stopped, wherein the operation is stopped.
6. The semiconductor memory device according to 6. 28. Each of the memory plates further comprises a power supply means for supplying power to the memory cell area and the peripheral circuit forming the memory plate, and the operation control means is set for each of the memory plates. 28. The semiconductor memory device according to claim 27, wherein the power supply means provided for each of the memory plates is operated or stopped according to the mode. 29. Power supply means shared between the plurality of memory plates for supplying power to the plurality of memory plates is provided, and the operation control means comprises the mode set for each of the memory plates. 28. The semiconductor memory device according to claim 27, further comprising a plurality of switch means for controlling, for each memory plate, whether or not power is supplied from the power supply means to each of the memory plates. 30. The semiconductor memory according to claim 27, further comprising programming means for setting the mode for each of the memory plates in response to an input mode signal. apparatus. 31. The program means specifies a memory plate having a memory cell area corresponding to the input address based on the input address, and determines the mode specified by the input mode signal to the specified memory. 31. The semiconductor memory device according to claim 30, wherein the semiconductor memory device is set as a mode for a plate. 32. A control circuit for supplying an address signal to a selecting means for selecting a memory cell requiring refresh, the refresh address generating means generating a refresh address signal in response to a change in an input address signal, An address switching unit for outputting the refresh address signal to the selecting unit and then outputting the input address signal to the selecting unit. 33. The address switching means continuously accesses a plurality of memory cells having the same upper predetermined bits while changing a page address composed of bits other than the upper predetermined bits of the input address signal. 33. The control circuit according to claim 32 , wherein the control circuit outputs an address signal to the selecting means. 34. The refresh address generating means, control circuit according to claim 32 or 33, characterized in that to generate the refresh address signal in response to the input address signal or activation signal. 35. The address switching means outputs the refresh address signal to the selecting means and then outputs the input address signal to the selecting means by using a change of the input address signal as one trigger. control circuit according to any one of claims 32-34, characterized. 36. The refresh address generating means activates self-refresh when the input address signal has not changed for a predetermined time, and generates the refresh address signal at a constant time interval. The control circuit according to any one of 32 to 35 . 37. The address switching means, when the input address signal changes during refreshing by the self-refresh, sends the input address signal to the selecting means after the self-refreshing is performed. 37. The control circuit according to claim 36 , which outputs. 38. A refresh control unit that includes at least the refresh address generation unit and controls the refresh, a voltage supplied to a predetermined circuit including the refresh control unit and the memory cell and the selection unit is generated. A first mode in which power is supplied to both of the voltage generating means, and a second mode in which power supply to the refresh control means is stopped and power is supplied to the voltage generating means.
Mode, and mode control means for generating a mode switching signal for switching to any one of the third modes for stopping the supply of power to both the refresh control means and the voltage generation means. The control circuit according to any one of claims 32 to 37 , wherein: 39. The mode control means according to claim 38, wherein the mode control signal is generated in response to a write request for writing predetermined data for each mode to a predetermined address. Control circuit. 40. A refresh request selecting unit is further provided for selecting either an input refresh request or an internal refresh request generated based on a change of the input address signal in response to an input test mode signal. The address switching means outputs the input address signal as the refresh address signal to the selecting means or outputs the refresh address signal as it is to the selecting means according to the selected refresh request. The control circuit according to any one of claims 32 to 39 . 41. The control circuit of claim 40, wherein the input refresh request is input through a pin that is not used during the refresh. 42. The refresh address generating means, according to claim 32 to 41, characterized in that updating the refresh address signal every time to perform the refresh
The control circuit according to any one of 1. 43. The address switching means outputs the refresh address signal to the selecting means and then outputs the input address signal to the selecting means regardless of whether a write request or a read request is input. The control circuit according to any one of claims 32 to 42 , wherein: 44. When a write request is input, the address switching unit outputs the refresh address signal to the selecting unit in response to the address change detection signal, and then the input address to the selecting unit. When the read request is output, the input address signal is output to the selecting means and then the refresh address signal is output to the selecting means in response to the address transition detection signal. Claims 32 to 4
2. The control circuit according to any one of items 2 . 45. The address switching means determines whether the input access request is a read request or a write request when a predetermined time has elapsed since the input address signal changed. The control circuit according to claim 44 . According 46. A mode whether to operate in the refresh standby state of each circuit that Do required of the memory cell is selected from among a plurality of types of modes defined for each circuit, has become the standby state 38. The control circuit according to any one of claims 32 to 37 , wherein each circuit required for the refresh is operated or stopped at the same time. 47. It is set for each memory plate including a memory cell area in which whether or not to perform the refresh is independently controlled when in the standby state and a peripheral circuit necessary for refreshing the memory cell area. 47. The control circuit according to claim 46 , wherein each of the memory plates is operated or its operation is stopped according to the mode. 48. A power supply unit provided for each memory plate is operated to supply power to the memory cell area and the peripheral circuit according to the mode set for each memory plate, or 48. The control circuit according to claim 47, which stops its operation. 49. According to the mode set for each of the memory plates, a power supply unit shared between the plurality of memory plates for supplying power to the plurality of memory plates is used to supply the power to the memory plates. 48. The control circuit according to claim 47 , further comprising a plurality of switch means for controlling whether or not power is supplied to each of them. 50. In response to the input mode signal, the control circuit according to said mode to any one of claims 47-49, characterized in that it comprises program means for setting for each of the memory plate . 51. The program means specifies a memory plate having a memory cell area corresponding to the input address based on the input address, and specifies the mode specified by the input mode signal to the specified memory. The mode is set as a mode for the plate.
50. The control circuit according to item 50 .