JP2006351140A - Semiconductor memory device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance manufacturing yield by providing a redundant memory cell and to accelerate an operation speed in a semiconductor memory device. <P>SOLUTION: In the case that write access corresponding to an input address in a first access cycle wherein a write enable signal from the outside has been put into an active state, is executed after read access corresponding to an input address in a second access cycle next to the first access cycle, an address output from a redundant address setting circuit in the second access cycle is latched and is output as an access object address when executing the read access, and an address which has been latched before execution of the read access and is output from the redundant address setting circuit in the first access cycle is output as an access object address when executing the write access. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device having a memory cell array in which dynamic memory cells are arranged in a matrix, and more particularly to a semiconductor memory device capable of replacing a defective memory cell with a redundant memory cell.

  A virtual SRAM (VSRAM, Virtually Static RAM) is known as a semiconductor memory device developed to have both the advantages of DRAM and SRAM. A virtual SRAM (also referred to as “pseudo SRAM (PSRAM)”) includes a memory cell array including dynamic memory cells that are the same as those of a DRAM and has a built-in refresh timer to perform a refresh operation internally. Running. Therefore, an external device (for example, a CPU) connected to the virtual SRAM can perform read access (data read) and write access (data write) to the virtual SRAM without being aware of the refresh operation. .

  Further, in the semiconductor memory device, a spare memory cell called a redundant memory cell is provided in advance, and a defective memory cell generated in the original memory cell array is replaced with the redundant memory cell, so that the manufacturing yield of the semiconductor memory device is increased. In general, a redundant technique for improving the above is employed, and is also employed in the virtual SRAM.

  For example, Patent Documents 1 and 2 describe the redundancy technology in the semiconductor memory device.

JP-A-8-83495 JP 2003-68071 A

  By the way, the semiconductor memory device adopting the above redundancy technique has a problem in terms of operation speed as described below.

  FIG. 8 is an explanatory diagram showing an example of the flow of write access processing in the virtual SRAM employing the redundancy technique. Note that the rectangles indicated by the double-lined frames in the figure indicate the periods during which the corresponding signals are generated (active periods),

  As shown in FIG. 8, when the write enable signal #WE changes from the active state to the inactive state, the write request signal RQWA is generated accordingly. In addition, an address transition signal ATD (hereinafter also referred to as “ATD signal”) is generated in the virtual SRAM in response to a change in the input external address (input address) ADD, and a read access request signal is generated accordingly. RQRA occurs.

  When the read access request signal RQRA is generated, the read access execution signal ACTRA is preferentially generated and the read access is executed even if the write access request signal RQWA has been generated. This read access is executed in the order of redundancy determination, access target address setting, word line (WL) activation and deactivation. In this redundancy determination, it is determined whether the address specified by the input address is an address of a defective memory cell and corresponds to an address that has been replaced in advance by a redundant memory cell. An address corresponding to the redundant memory cell is output.

  Then, after the end of the read access, the write access execution signal ACTWA is generated to execute the write access. Similar to the read access, this write access is executed in the order of redundancy determination, setting of an access target address, activation and deactivation of the word line.

  As shown in FIG. 8, in the case where read access is executed before actually executing write access, the minimum value allowed as cycle time Tcw for write access (hereinafter also referred to as “minimum cycle time”). Tcw <min> is the time required for actual read access (hereinafter also referred to as “read access time”) Tra and the time required for actual write access (hereinafter also referred to as “write access time”). It is expressed as the sum of Twa. Therefore, there is a problem that the minimum cycle time Tcw <min> for write access becomes longer by the amount including the read access time Tra.

  In addition, since the read access time Tra and the write access time Twa include a time Tdj for determining redundancy for each corresponding input address, when more redundant memory cells are provided to improve the yield As the number of redundancy determination targets increases, the time Tdj for redundancy determination increases and the respective access times Tra and Twa become longer. As a result, the minimum cycle time Tcw <min> for write access is further increased. The problem of getting longer.

  This problem is not only a virtual SRAM but also a problem common to semiconductor memory devices that have a memory cell array in which dynamic memory cells are arranged in a matrix and employ a redundancy technique.

  The present invention has been made to solve the above-described conventional problems. In a semiconductor memory device such as a virtual SRAM, the present invention aims to improve the yield by providing redundant memory cells and to improve the operation speed. The purpose is to provide a technology that can do this.

In order to achieve at least part of the above object, a semiconductor memory device according to the present invention includes:
A semiconductor memory device in which read access or write access is executed based on an address change of an external input address,
A memory cell array including a standard memory cell array unit in which memory cells are arranged in a matrix, and a redundant memory cell array unit having a redundant memory cell replaced with a defective memory cell in the standard memory cell array unit;
A circuit for outputting an address for specifying a memory cell in the memory cell array based on the input address, and the standard memory cell array corresponding to the input address in the standard memory cell array unit is the defective memory cell. In this case, it is determined in advance whether the memory cell has been replaced by the redundant memory cell in the redundant memory cell array unit, and if so, a redundant address corresponding to the replaced redundant memory cell is output. If not, a redundant address setting circuit for outputting a standard address corresponding to the standard memory cell;
An address setting circuit that latches an address output from the redundant address setting circuit and outputs an access target address corresponding to a memory cell to be accessed in the memory cell array,
The address setting circuit includes:
When an external write enable signal is in an active state in a certain first access cycle, after executing a read access corresponding to the input address in the second access cycle in the next second access cycle, When performing a write access corresponding to the input address in the first access cycle,
When the read access is executed, the address output from the redundant address setting circuit is latched and output as the access target address in the second access cycle, and when the write access is executed, the address is latched before the read access is executed. The address output from the redundant address setting circuit in the first access cycle is output as the access target address.

  According to the semiconductor memory device, at the time of write access execution after execution of read access in the second access cycle, the address output from the redundant address setting circuit in the first access cycle and latched before execution of read access is accessed. It can be set as the target address. As a result, when the write access is executed, the processing by the redundant address setting circuit can be omitted, and the write access time can be shortened by the time required for the processing by the redundant address setting circuit. As a result, it is possible to improve the yield of the semiconductor memory device by providing the redundant memory cells and to improve the operation speed of the write access.

  The present invention can be realized in various forms, for example, in the form of a semiconductor memory device, an access control method for the semiconductor memory device, an address setting method, and an electronic device including the semiconductor memory device. Can be realized.

Next, embodiments of the present invention will be described in the following order based on examples.
A. Outline of terminal configuration and operating state of semiconductor memory device:
B. Example:
B1. Internal configuration of the semiconductor memory device:
B2. Write access operation:
B3. Effects of the embodiment:
C. Application examples for electronic devices:
D. Variations:

A. Outline of terminal configuration and operating state of semiconductor memory device:
FIG. 1 is an explanatory diagram showing a terminal configuration of a memory chip 100 as an embodiment of a semiconductor memory device of the present invention. The memory chip 100 has the following terminals.

A0 to A20: Address input terminals (21),
#CS: Chip select input terminal,
#WE: Write enable input terminal,
#OE: Output enable input terminal,
IO0 to IO15: Input / output data terminals (16).

  In the following description, the same reference numerals are used for terminal names and signal names. A terminal name (signal name) prefixed with “#” means negative logic. A plurality of address input terminals A0 to A20 and a plurality of input / output data terminals IO0 to IO15 are provided, but are illustrated in a simplified manner in FIG. Further, other terminals that are not particularly necessary in the following description such as the power supply terminals are omitted.

  The memory chip 100 is configured as a virtual SRAM (VSRAM) that can be accessed in the same procedure as a normal asynchronous SRAM. However, unlike the SRAM, since a dynamic memory cell is used, refreshing is required within a predetermined period. For this reason, a refresh control circuit (not shown) is built in the memory chip 100. In this specification, data reading and writing operations from an external device (control device) are referred to as “external access” or simply “access”.

  Inside the memory chip 100, an address transition detection circuit 140 for detecting that any one or more of the input addresses A0 to A20 has changed is provided. The circuit in the memory chip 100 operates based on the address transition signal supplied from the address transition detection circuit 140. This address transition signal corresponds to the external access timing signal of the present invention. In the following description, the address transition detection circuit 140 is also referred to as an “ATD circuit”, and the address transition signal ATD (external access timing signal) is also referred to as an “ATD signal”.

  A chip select signal #CS shown in FIG. 1 is a signal for controlling the operating state of the memory chip 100. In this specification, “H level” means “1” level of the two levels of the binary signal, and “L level” means “0” level.

  When chip select signal #CS is at L level (active), the internal operating state is the operation mode, and a read / write operation cycle (hereinafter also simply referred to as “operation cycle” or “read / write cycle”). Done. In the operation cycle, external access can be executed, and refresh is executed when appropriate.

  When the chip select signal #CS is at the H level, the internal operation state is the standby mode. In the standby mode, execution of external access is prohibited, so that all word lines are inactivated. However, when refresh is performed, the word line specified by the refresh address is activated.

  Addresses A0 to A20 are 21 bits and designate an address of 2M words. The input / output data IO0 to IO15 is 16-bit data for one word. That is, one value of the addresses A0 to A20 corresponds to 16 bits (1 word), and 16-bit data can be input / output at a time.

  In the operation mode, when the write enable signal #WE becomes L level, it is determined as a write cycle, and when it becomes H level, it is determined as a read cycle. Further, when the output enable signal #OE becomes L level, output from the input / output data terminals IO0 to IO15 becomes possible.

  FIG. 2 is a timing chart showing an outline of the operation of the memory chip 100. Which of the two operating states (operation mode or standby mode) is determined at any time according to the change of the chip select signal #CS.

  In the first three cycles of FIG. 2, since the chip select signal #CS is at the L level, the operation state is the operation mode and the operation cycle is executed. In the operation cycle, either reading (read cycle) or writing (write cycle) is executed according to the level of the write enable signal #WE. Further, according to the level of the output enable signal #OE, specifically, output from the input / output data terminals IO0 to IO15 becomes possible when the output enable signal #OE becomes L level. However, the actual writing in the memory chip is not performed in the write cycle, as will be described later, but is performed after the data read operation performed in the next cycle.

  The period Tc of the ATD signal (that is, the period of change of the addresses A0 to A20) corresponds to the cycle time (also referred to as “cycle period”) of the memory chip 100. For example, the cycle time Tc is set to a value in the range of about 50 ns to about 100 ns in random access.

  After the end of the third cycle, the chip select signal #CS rises to the H level, indicating that the operation state is the standby mode.

B. Example:
B1. Internal configuration of the semiconductor memory device:
FIG. 3 is a block diagram showing an internal configuration of the memory chip 100. The memory chip 100 includes a memory block 110, an address buffer 120, and a data input / output buffer 130.

  The memory block 110 includes a memory cell array 112, a row decoder (hereinafter also referred to as “X decoder”) 114, a column decoder (hereinafter also referred to as “Y decoder”) 116, and a gate block 118. Yes.

  The configuration of the memory cell array 112 is the same as a typical DRAM memory cell array. That is, the memory cell array 112 has a plurality of 1-transistor 1-capacitor memory cells arranged in a matrix. Each memory cell is connected to a word line and a bit line pair (also called a data line pair). However, the memory cell array 112 is divided into two blocks: a standard memory cell array unit 112a corresponding to the original memory cell array and a redundant memory cell array unit 112b. In this example, 8192 rows, 256 × 16 columns (4096 columns) of memory cells are arranged in a matrix in the standard memory cell array unit 112a, and 128 rows, 256 × in the redundant memory cell array unit 112b. Sixteen columns (4096 columns) of memory cells are arranged in a matrix.

  The X decoder 114 includes a row driver, and a plurality of words in the memory cell array 112 according to a supplied 14-bit row address (hereinafter also referred to as “X address”) XAA and the word line activation signal RASE. Select one of the lines to activate it. The Y decoder 116 includes a column driver and corresponds to one word (16 bits) out of a plurality of bit line pairs in the memory cell array 112 according to a supplied 8-bit column address (hereinafter also referred to as “Y address”). (Bit) bit line pairs are simultaneously selected. Whether a word line in the standard memory cell array unit 112a is selected or a word line in the redundant memory cell array unit 112b is selected is an X address for selecting a 14-bit word line (hereinafter referred to as "access target X address"). It is also selected according to the value of the most significant bit of XAA. For example, if the most significant bit is “0”, the word line in the standard memory cell array unit 112a is selected according to the value of the lower 13 bits. If “1”, the word line in the redundant memory cell array unit 112b is the value of the lower 7 bits. Selected according to.

  The gate block 118 includes a read circuit and a write circuit (not shown), and is controlled by a control circuit (not shown) so that data can be exchanged between the data input / output buffer 130 and the memory cell array 112. Further, in the memory block 110, a precharge circuit, a sense amplifier, etc. (not shown) are also provided. Note that the read circuit, write circuit, precharge circuit, sense amplifier circuit, and control circuit are not particularly necessary for the description of the present invention, and thus the description thereof will be omitted.

  The address buffer 120 is a circuit that supplies external addresses (hereinafter also simply referred to as “addresses” or “input addresses”) A0 to A20 given from an external device to other internal circuits. Lower 8-bit addresses A0 to A7 are used as Y addresses, and upper 13-bit addresses A8 to A20 are used as X addresses XAN. A memory cell for one word (16 bits) is selected by the Y addresses A0 to A7 and the X addresses A8 to A20 (hereinafter also collectively referred to as “X address XAN”). One word worth of data corresponding to the memory cell is read or written via the data input / output buffer 130. That is, the external device can use one address A0 to A20 (hereinafter collectively referred to as “address ADD”). It is possible to simultaneously access memory cells for one word.

  The memory chip 100 further includes an ATD circuit 140, an access control circuit 150, a redundant address setting circuit 160, an X address setting circuit 170, an X address control circuit 180, and an activation control circuit 190. .

  In addition to the circuit shown in FIG. 3, the memory chip 100 includes various circuits such as a control circuit that controls the Y decoder according to Y addresses A0 to A7 given from an external device, and a control circuit that controls refresh. However, since it is not particularly necessary for explaining the present invention, it is omitted in FIG.

  The ATD circuit 140 detects whether or not there is a change in any one or more of the 21-bit addresses A0 to A20 supplied from the external device. When a change is detected, the ATD circuit 140 is shown in FIG. A pulsed ATD signal like this is generated.

  The access control circuit 150 performs a redundancy determination start signal JST, a read access request signal RQRA, a write access request signal RQWA, a read access execution signal ACTRA, according to the chip select signal #CS, ATD signal, and write enable signal #WE. A write access execution signal ACTWA is generated.

  In the redundant address setting circuit 160, the supplied X address XAN is an address corresponding to the defective memory cell, and is previously set to the address of the word line corresponding to the defective memory cell among the word lines in the standard memory cell array unit 112a. It is determined whether it is applicable. If applicable, a 14-bit address corresponding to the word line in the replaced redundant memory cell array unit 112b is output in advance as the X address XAL. If not, an address corresponding to the supplied 13-bit X address XAN among the 14-bit X addresses corresponding to the word ship in the standard memory cell array unit 112a is output as the X address XAL. The redundant address setting circuit 160 generates a redundancy determination end signal JEND when the series of processes (hereinafter also referred to as “redundancy determination process”) for the supplied X address XAN is completed.

  The X address setting circuit 170 latches the X address XAL supplied from the redundant address setting circuit 160 according to the three gate signals Gate-N, Gate-W1, and Gate-W2 supplied from the X address control circuit 180, and accesses them. The target X address XAA is supplied to the X decoder 114.

  The X address setting circuit 170 includes a first gate 171 that operates according to the first gate signal Gate-N, a second gate 173 that operates according to the second gate signal Gate-W1, a first gate 171 and a first gate 171 A first latch 172 connected to the third gate 175, and a second latch 174 provided between the second gate 173 and the third gate 175.

  When the first gate 171 is opened in accordance with the first gate signal Gate-N, the X address XAL supplied from the redundant address setting circuit 160 is supplied to the first latch 172. When the first gate 171 is closed according to the first gate signal Gate-N, the supplied X address value is latched in the first latch 172. Then, the value of the X address latched in the first latch 172 is output as the access target X address XAA.

  Similarly, when the second gate 173 is opened in accordance with the second gate signal Gate-W1, the X address XAL supplied from the redundant address setting circuit 160 is supplied to the second latch 174. Then, when the second gate 173 is closed in accordance with the second gate signal Gate-W1, the value of the supplied X address XAL is latched in the second latch 174.

  When the third gate 175 is opened according to the third gate signal Gate-W2, the value of the X address XAL latched in the second latch 174 is supplied to the first latch 172. When the third gate 175 is closed in accordance with the third gate signal Gate-W2, the value of the X address XAL supplied from the second latch 174 is latched in the first latch 174. Then, the value of the X address latched in the first latch 172 is output as the access target X address XAA.

  The X address control circuit 180 performs the above three gate signals Gate-N, Gate according to the read access request signal RQRA, the write access request signal RQWA, the read access execution signal ACTRA, the write access execution signal ACTWA, and the redundancy determination end signal JEND. -W1 and Gate-W2 are generated.

  The activation control circuit 190 performs the word line activation signal RASE according to the read access execution signal ACTRA, the write access execution signal ACTWA, the redundancy determination end signal JEND, and the three gate signals Gate-N, Gate-W1, and Gate-W2. Is generated.

  When the access target X address XAA is supplied from the X address setting circuit 170, the X decoder 114 activates one word line corresponding to the access target X address XAA in accordance with the word line activation signal RASE. And At this time, data writing is executed by the above-described writing circuit (not shown), or data reading is executed by a reading circuit (not shown).

B2. Write access operation:
The semiconductor memory device of this embodiment is characterized by the operation in the write cycle, and the operation in the read cycle is the same as the conventional one. Therefore, only the operation in the write cycle will be described below.

  FIG. 4 is a timing chart showing the operation in the write cycle. FIG. 4 shows the first and second write cycles. In each cycle, the input address ADD (FIG. 4A) changes, and the write enable signal #WE (FIG. 4B) remains constant for a certain period. The case where it changes to L level is shown.

  For convenience of explanation, it is assumed that the X address XAL output from the redundant address setting circuit 160 is not a redundant address corresponding to a redundant memory cell but an address corresponding to a standard memory cell.

  In the first cycle, when the input address ADD changes, an ATD signal (FIG. 4C) that changes to H level for a certain period is generated accordingly. Then, the read access request signal RQRA (FIG. 4 (f)) that changes to the H level is generated in response to the rise of the ATD signal.

  Then, in response to the fall of the ATD signal, the read access execution signal ACTRA (FIG. 4 (h)) changes to H level, and read access is executed.

  First, the redundancy determination start signal JST (FIG. 4 (j)) that changes to the H level is generated in response to the rise of the read access execution signal ACTRA. As a result, the redundancy determination process described above is executed for the X address XAN supplied by the redundant address setting circuit 160. When the redundancy determination process ends, a redundancy determination end signal JEND (FIG. 4 (k)) indicating the end of the redundancy determination process is generated, and the value of the address set according to the determination result becomes the X address XAL (FIG. d)). Here, 14-bit data corresponding to the value [n] indicated by the X address of the upper 13 bits of the input address ADD is output as the X address XAL.

  When the redundancy determination process in the redundancy address setting circuit 160 is completed and the redundancy determination end signal JEND changes to H level, the first gate signal Gate-N that changes to H level for a certain period accordingly (FIG. 4 ( l)) occurs. When the first gate signal Gate-N is generated, the value of the X address XAL supplied from the redundant address setting circuit 160 is latched in the first latch 172 of the X address setting circuit 170 as described above, and the access target X Set as address XAA.

  When the first gate signal Gate-N changes to L level, a word line activation signal RASE (FIG. 4 (o)) that changes to H level for a certain period is generated accordingly. As a result, the word line (word line (WL) corresponding to the address value [n]) indicated by the access target X address XAA is activated.

  When the word line activation signal RASE changes to the L level, the read access execution signal ACTRA changes to the L level after a predetermined time for deactivating the activated word line, and the read access operation ends. To do.

  When the write enable signal #WE changes to H level, a write access request signal RQWA (FIG. 4 (g)) that changes to H level is generated accordingly.

  Next, also in the second cycle, when the input address ADD changes, an ATD signal is generated accordingly. Then, the read access request signal RQRA that changes to the H level is generated in response to the rise of the ATD signal.

  Further, when the ATD signal changes to H level, the write access request signal RQWA changes to H level, so that the second gate signal Gate-W1 that changes to H level for a certain period in response to the rise of the ATD signal. (FIG. 4 (n)) occurs. When the second gate signal Gate-W1 is generated, as described above, the value of the X address XAL supplied from the redundant address setting circuit 160 to the second latch 174 of the X address setting circuit 170 (in the example of FIG. ]) Is latched.

  Then, in accordance with the fall of the ATD signal, as in the first cycle, the read access execution signal ACTRA changes to H level, and read access is executed. In this case, however, the value latched in the first latch 172 of the X address setting circuit 170 in accordance with the generation of the first gate signal Gate-N is the upper 13 of the input addresses ADD in the second cycle. It is the value [n + 1] indicated by the X address of the bit, and the word line corresponding to this value is activated.

  When the read access execution signal ACTRA changes to L level, the write access execution signal ACTWA (FIG. 4 (i)) changes to H level accordingly, and write access is executed.

  First, in response to the rise of the write access execution signal ACTWA, a third gate signal Gate-W2 (FIG. 4 (n)) that changes to the H level for a certain period is generated. When the third gate signal Gate-W2 is generated, as described above, the value ([n]) of the X address XAL in the first cycle latched in the second latch 174 of the X address setting circuit 170 is changed. Are supplied to and latched in the first latch 172 and set as the access target X address XAA.

  Then, when the third gate signal Gate-W2 changes to L level, the word line activation signal RASE that changes to H level for a certain period is generated accordingly. As a result, the word line represented by the X address XAA (the word line corresponding to the address value [n]) is activated.

  When the word line activation signal RASE changes to L level, the read access execution signal ACTRA changes to L level after a predetermined time for deactivating the activated word line, and the write access operation ends. To do.

  As described above, actual write access corresponding to a certain write cycle is performed after execution of read access in the next cycle. At this time, the time required for the read access is the time required for the redundancy determination process, the access target address setting time, the word line activation time, and the deactivation time. The time required for the write access is the set time of the access target address, the activation time and the inactivation time of the word line.

B3. Effects of the embodiment:
FIG. 5 is an explanatory diagram showing the effect of the embodiment. FIG. 5B shows a flow of operation when write access is executed following read access in the write cycle of the embodiment, and FIG. 5A shows a comparative example. The flow of operation in the write cycle is shown from left to right with reference to the fall of the ATD signal. In addition, the rectangles indicated by double-line frames in the figure indicate periods during which corresponding signals are generated (active periods).

  As shown in FIG. 5A, in the comparative example, during the period in which the read access execution signal ACTRA is generated, redundancy determination, setting of an access target address, activation of the word line (WL), word Processing is performed in the order of deactivation of the lines, and read access is executed. When the read access is completed, a write access execution signal ACTWA is generated following the read access execution signal ACTRA. Even during the period in which the write access execution signal ACTWA is generated, the write access is executed by processing in the order of redundancy determination, word line activation, and word line deactivation, as in the case of read access. Is done.

  On the other hand, as shown in FIG. 5B, in the case of the embodiment, during the period in which the write access execution signal ACTWA is generated, setting of the access target address, activation of the word line, inactivation of the word line Processing is performed in the order of conversion.

  In the comparative example, the minimum value (minimum cycle time) Tcw0 allowed as the write cycle time is the time from the start of the read access to the end of the write access, that is, the read access time Tra0 and the write access time Twa0. Expressed in sum.

  Similarly, in the embodiment, the minimum cycle time Tcw1 is represented by the sum of the read access time Tra1 and the write access time Twa1.

  Here, the read access time Tra1 in the embodiment is equal to the read access time Tra0 in the comparative example, but the write access time Twa1 in the embodiment is only a time corresponding to the redundancy determination processing time Tdj with respect to the write access time Twa0 in the comparative example. Shorter.

  Therefore, in the case of the embodiment, the access time from the fall of the ATD signal to the end of the write access can be shortened in the write cycle as compared with the case of the comparative example, so that the write cycle time can be shortened. It becomes possible.

C. Application examples for electronic devices:
FIG. 6 is a perspective view of a mobile phone as an embodiment of an electronic apparatus using the semiconductor memory device according to the present invention. This cellular phone 700 includes a main body 710 and a lid 720. The main body 710 is provided with a keyboard 712, a liquid crystal display 714, a receiver 716, and a main body antenna 718. The lid 720 is provided with a transmitter 722.

  FIG. 7 is a block diagram showing an electrical configuration of the mobile phone 700 of FIG. The CPU 730 is connected to a keyboard 712, an LCD driver 732 for driving the liquid crystal display unit 714, an SRAM 740, a VSRAM 742, and an EEPROM 744 via a bus line.

  The SRAM 740 is used as a high-speed cache memory, for example. The VSRAM 742 is used as a work memory for image processing, for example. As the VSRAM 742 (referred to as a pseudo SRAM or a virtual SRAM), the memory chip 100 described above can be employed. The EEPROM 744 is used for storing various setting values of the mobile phone 700.

  When the operation of the cellular phone 700 is temporarily stopped, the VSRAM 742 can be maintained in a standby state. By doing so, the VSRAM 742 automatically performs internal refresh, so that the data in the VSRAM 742 can be retained without being lost. In particular, since the memory chip 100 of this embodiment has a relatively large capacity, there is an advantage that a large amount of data such as image data can be held for a long time. Further, the memory chip 100 of this embodiment has an advantage that it can be used in the same manner as the SRAM because it is not necessary to be aware of the refresh operation. Further, the memory chip 100 of this embodiment has an advantage that data write can be performed at high speed because the write cycle time can be shortened.

D. Variations:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

  In the above embodiment, the ATD circuit (FIG. 4) is provided, and the access operation is executed based on the ATD signal. Instead, a clock signal may be supplied from an external device.

  In the above embodiment, the semiconductor memory device that designates an address of 2M words by an input address of 21 bits has been described as an example. However, the present invention is not limited to this, and it corresponds to an input address of various bits. It may be a semiconductor memory device. In the above embodiment, the semiconductor memory device capable of inputting / outputting 16-bit data has been described as an example. It may be.

It is explanatory drawing which shows the terminal structure of the memory chip 100 as one Example of the semiconductor memory device of this invention. 3 is a timing chart showing an outline of the operation of the memory chip 100. 2 is a block diagram showing an internal configuration of a memory chip 100. FIG. 6 is a timing chart showing an operation in a write cycle. It is explanatory drawing which shows the effect of an Example. 1 is a perspective view of a mobile phone as an embodiment of an electronic apparatus using a semiconductor memory device according to the present invention. It is a block diagram which shows the electrical constitution of the mobile telephone 700 of FIG. It is explanatory drawing which shows an example of the flow of the process of the write access in virtual SRAM which employ | adopted the redundancy technique.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Memory chip 110 ... Memory block 112 ... Memory cell array 112a ... Standard memory cell array part 112b ... Redundant memory cell array part 114 ... Row decoder (X decoder)
116 ... Column decoder (Y decoder)
118 ... Gate block (GATE)
120 ... Address buffer 130 ... Data input / output buffer 140 ... Address transition detection circuit (ATD circuit)
150 ... Access control circuit 160 ... Redundant address setting circuit 170 ... X address setting circuit (row address setting circuit)
171,173,175 ... Gate 172,174 ... Latch 180 ... X address control circuit (row address control circuit)
190 ... Activation control circuit 700 ... cell phone 710 ... main body 712 ... keyboard 714 ... liquid crystal display 716 ... receiver 718 ... main body antenna 720 ... lid Part 722 ... Sending part 730 ... CPU
732 ... LCD driver 740 ... SRAM
742 ... VSRAM
744 ... EEPROM

Claims (3)

A semiconductor memory device in which read access or write access is executed based on an address change of an external input address,
A memory cell array including a standard memory cell array unit in which memory cells are arranged in a matrix, and a redundant memory cell array unit having a redundant memory cell replaced with a defective memory cell in the standard memory cell array unit;
A circuit for outputting an address for specifying a memory cell in the memory cell array based on the input address, and the standard memory cell array corresponding to the input address in the standard memory cell array unit is the defective memory cell. In this case, it is determined in advance whether the memory cell has been replaced by the redundant memory cell in the redundant memory cell array unit, and if so, a redundant address corresponding to the replaced redundant memory cell is output. If not, a redundant address setting circuit for outputting a standard address corresponding to the standard memory cell;
An address setting circuit that latches an address output from the redundant address setting circuit and outputs an access target address corresponding to a memory cell to be accessed in the memory cell array,
The address setting circuit includes:
When an external write enable signal is in an active state in a certain first access cycle, after executing a read access corresponding to the input address in the second access cycle in the next second access cycle, When performing a write access corresponding to the input address in the first access cycle,
When the read access is executed, the address output from the redundant address setting circuit is latched and output as the access target address in the second access cycle, and when the write access is executed, the address is latched before the read access is executed. The semiconductor memory device, wherein the address output from the redundant address setting circuit in the first access cycle is output as the access target address.   An electronic device comprising the semiconductor memory device according to claim 1. A method for setting an access target address in a semiconductor memory device in which an access operation is executed based on an address change of an external input address,
The semiconductor memory device includes:
A memory cell array including a standard memory cell array unit in which memory cells are arranged in a matrix, and a redundant memory cell array unit having a redundant memory cell replaced with a defective memory cell in the standard memory cell array unit;
A circuit for outputting an address for specifying a memory cell in the memory cell array based on the input address, and the standard memory cell array corresponding to the input address in the standard memory cell array unit is the defective memory cell. In this case, it is determined in advance whether the memory cell has been replaced by the redundant memory cell in the redundant memory cell array unit, and if so, a redundant address corresponding to the replaced redundant memory cell is output. A redundant address setting circuit that outputs a standard address corresponding to the standard memory cell, if not applicable,
When an external write enable signal is in an active state in a certain first access cycle, after executing a read access corresponding to the input address in the second access cycle in the next second access cycle, When performing a write access corresponding to the input address in the first access cycle,
When the read access is executed, the address output from the redundant address setting circuit is latched and output as the access target address in the second access cycle, and when the write access is executed, the address is latched before the read access is executed. The access target address setting method, wherein the address output from the redundant address setting circuit in the first access cycle is output as the access target address.

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