JP3367475B2 - Wireless communication device and power consumption control method for wireless communication device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio communication device and a power consumption control method for the radio communication device, and more particularly, it is used as a mobile station of a mobile communication system and is used by a plurality of CDMA transmitters as in a handover. The present invention relates to a wireless communication device of a CDMA communication system that receives a signal of the above and its power consumption control method.

[0002]

2. Description of the Related Art Recently, mobile communication systems such as mobile phones have become widespread. One of the communication methods used in such a mobile communication system is CDMA (Co
deDivision Multiple Multiple Acces
s).

In this CDMA, the transmitting side spreads and transmits data by a predetermined spreading code which is different for each data to be transmitted, and the receiving side transmits the same spreading code as the transmitting side (to be exact, spreading of the transmitting side). The received signal is spread (so-called despreading) with a code and a complex conjugate code to obtain data. That is, in such CDMA communication, the signal transmitted from the transmitting side can be reproduced by shifting the timing of despreading the signal received at the receiving side and finding the peak of the correlation value.

By the way, a mobile station in a mobile communication system such as a mobile phone is required to be easily carried by a mobile station.
It is desired to be smaller and lighter and to be usable for a long time. Therefore, the internal battery that drives the mobile station is also downsized, and in order to enable long-time operation with such a small battery, low power consumption of the mobile station is an important issue.

As an example of reducing the power consumption of a CDMA receiver, there is a CDMA receiver disclosed in Japanese Patent Laid-Open No. 9-200177. This CDMA receiver is intended to reduce the power consumption of a correlation filter that despreads a received signal.

FIG. 15 is a block diagram showing a correlation filter of the CDMA receiver disclosed in Japanese Patent Laid-Open No. 9-200177.

As shown in FIG. 15, this correlation filter has a delay circuit 51, a weighting synthesis circuit 52, a timing control circuit 53, and a switch element 54.

The delay circuit 51 is for obtaining a signal obtained by delaying the input signal. When the input signal is a digital signal, the delay circuit 51 is constituted by a shift register, for example, and when the input signal is an analog signal. For example, it is composed of a delay line and an analog shift register.

The weighting / synthesizing circuit 52 is provided corresponding to the tap outputs TP1 to TPn from the delay circuit 51, a plurality of weighting circuits for multiplying the tap outputs TP1 to TPn and the weighting coefficients W1 to Wn, and a plurality of weighting circuits. And a synthesizing circuit for synthesizing and outputting output signals from the respective weighting circuits.

The timing control circuit 53 controls the operation of the switch element 54 based on the correlation output signal obtained from the weighting synthesis circuit 52. The switch element 54 is closed for a predetermined time by a control signal from the timing control circuit 53 so that the power supply voltage is supplied from the power supply 55 to the weighting synthesis circuit 52.

In other words, the weighting synthesis operation in the weighting synthesis circuit 52 can be said to detect the correlation between the input signal and the weighting factors W1 to Wn. In the CDMA receiver disclosed in Japanese Unexamined Patent Publication No. 9-200177, since the portion where the correlation result shows a peak does not exist over the entire input signal, the weighted combination is performed except for the portion where the correlation result shows a peak. The power consumption is reduced by stopping the power supply to the circuit 52.

[0012]

By the way, in a CDMA mobile communication system, when a mobile station moves from a cell covered by one base station to a cell covered by another base station, both mobile stations After the period for receiving the signal from the base station, the handover for switching the receiving base station is performed.

For example, at the time of this handover, the mobile station needs to receive signals from a plurality of base stations and demodulate the plurality of signals, which results in a large power consumption.

However, the above-mentioned JP-A-9-200177 is used.
In the prior art such as the CDMA receiver disclosed in the publication, no consideration is given to reduction of power consumption during handover, and much power is still consumed during handover.

That is, in the prior art, not only at the time of handover, but also in the structure in which the CDMA receiver receives signals from a plurality of CDMA transmitters, that is, in the structure such as site diversity, reduction of power consumption is considered. Absent.

The present invention has been made in view of the above points, and in the case of receiving signals from a plurality of CDMA transmitters at the time of handover, a wireless communication device and its power consumption can be reduced. An object is to provide a power consumption control method for a wireless communication device.

[0017]

In order to achieve the above object, the present invention has a plurality of delay profile circuits for creating a delay profile by correlating a received signal with known data at a plurality of timings. ,
In a wireless communication device of a CDMA communication system having a timing circuit for generating a correlation timing in each of the plurality of delay profile circuits,
Let N be a number (N is a natural number with 2 <N),
The delay created by each of the delay profile circuits
B. The maximum correlation value of each profile is Pb in ascending order
(N), Pb (N-1), ... Pb (1)
(Pb (N) -Pb (i)) (i is 1 ≦ i <N
When a certain natural number) is larger than a predetermined threshold, the maximum phase
The delay profile for the function Pb (i)
Ray profile circuit and delay profile circuit
Of the timing circuit that generates the correlation timing in the path
It is characterized by stopping the operation .

The present invention also achieves the above objects.
In addition, known data at multiple timings for the received signal
A delay profile that correlates the
In addition to having a plurality of profile circuits,
For each delay profile circuit, the delay profile
Timing to generate correlation timing in the loop circuit
In a wireless communication device of a CDMA communication system having a circuit
The number of delay profile circuits is N (N
Is a natural number such that 2 <N, and
Delay profile created by each of the profile circuits
Pb (N), P
b (N-1), ..., Pb (1), (Pb
(I) -Pb (i-1)) (i is 1 <i ≦ N
Is greater than a predetermined threshold, the maximum correlation value P
Create delay profiles b (i-1) to Pb (1)
DELAY PROFILE CIRCUIT AND THE DELAY PRO
Timing for generating correlation timing in file circuits
The operation of the switching circuit is stopped .

According to the present invention, in the wireless communication device of the CDMA communication system according to claim 1 or 2, the plurality of delay profile circuits respectively receive signals from a plurality of CDMA transmitting devices which are simultaneously received. And a delay for creating the delay profile in accordance with the correlation value of the delay profile at the time of handover for switching the reception target from any one of the plurality of CDMA transmitters to another one. It is characterized in that the operation of the timing circuit that generates the correlation timing in the profile circuit and the delay profile circuit is stopped.

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

In the following embodiments, the case where the present invention is applied to a mobile station in a CDMA mobile communication system will be described. Further, the following embodiment is an example in the case of reducing the power consumption at the time of handover.

FIG. 1 is a block diagram showing an outline of an example of a CDMA mobile communication system to which a mobile station according to the present invention is applied.

The base station-base station controller-switching station, which constitutes the network side of the mobile communication system, diversifies the services provided by the mobile communication system (multimedia), controls each base station, and base station. From the viewpoint of efficient use (statistical multiplexing) of the transmission line connecting the device and the exchange, the ATM (Asy
Nchronous Transfer Mode) communication technology has come to be applied.

The mobile station 1 communicates with another mobile station or a terminal device connected to another network by a mobile communication system. There may be various types of communication such as voice and data communication.

The transmission data from the mobile station 1 is transmitted as communication data to the base station 2 by wireless communication. The base station 2 assembles the communication data received from the mobile station 1 and other mobile stations into ATM cells, performs various processes, and then transmits the data to the base station control device 3.

As described above, even if the communication data in the wireless section is voice, image, or any other form of data, the information converted into ATM cells is transmitted by the base station in the network and is thus converted into multimedia. It is possible to easily cope with different communication modes.

The base station control device 3 routes the ATM cell received from the base station 2 for each user and transmits the ATM cell to the exchange 4 or another base station under its control. Exchange 4
Then, similarly to the base station controller 3, the ATM cell received from the base station controller 3 is routed for each user,
It is sent to another exchange or the gateway 5.

For the transmission of such ATM cells, it suffices to flow them in the transmission line according to the generation of the ATM cells, and it is not necessary to provide a predetermined transmission line for each channel as in the conventional case. The effect can be obtained and the transmission line can be used efficiently. The gateway station 5 is provided for relaying to other networks.

When the base station 2 transmits data from the network side to the mobile station 1, after performing primary modulation such as QPSK, 2
The code is spread as the next modulation and transmitted. The demodulation circuit of the present embodiment can be applied to the mobile station 1, for example,
The mobile station 1 demodulates the received signal from the base station 2 by using this demodulation circuit to demodulate and reproduce the data from the network side.

FIG. 2 is a block diagram showing a communication environment of a CDMA mobile communication system to which the mobile station 1 shown in FIG. 1 is applied.

In the CDMA mobile communication system shown in FIG. 2, the cellular system is adopted, the range covered by the base station 2a is the cell 6a, and the range covered by the base station 2b is the cell 6b. The range covered by the station 2c is the cell 6c.

Here, it is assumed that the mobile station 1 is currently located in the cell 6a and is moving in the direction of the arrow shown in FIG. At this time, the mobile station 1 initially communicates only with the base station 2a, and then detects that the signal from the base station 2a has weakened and performs handover. In this handover, not only the signal from the base station 2a but also the signals from the base stations other than the base station 2a are received at the same time, so that the base station that can receive the strongest signal is found and the base station to communicate with in the future is selected. It is to switch.

As described above, the mobile station 1 needs to simultaneously receive signals from a plurality of base stations at the time of handover. The signals from each base station are spread and transmitted with different spreading codes, and in order to enable the mobile station 1 to receive signals from a plurality of base stations at the same time, the received signal is It is necessary to provide as many circuits for finding the timing for despreading as as many base stations as desired to receive at the same time.

FIG. 3 is a block diagram of a first embodiment of a mobile station according to the present invention.

In the present embodiment, the antenna 7 that receives a signal from the base station, the radio circuit 8 that performs quadrature detection and demodulation on the signal received by the antenna 7, the signal from the radio circuit 8 and the known data. Delay profile circuit 9 for obtaining a delay profile by correlating with
And a searcher circuit 10 that selects a signal having a high correlation value from a plurality of delay profiles obtained by the delay profile circuit 9 and outputs a signal that is the basis of the timing for despreading, and a signal from the searcher circuit 10. A timing circuit 11 for outputting a pulse signal indicating the timing of correlation in the delay profile circuit 9 based on
A CPU 12 for controlling the operations of the delay profile circuit 9 and the timing circuit 11; and an operation clock generation circuit 13 for generating and outputting an operation clock for operating the delay profile circuit 9 and the timing circuit 11. The operation clock generation circuit 13 generates and outputs a clock signal having a frequency of 16.384 MHz, for example.

As described above, the mobile station needs to simultaneously receive signals from a plurality of base stations at the time of handover. In the example shown in FIG. 3, the delay profile circuit 9, the searcher circuit 10, and the timing circuit 10 are required. Is provided for each base station.

That is, the delay profile circuit 9
Is a first base station delay profile circuit 9a and a second base station delay profile circuit 9b that are provided for each base station among a plurality of base stations that receive simultaneously.
And a third base station delay profile circuit 9c.

Further, the searcher circuit 10 includes a first base station searcher circuit 10a, a second base station searcher circuit 10b, which are provided for each base station among a plurality of base stations that receive simultaneously. It comprises a third base station searcher circuit 10c.

Further, the timing circuit 11 includes a first base station timing circuit 11a and a second base station timing circuit 11b, which are provided for each base station among a plurality of base stations that receive simultaneously. And a third base station timing circuit 11c.

The searcher circuit 10 is, for example, DS
It may be configured by P and the processing may be realized by software. In this case, one DSP can perform processing relating to a plurality of base stations.

FIG. 4 is a diagram showing an example of the configuration of a received signal transmitted from the base station 2 shown in FIG. 1 and received by the mobile station 1.

As shown in FIG. 4, the length 1 from the base station 2
Radio frames of 0 ms are continuously transmitted. One radio frame is composed of 16 slots, and one slot is composed of 10 symbols. Further, 10 symbols forming one slot are composed of 4 pilot symbols and 6 information data symbols.

The pilot symbol is known data which is predetermined in the communication system, and the delay profile circuit 9 shown in FIG. 3 uses this known data to calculate the delay profile. Further, the information data symbol is actual data that is desired to be actually transmitted / received by communication between terminals.

As described above, the inside of the delay profile circuit 9 is configured for each base station, and includes a first base station delay profile circuit 9a, a second base station delay profile circuit 9b, and a third base station delay profile circuit 9b. It is divided into a base station delay profile circuit 9c. The data transmitted from each base station is spread with a different spreading code, and each base station delay profile circuit 9a,
In 9b and 9c, only the signal from the base station can be obtained by despreading with the spreading code assigned to the corresponding base station.

The first base station delay profile circuit 9 in the delay profile circuit 9 shown in FIG.
Since a, the second base station delay profile circuit 9b and the third base station delay profile circuit 9c have the same internal configuration, in the following description, the first base station delay profile circuit 9a will be representatively described. explain.

Similarly, the searcher circuit 10 shown in FIG.
Since the first base station searcher circuit 10a, the second base station searcher circuit 10b, and the third base station searcher circuit 10c have the same internal configuration, in the following description, the first base station searcher circuit 10a will be representatively described. The base station searcher circuit 10a will be described, and the first base station timing circuit 11a, the second base station timing circuit 11b, and the third base station timing circuit 11c in the timing circuit 11 shown in FIG. Since the internal configuration is the same, in the following explanation,
The first base station timing circuit 11a will be described as a representative.

FIG. 5 is a block diagram showing the internal configuration of the first base station delay profile circuit 9a shown in FIG.

The first base station delay profile circuit 9a serves as an interface for receiving the delay profile circuit control signal from the CPU 12 shown in FIG.
A PU interface unit 15, an operation unit 16 for performing an operation for obtaining a delay profile, and an external DPRA
It is configured to have a RAM control unit 17 that controls reading and writing from and to M19, and a switch unit 18 that switches between supply and stop of the operation clock. CPU
The interface unit 15, the arithmetic unit 16, and the RAM control unit 17 operate by being supplied with an operation clock. Arithmetic unit 16 and RAM control unit 1
7 stops its operation when the supply of the operation clock is stopped, and consumes almost no power when this operation is stopped. The switch unit 18 is normally closed, and the operation clock is supplied not only to the CPU interface unit 15 but also to the arithmetic unit 16 and the RAM control unit 17.

The DPRAM 19 is a bidirectional RAM, and RA can be read and written bidirectionally from the delay profile circuit 9 side and from the searcher circuit 10 side.
It is M. The delay profile circuit 9 and the searcher circuit 10 exchange data via the DPRAM 19. That is, the delay profile created by the delay profile circuit 9 is the DPRAM 19
Is written in the searcher circuit 10, and the searcher circuit 10 reads the delay profile from the DPRAM 19.

Further, a total of three DPRAMs 19 are provided for each of the first base station delay profile circuit 9a, the second base station delay profile circuit 9b, and the third base station delay profile circuit 9c. Alternatively, only one delay profile circuit 9 may be provided.

FIG. 6 is a block diagram showing the internal structure of the arithmetic unit 16 in the first base station delay profile circuit 9a shown in FIG.

The calculation unit 16 correlates a received signal from the first base station with known data, and a power value calculation unit 22 for converting the correlation result obtained by the correlation processing unit 21 into a power. And an average value calculation unit 24 that calculates the average of a plurality of slots of the received signal with respect to the addition result by the power value addition unit 23 and adds the outputs of the power value calculation unit 22 and outputs the result as a delay profile. And is configured.

Note that, in FIG. 5, control such as designation of an address for writing and reading from the DPRAM 19 is performed from the arithmetic unit 17 via the RAM control unit 17, and since the data flow is shown in FIG.
The control unit 17 is not shown in FIG.

Here, referring to FIG. 5 and FIG. 6, the first
The operation of the base station delay profile circuit 9a will be described.

The received signal from the radio circuit 8 shown in FIG. 3 and the delay profile circuit timing signal from the first base station timing circuit 11a shown in FIG. 9 are used for the first base station shown in FIG. Delay profile circuit 9
It is input to the arithmetic unit 16 of a.

The correlation processing unit 21 of the arithmetic unit 16 shown in FIG.
Then, the spread code and known data (for example, pilot symbol) for the base station are obtained from the CPU 12 shown in FIG. 3 via the CPU interface unit 15, the received signal is despread by the spread code, and the delay signal is delayed. The correlation between the received signal after despreading at the timing of the profile circuit timing signal and the known data is obtained.

FIG. 7 is a diagram for explaining the processing for obtaining the correlation in the correlation processing unit 21 shown in FIG.

First, the correlation processing section 21 performs despreading with the spreading code obtained via the CPU interface section 15. The received signal shown in FIG. 7 is a signal after despreading.

Next, as shown in FIG. 7, the correlation processing unit 21 takes in the received signal at the timing of the delay profile circuit timing signal and obtains the correlation between the taken-in data and known data.

In obtaining this correlation, a plurality of correlation results are obtained while gradually shifting the relative position of the known data with respect to the fetched data (while shifting the correlation detection timing). In the example shown in FIG. 7, a total of 512 correlation results are obtained by shifting by 61 ns. The width of 61 ns for shifting the correlation detection timing is 16.384 MH generated by the operation clock generation circuit 13 shown in FIG.
It is a pulse cycle of the z clock, but it goes without saying that the present invention is not limited to this.

The correlation result thus obtained is delivered to the blocks after the power value calculation unit 22 shown in FIG.
After that, the power value calculation unit 22 powers the correlation result obtained by the correlation processing unit, the power value addition unit 23 adds the output of the power value calculation unit 22, and the average value calculation unit 24 the power value addition unit. With respect to the addition result obtained by 23, the average of a plurality of slots of the received signal is obtained and output as a delay profile.

Here, the power value addition unit 23 uses the DPRAM 19 for temporarily storing data in the addition process, and the average value calculation unit 24 writes the obtained delay profile in the DPRAM 19, The delay profile is output. As a result, 512 delay profiles with different correlation detection timings are written in the DPRAM 19, and the searcher circuit 10 shown in FIG.
The delay profile as the correlation result is obtained via the AM 19.

FIG. 8 is a block diagram showing the internal structure of the first base station searcher circuit 10a shown in FIG.

The first base station searcher circuit 10a is
Correlation that finds the largest correlation value among the plurality of delay profiles with different correlation detection timings, which is obtained by the first base station delay profile circuit 9a, and outputs a stop request signal by the process described later regarding the correlation value. The value detection circuit 26 and a timing correction signal for correcting the correlation detection timing in the first base station delay profile circuit 9a based on the correlation detection timing of the delay profile having the largest correlation value found by the correlation value detection circuit 26. A timing control circuit 27 that outputs a despread timing signal that is the timing to despread the received signal and a RAM 28 that stores a threshold value used in the process of outputting the stop request signal in the correlation value detection circuit 26 are output. Configured to have.

In the first base station searcher circuit 10a shown in FIG. 8, first, in the correlation value detection circuit 26, D
The 512 delay profiles with the correlation detection timing shifted are read from the PRAM 19, the delay profile having the largest correlation value, that is, the correlation value showing the peak is searched, and the timing profile is notified to the timing control circuit 27.

The process of outputting the stop request signal in the correlation value detection circuit 26 will be described later.

The timing control circuit 27 corrects the correlation detection timing in the first base station delay profile circuit 9a based on the correlation detection timing of the delay profile having the largest correlation value found by the correlation value detection circuit 26. In addition to outputting the correction signal, a finger (not shown) outputs a despreading timing signal that is the timing for despreading the received signal.

Here, the first base station searcher circuit 1
The timing correction signal and the despreading timing signal output from the timing control circuit 27 in 0a will be described.

As shown in FIG. 7, the delay profile circuit 9 for each base station in the delay profile circuit 9
In a, 9b, and 9c, 512 delay profiles with different correlation detection timings are obtained. For this reason, if the position where the known data is inserted in the received signal is a position that does not fit in these 512, the correct despreading position cannot be found.

To solve this, in the timing control circuit 27, the timing for correcting the timing signal for the delay profile circuit is adjusted so that the delay profile at the center of the 512 shown in FIG. 7 has the maximum correlation value. Output the correction signal.

Since the despreading timing signal output from the timing control circuit 27 is for notifying a finger (not shown) of the timing of despreading the received signal, the known data as shown in FIG. That is, in the case of the data format in which the pilot symbol is at the beginning of each slot, the despreading timing signal is output at the correlation detection timing of the delay profile having the maximum correlation value among the 512 delay profiles shown in FIG.

The timing correction signal and the despreading timing signal output from the timing control circuit 27 in the first base station searcher circuit 10a in this way are sent to the first base station timing circuit 11a shown in FIG. Is entered.

FIG. 9 is a block diagram showing an internal configuration of the first base station timing circuit 11a shown in FIG.

The first base station timing circuit 11a is
The CPU interface unit 30 serving as an interface for receiving the timing circuit control signal from the CPU 12 shown in FIG. 3, and counting up based on the counter on / off signal from the CPU interface unit 30 and the timing correction signal from the first searcher circuit 10a. 10,
a count unit 31 that outputs the timing of the ms cycle, a comparison unit 32 that compares the timing output by the count unit 31 with the despread timing signal from the first searcher circuit 10a, and outputs the timing at which the two match. A signal generation unit 33 that generates a pulse signal at the timing output by the counting unit 31 and outputs the pulse signal as a delay profile circuit timing signal, and also generates a pulse signal at the timing output by the comparison unit 32 and outputs it as a finger timing signal. It is configured to include a switch unit 34 that switches between supply and stop of supply of a clock. CPU
The interface unit 30, the count unit 31, the comparison unit 32, and the signal generation unit 33 operate by being supplied with an operation clock. The counting unit 31, the comparing unit 32, and the signal generating unit 33 stop their operations when the supply of the operation clock is stopped, and consume almost no power when this operation is stopped. The switch unit 34 is normally closed, and the operation clock is supplied not only to the CPU interface unit 30 but also to the counting unit 31, the comparing unit 32, and the signal generating unit 33.

In the first base station timing circuit 11a, the counting unit 31 includes the CPU interface unit 3
By counting up by the counter on / off signal obtained via 0, the cycle of 10 ms is counted and output. As a result, a signal having a cycle corresponding to the length of the radio frame shown in FIG. 4 is produced.

Here, the count section 31 is reset by the timing correction signal from the timing control circuit 27 shown in FIG. 8, and as a result, a signal having a cycle corresponding to the length of the radio frame is produced at the timing of the timing correction signal. ing.

The signal from the count unit 31 is the signal generation unit 3
3, the signal generator 33 generates a pulse signal in the cycle of the signal from the counter 31 and outputs it as a delay profile circuit timing signal.

The signal from the count section 31 is also input to the comparison section 32. In the comparison unit 32, the counting unit 31
8 is compared with the despreading timing signal from the timing control circuit 27 shown in FIG. 8, and a coincidence signal is output if the comparison results in coincidence. This coincidence signal is input to the signal generation unit 33, and the signal generation unit 33 generates a pulse signal at the cycle of the coincidence signal from the comparison unit 32 and outputs it as a finger timing signal. This finger timing signal is input to a finger (not shown) and used as the despreading timing in the finger.

FIG. 10 is a diagram showing a flowchart of a process of outputting a stop request signal from the correlation value detection circuit 26 shown in FIG. 8 in the first embodiment of the present invention.

The correlation value detection circuit 26 shown in FIG. 8 first shifts the correlation detection timing from the DPRAM 19 by five.
Read 12 delay profiles (A-1),
A delay profile having the largest correlation value, that is, a peak correlation value is searched from among these (A-2).

Next, the maximum correlation value is compared with the threshold value stored in advance in the RAM 28 in the first base station searcher circuit 10a (A-3), and as shown in FIG. If is smaller than the threshold, a stop request signal is output (A-4).

When the CPU 12 shown in FIG. 3 receives this stop request signal, the CPU 12 outputs the fact to the delay profile circuit control signal. In the CPU interface unit 15 in the first delay profile circuit for base station 9a shown in FIG. 5, which receives the delay profile circuit control signal, the switch unit 18 is opened and the operation clock for the arithmetic unit 16 and the RAM control unit 17 is changed. Stop the supply. Arithmetic unit 16 and RAM control unit 1
No. 7 stops its operation when the supply of the operation clock is stopped, which reduces power consumption.

Further, when the CPU 12 receives the stop request signal, the CPU 12 outputs the fact to the timing circuit control signal. In the CPU interface unit 30 in the first base station timing circuit 11a shown in FIG. 9 that receives this timing circuit control signal, the switch unit 34 is opened and the operations for the counting unit 31, the comparing unit 32, and the signal generating unit 33 are performed. Stop clock supply. The counting unit 31, the comparing unit 32, and the signal generating unit 33 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

FIG. 12 shows the correlation value detection circuit 2 shown in FIG.
It is a figure which shows the flowchart of the process which returns operation | movement, when the stop request signal is output from 6. This FIG.
The process shown in is executed by the correlation value detection circuit 26 shown in FIG.

First, in step (B-1), it is determined whether or not the stop request signal is currently being output. If the stop request signal is not being output, wait until the stop request signal is output.

In step (B-1), if the stop request signal is being output, it waits for a predetermined time to elapse from the start of outputting the stop request signal (B-2). Stop the output of the stop request signal (B
-3).

The predetermined time in step (B-2) is
It is preferable to make it a natural number times the length of the radio frame, and when the length of the radio frame is 10 ms, it is 10 ms × n (where n is a natural number).

When the output of the stop request signal to the CPU 12 shown in FIG. 3 is stopped, when the CPU 12 receives the stop request signal, the CPU 12 outputs the fact to the delay profile circuit control signal. Upon receiving the delay profile circuit control signal, in the CPU interface unit 15 in the first base station delay profile circuit 9a shown in FIG. 5, the switch unit 18 is closed and the arithmetic unit 1
6 and the supply of the operation clock to the RAM control unit 17 are restarted.

Further, when the CPU 12 receives the stop of the stop request signal, the CPU 12 outputs the fact to the timing circuit control signal. Upon receipt of this timing circuit control signal, C in the first base station timing circuit 11a shown in FIG.
In the PU interface unit 30, the switch unit 34 is closed, and the counting unit 31, the comparing unit 32, and the signal generating unit 33.
Supply of the operation clock to

Next, a second embodiment of the present invention will be described. In the second embodiment, its block configuration is the same as that of the first embodiment, and therefore, FIG.
Detailed description will be omitted with reference to FIG. 7. However, in the present embodiment, the searcher circuit 10 shown in FIG.
Is not configured to perform independent processing for each of a plurality of base stations that are simultaneously received, and refers to a correlation value of delay profiles of a plurality of base stations.

FIG. 13 is a diagram showing a flowchart of a process for outputting a stop request signal from the correlation value detection circuit 26 shown in FIG. 8 in the second embodiment of the present invention.

The correlation value detection circuit 26 shown in FIG. 8 first shifts the correlation detection timing from the DPRAM 19 by 5
All the base stations of the 12 delay profiles are read (C-1), and the delay profile having the largest correlation value, that is, the peak correlation value is searched for from each base station (C-2).

Next, when the maximum correlation value obtained for each base station is Pb1, the next maximum correlation value is Pb2, and the minimum correlation value is Pb3 (C-3), Pb1 and Pb2.
(Pb1-Pb2) and the threshold value stored in advance in the RAM 28 are compared (C-4). As a result of this comparison,
When (Pb1-Pb2) is larger than the threshold value, Pb
The stop request signal for the base station No. 2 and the stop request signal for the base station Pb3 are output (C-5).

When the CPU 12 shown in FIG. 3 receives this stop request signal, the CPU 12 outputs the fact to the delay profile circuit control signal and outputs it. By the same processing as that of the first embodiment, the base station of Pb2. Supply of the operation clock to the calculation unit 16 and the RAM control unit 17 for the Pb3 base station and the base station for Pb3. The arithmetic unit 16 and the RAM control unit 17 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

Further, when the CPU 12 receives the stop request signal, the CPU 12 outputs a message to that effect on the timing circuit control signal and outputs it by the same processing as that of the first embodiment for the base station for Pb2 and the base station for Pb3. The supply of the operation clock to the station count unit 31, the comparison unit 32, and the signal generation unit 33 is stopped. The counting unit 31, the comparing unit 32, and the signal generating unit 33 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

In step (C-4), (Pb1-
If Pb2) is less than or equal to the threshold value, the difference between Pb1 and Pb3 (Pb1-Pb3) is compared with the threshold value previously stored in the RAM 28 (C-6). As a result of this comparison,
When (Pb1-Pb3) is larger than the threshold value, Pb
The stop request signal for the base station No. 3 is output (C-7).

When the CPU 12 shown in FIG. 3 receives this stop request signal, the CPU 12 shown in FIG. 3 outputs a message to that effect on the delay profile circuit control signal, and outputs it by the same processing as in the first embodiment. The supply of the operation clock to the arithmetic operation unit 16 and the RAM control unit 17 is stopped. The arithmetic unit 16 and the RAM control unit 17 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

Further, when the CPU 12 receives the stop request signal, it outputs the fact to the timing circuit control signal and outputs it, and by the same processing as in the first embodiment, the counting unit 31 for the base station of Pb3 31 is executed. , Comparison unit 32 and signal generation unit 3
The supply of the operation clock to 3 is stopped. The counting unit 31, the comparing unit 32, and the signal generating unit 33 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

In the second embodiment, the process of returning the operation when the stop request signal is output from the correlation value detection circuit 26 shown in FIG. 8 is the same as the process shown in FIG. Therefore, the description is omitted.

Next, a third embodiment of the present invention will be described. Also in this third embodiment, the block configuration is the same as that of the first embodiment, so that FIG.
Detailed description will be omitted with reference to FIG. 7. Further, also in the present embodiment, as in the second embodiment, the searcher circuit 10 shown in FIG. 3 is not configured to perform independent processing for each of a plurality of base stations that receive at the same time. It refers to the correlation values of the delay profiles of a plurality of base stations.

FIG. 14 is a diagram showing a flowchart of processing for outputting a stop request signal from the correlation value detection circuit 26 shown in FIG. 8 in the third embodiment of the present invention.

The correlation value detection circuit 26 shown in FIG.
All the base stations of the 12 delay profiles are read (D-1), and the delay profile having the largest correlation value, that is, the peak correlation value is searched for from each base station (D-2).

Next, when the maximum correlation value obtained for each base station is Pb1, the next maximum correlation value is Pb2, and the minimum correlation value is Pb3 (D-3), Pb1 and Pb2.
And the difference (Pb1-Pb2) between the threshold and the threshold previously stored in the RAM 28 are compared (D-4). As a result of this comparison,
When (Pb1-Pb2) is larger than the threshold value, Pb
The stop request signal for the base station No. 2 and the stop request signal for the base station Pb3 are output (D-5).

When the CPU 12 shown in FIG. 3 receives the stop request signal, the CPU 12 outputs the fact to the delay profile circuit control signal and outputs it, and the base station of Pb2 performs the same processing as in the first embodiment. Supply of the operation clock to the calculation unit 16 and the RAM control unit 17 for the Pb3 base station and the Pb3 base station. The arithmetic unit 16 and the RAM control unit 17 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

Further, when the CPU 12 receives the stop request signal, the CPU 12 outputs a message to that effect on the timing circuit control signal and outputs it by the same processing as that of the first embodiment for the base station for Pb2 and the base station for Pb3. The supply of the operation clock to the station count unit 31, the comparison unit 32, and the signal generation unit 33 is stopped. The counting unit 31, the comparing unit 32, and the signal generating unit 33 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

In step (D-4), (Pb1-
If Pb2) is less than or equal to the threshold value, the difference between Pb2 and Pb3 (Pb2-Pb3) is compared with the threshold value previously stored in the RAM 28 (D-6). As a result of this comparison,
If (Pb2-Pb3) is larger than the threshold value, Pb
The stop request signal for the base station No. 3 is output (D-7).

When the CPU 12 shown in FIG. 3 receives this stop request signal, it outputs it to the delay profile circuit control signal and outputs it by the same processing as in the first embodiment. The supply of the operation clock to the arithmetic operation unit 16 and the RAM control unit 17 is stopped. The arithmetic unit 16 and the RAM control unit 17 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

Further, when the CPU 12 receives the stop request signal, the CPU 12 outputs a message to that effect on the timing circuit control signal and outputs it, and by the same processing as that of the first embodiment, the counting unit 31 for the base station of Pb3. , Comparison unit 32 and signal generation unit 3
The supply of the operation clock to 3 is stopped. The counting unit 31, the comparing unit 32, and the signal generating unit 33 stop their operations when the supply of the operation clock is stopped, and the power consumption is thereby reduced.

Incidentally, also in the third embodiment,
The process of returning the operation when the stop value request signal is output from the correlation value detection circuit 26 shown in FIG. 8 is the same as the process shown in FIG.

In addition, in the third embodiment,
The threshold value in step (D-4) and the threshold value in step (D-6) shown in FIG. 14 may be set to different values.

In each of the above embodiments, the operations of both the delay profile circuit 9 and the timing circuit 11 are stopped under a predetermined condition, but the present invention is not limited to this, and the delay One of the profile circuit 9 and the timing circuit 11 may be stopped. Here, when only the timing circuit 11 is stopped, when the predetermined time has not elapsed in step (B-2) shown in FIG. 12, for example, step (A-1) shown in FIG. ) May be performed to determine whether to operate or stop the operation of the timing circuit 11 based on the latest delay profile.

When the searcher circuit 10 is constructed for each of a plurality of base stations which receive simultaneously, like the delay profile circuit 9 and the timing circuit 11,
The operation may be stopped under a predetermined condition.

Further, in each of the above-described embodiments, the supply of the operation clock to the delay profile circuit 9 and the timing circuit 11 is stopped under a predetermined condition, but the present invention is not limited to this, and the delay profile circuit is not limited to this. 9 and the timing circuit 11 may be stopped, so that, for example, the delay profile circuit 9
The power supply to the timing circuit 11 may be stopped.

Further, in each of the above-described embodiments, the configuration is such that three base stations can be simultaneously received, but the present invention does not limit the number of base stations that can be simultaneously received to three. At this time, the internal configurations of the delay profile circuit 9, the searcher circuit 10, and the timing circuit 11 are not limited to three, and may be set according to the number of receivable base stations.

[0124]

As described above, according to the present invention, when receiving signals from a plurality of CDMA transmitters at the time of handover, the power consumption of the CDMA communication system can be reduced. A power consumption control method for a communication device and a wireless communication device can be provided.

As an example of a specific numerical value, the current consumed by the delay profile circuit is about 143 mA, and in this case, the current consumption of about 48 mA is reduced by stopping one delay profile circuit for the base station. be able to.

That is, according to the present invention, the operation of the delay profile circuit 9 is stopped according to a predetermined condition for the correlation value, so that the power consumption can be suppressed lower than that of the conventional CDMA system.

Further, according to the present invention, since the searcher circuit 10 and the CPU 12 shown in FIG. 3, which are also used in the conventional CDMA system, make a determination to stop the operation of the delay profile circuit 9, a new Another advantage is that no special hardware is required.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of an example of a CDMA mobile communication system to which a mobile station according to the present invention is applied.

2 is a block diagram showing a communication environment of a CDMA mobile communication system to which the mobile station shown in FIG. 1 is applied.

FIG. 3 is a block diagram of a first embodiment of a mobile station according to the present invention.

FIG. 4 is a diagram showing an example of a configuration of a received signal transmitted from the base station shown in FIG. 1 and received by a mobile station.

5 is a block diagram showing an internal configuration of a first base station delay profile circuit shown in FIG. 3. FIG.

FIG. 6 is a block diagram showing an internal configuration of a calculation unit in the first delay profile circuit for base station shown in FIG.

FIG. 7 is a diagram illustrating a process of obtaining a correlation in the correlation processing unit shown in FIG.

8 is a block diagram showing an internal configuration of a first base station searcher circuit shown in FIG. 3. FIG.

9 is a block diagram showing an internal configuration of a first base station timing circuit shown in FIG. 3. FIG.

10 is a diagram showing a flowchart of processing for outputting a stop request signal from the correlation value detection circuit shown in FIG. 8 in the first embodiment of the present invention.

11 is a diagram illustrating the processing illustrated in FIG.

FIG. 12 is a diagram showing a flowchart of a process for returning the operation when the stop request signal is output from the correlation value detection circuit shown in FIG.

FIG. 13 is a diagram showing a flowchart of processing for outputting a stop request signal from the correlation value detection circuit shown in FIG. 8 in the second embodiment of the present invention.

FIG. 14 is a diagram showing a flowchart of processing for outputting a stop request signal from the correlation value detection circuit shown in FIG. 8 in the third embodiment of the present invention.

FIG. 15 is a block diagram showing a correlation filter of the CDMA receiver disclosed in Japanese Patent Laid-Open No. 9-200177.

[Explanation of symbols]

1 mobile station 2, 2a, 2b, 2c Base station 3 Base station controller 4 exchanges 5 Kanmon Bureau 6a, 6b, 6c cells 7 antenna 8 wireless circuits 9 Delay profile circuit 9a First delay profile circuit for base station 9b Second base station delay profile circuit 9c Third base station delay profile circuit 10 Searcher circuit 10a First base station searcher circuit 10b Second base station searcher circuit 10c Third base station searcher circuit 11 Timing circuit 11a First base station timing circuit 11b Second base station timing circuit 11c Third base station timing circuit 12 CPU 13 Operation clock generation circuit 15 CPU interface section 16 Operation part 17 RAM control section 18 Switch 19 DPRAM 21 Correlation processing unit 22 Power value calculator 23 Power value adder 24 Average value calculator 26 Correlation value detection circuit 27 Timing control circuit 28 RAM 30 CPU interface section 31 counting section 32 comparison section 33 signal generator 34 Switch 51 Delay circuit 52 Weighting Synthesis Circuit 53 Timing control circuit 54 switch element 55 Power

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04B 1/69-1/713 H04J 13/00-13/06 H04B 7/02 H04B 7/26

Claims (3)

(57) [Claims] 1. A plurality of delay profile circuits for creating a delay profile by correlating a received signal with known data at a plurality of timings,
In a wireless communication device of a CDMA communication system having a timing circuit for generating a correlation timing in each of the plurality of delay profile circuits, the number of the plurality of delay profile circuits is N (N is
2 <N is a natural number), and the maximum correlation value of each delay profile created by each of the plurality of delay profile circuits is Pb (N), Pb in descending order.
When (N-1), ... Pb (1), (Pb
When (N) −Pb (i)) (i is a natural number satisfying 1 ≦ i <N) is larger than a predetermined threshold value, the maximum correlation value Pb
(I) The operation of the delay profile circuit that created the delay profile and the operation of the timing circuit that generates the correlation timing in the delay profile circuit is stopped.
A wireless communication device of a CDMA communication system characterized by stopping . 2. A plurality of delay profile circuits for creating a delay profile by correlating a received signal with known data at a plurality of timings, and
In a wireless communication device of a CDMA communication system having a timing circuit for generating a correlation timing in each of the plurality of delay profile circuits, the number of the plurality of delay profile circuits is N (N is
2 <N is a natural number), and the maximum correlation value of each delay profile created by each of the plurality of delay profile circuits is Pb (N), Pb in descending order.
When (N-1), ... Pb (1), (Pb
When (i) −Pb (i−1)) (i is a natural number satisfying 1 <i ≦ N) is larger than a predetermined threshold value, the maximum correlation value P
b (i-1) the delay profile circuit created delay profile ~Pb (1) and Timing for generating a correlation timing in said delay profile circuit
A wireless communication device of a CDMA communication system characterized by stopping the operation of a switching circuit . 3. The plurality of delay profile circuits are for receiving respective signals from a plurality of CDMA transmitters that are simultaneously received, and the plurality of C
A delay profile circuit that creates the delay profile according to the correlation value of the delay profile and a correlation in the delay profile circuit at the time of handover for switching the reception target from any one of the DMA transmitters to the other one claims, characterized in that the stop operation of the timing circuit for generating a timing
A wireless communication device of the CDMA communication system according to Item 1 or 2 .