JP3365909B2 - Digital signal multiplexer - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a digital signal multiplexing apparatus for multiplexing a plurality of service data in a time division on the base band, more particularly, the digital audio broadcasting system European standard receiver about digital signal multiplexing apparatus in the test signal generator utilized in the simulator or the like.

[0002]

2. Description of the Related Art As a broadcasting system for time-divisionally multiplexing service data on a base band, there is a CS PCM music broadcasting system using a CS satellite. This is B
2.048 Mb of PCM music broadcasting format for S broadcasting
The ps signal is a system for multiplexing 6 channels, and the service data to be multiplexed always has a bit rate of 2.04.
It is fixed at 8 Mbps.

Meanwhile, the European digital audio broadcasting system of a digital audio broadcasting standard (hereinafter, referred to as DAB), conventional broadcast (program) service data corresponding to one channel, a plurality of multiplexed in each different bit rates In addition, the format is such that the bit rate of the service data to be multiplexed can be varied during broadcasting without impairing the temporal continuity (hereinafter, also referred to as multiple reconstruction).

European DAB standard (Eupopean Telecommunic
Information Standard, ETS300 401), the information transmitted is a synchronization channel (Syn) on which synchronization information necessary for synchronization on the receiving side is transmitted.
c), a fast information channel in which information necessary for the receiver to select a channel and auxiliary information for a program are multiplexed (hereinafter, a fast information channel (FIC) is also referred to as FIC), It is composed of a main service channel (hereinafter, also referred to as MSC) in which service data such as voice data is multiplexed.

[0005] In digital signal multiplexing apparatus of the DAB standard, multiplexed information (Multiplex Confi
Guration Information (MC
(Also referred to as I)) must be converted to the FIC format and multiplexed. Furthermore, the above-mentioned multiplexing information (MCI)
The MSC must be encoded according to the above. Further, when the bit rate of service data is changed by multiplexing reconfiguration, the encoder setting must be changed at the designated timing. In particular, since time interleaving is performed on a frame-by-frame basis and between frames, and its depth extends to a maximum of 15 frames,
When the bit rate is changed by the multiplex reconstruction, it is necessary to correct the switching timing of the change of the punctured code of the convolutional encoder in consideration of the time interleaving processing time. As a matter of fact, when the bit rate is small, it is necessary to change the punctured 15 frames before the change.

[0006]

However, it is possible to multiplex the service data of a plurality of different bit rates in a form that matches the multiplexing information designated (by the user) in advance, and the bit rate is being signaled. There was no variable digital multiplexer.

According to the present invention, it is possible to multiplex a plurality of service data of different bit rates in conformity with the multiplexing information designated (by the user) in advance, and the bit rate can be changed even during signal transmission. It is an object of the present invention to provide a digital multiplexing device capable of performing the above.

[0008]

Digital signal multiplexing apparatus according to the present invention SUMMARY OF THE INVENTION, in digital signal multiplexing apparatus for multiplexing a plurality of service data in a time division on the base band, based on the instruction information Information generating means for generating multiple information data indicating how the service data is multiplexed and a command having contents matching the multiple information data, and a storage for storing the multiple information data generated by the information generating means. A circuit, conversion means for controlling writing of the multiple information data to the memory circuit and for converting a command generated by the information generating means into a control signal of an encoder, and multiple information data read from the memory circuit. A first encoder for encoding according to the format, and a plurality of service data converted by the conversion means. A second encoder for encoding in accordance with the format, respectively on the basis of the control signal,
A first multiplexing circuit that multiplexes a plurality of service data encoded by a second encoder, and the data encoded by the first encoder and the data multiplexed by the first multiplexing circuit A second multiplexing circuit for multiplexing a plurality of service data having different bit rates.

The multiplex information data indicating how the service data is multiplexed based on the instructed information and the command having the contents matching the multiplex information data are generated by the information generating means, and the generated multiple information data is generated. Is written in the storage circuit and the generated command is converted into the control signal of the encoder by the conversion means, the multiple information data read from the storage circuit is encoded by the first encoder according to the format, and a plurality of service data are obtained. A plurality of service data encoded by the second encoder and encoded by the second encoder are multiplexed by the first multiplexing circuit according to the format based on the control signal converted by the conversion means, and the first multiplexor circuit multiplexes the first and second multiplex service data. The data encoded by the encoder Motor and is multiplexed with data by the first multiplexing circuit is multiplexed by a second multiplexing circuit, service data of different bit rates are more multiplexed.

A digital signal multiplexer according to the present invention writes a plurality of types of multiple information data in a memory circuit,
An encoding control circuit that switches the control signal to the second encoder at a specified frame based on a plurality of types of multiplexed information data read from the storage circuit is provided, and the multiplexing state is maintained while maintaining temporal continuity. It is characterized by being changed periodically.

Plural kinds of multiple information data are written in the memory circuit, and the control signal to the second encoder is switched in the designated frame based on the plural kinds of multiple information data read from the memory circuit. The state of multiplexing is periodically changed while maintaining general continuity.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The following describes the digital signal multiplexing apparatus according to the present invention using embodiments. Figure 1 is a block diagram showing the configuration of a digital signal multiplexing apparatus according to an embodiment of the present invention, one channel and other MPEG service data to be multiplexed MPEG audio signal c
This is an example in the case of one channel of the audio signal c '.

[0013] Before explaining the digital signal multiplexing apparatus according to an embodiment of the present invention, firstly, DAB standard (Eup
open telephone communication S
standard. The basic structure of data defined in ETS300 401) will be briefly described.

As shown in FIG. 7, the transmission frame is composed of a synchronization channel (Sync), FIC and MSC. The FIC is composed of a plurality of 256-bit fast information blocks (hereinafter, FIB (Fast Information Block).
Block)) is also called a data block. The FIB has information about service data multiplexed in the MSC, and an essential part of this control information is multiple information data called MCI. F
ICs are not time interleaved and MSCs are time interleaved.

As shown in FIG. 7, the MSC has one (when the transmission mode is "2" or "3") or four (when the transmission mode is "1") common interleaved based on the transmission mode. Frame (hereinafter CIF (Common In
terleaved frame).
CIF is an MP composed of frames with a cycle of 24 ms
In connection with the EG voice signal, a plurality of encoded service data are multiplexed in a frame of 24 ms. This frame is also the basic unit of time interleave processing. The configuration is shown in FIG.
The relationship between F and MSC is shown in FIG.

As shown in FIG. 8, the CIF is composed of a plurality of sub channels. Here, the subchannel means encoded service data. The CIF is composed of an addressable capacity unit (hereinafter, CU (capacity unit)). The CU consists of 64 bits.
The CIF is composed of 55296 bits, and therefore 864 CUs. In FIG. 8, SubChld indicates a subchannel identification code.

A general structure of the FIB is shown in FIG. FI
B is composed of a plurality of data groups called Fast Information Groups (hereinafter, also referred to as FIG. 1) and a cyclic redundancy code (CRC). FIG includes a FIG header and a FIG data field. The FI header is FI
It consists of 3 bits (b7 to b5) indicating the G type and 5 bits (b4 to b0) indicating the length of the FIG data field.

F in the case of FIG type "0" field
The data field in the IG is constructed as shown in FIG. 10, and the b7 bit C / N is a flag indicating the status of the present multiplex information or the next multiplex information. b4 to b0
A bit (extension) is an identification signal that indicates what kind of information the FIG data field is. The essential information regarding the multiplex structure is the extension "1".
The case is shown in Fig. 11, and in the case of extension 〃0〃
It is shown in FIG.

Field type 0 / exten in FIG . 11
Option 1 corresponds to the structure of the type 0 field in Figure 10.
And, the type 0 field in the FIG data field in the case of FIG type 〃0〃 field extension 〃1〃 (FIG0 / 1), there is as shown in FIG. 11, 10-bit b9~b0 the CU Indicates the start address (0 to 863). Short / long form, short form provides voice service,
The long form represents a data service. For short forms, size and protection are indexed.

FIG. 12 shows the case of FIG type "0" field and extension "0" (FIG0 / 0). The 13 bits of b12 to b0 described as CIF count in FIG. 12 are continued. The count value of the CIF counter that counts the CIFs to be performed is 5 bits of b12 to b8 among them, which are the higher bits of the CIF counter, and the count values of 0 to 19 are the remaining b7 to b0.
8 bits are the lower bits of the CIF counter. The change flag is a flag indicating the presence or absence of multiple reconstruction,
When it is "00", there is no multiplex reconstruction, and in this case no occurrence change is added. Other than that, 8 bits of occurrence change are added.

Since time interleaving is performed between frames and there are 16 interleaving depths ranging from 0 to 15 frames, the interleaving process requires a maximum of 15 frames. Therefore, it is necessary to consider the processing time when multiple reconstruction occurs. 13, the horizontal axis represents the number of frames, the vertical axis represents the bit rate (the number of bits per frame), and FIG. 13A shows the sub-channel No. before time interleaving. Shows the case of 1 to 4C to 6C
When increasing to U, the bit rate is switched at time t2, and when decreasing from 6 CU to 4 CU, at time t
3 shows that the bit rate can be switched. 13B shows the sub-channel No. before time interleaving. 2 shows the case of decreasing from 6 CU to 4 CU, and indicates that the time is changed at time t1 and the time of increasing from 4 CU to 6 CU is changed at time t4. There are 15 frame intervals between times t1 and t2 and between times t3 and t4.

On the other hand, FIG. 13 (c) shows a sub-channel after time interleaving, where time t2.
Indicates the position of the first occurrence change, that is, the first switching position, and the time point t4 indicates the position of the second occurrence change, that is, the second switching position.
Is defined as a fixed number of frames and a minimum of 250 frames.

Returning to FIG. 1, multiple information data (MCI) is displayed on the control device 1 which is a personal computer.
In DAB format (Fast Information B
(corresponding to lockassembler), and a command having contents matched with the multiplex information data is created as a control signal of the MSC encoder. The FIB including the multiple information data (MCI) created in the DAB format is indicated by a, and the command having the contents matching the multiple information data created as the control signal of the MSC encoder is indicated by b. The controller 1 communicates with the CPU 3 through the interface circuit 2.

The FIB data (multiple information data) a created in the DAB format is sent to the CPU3 via the CPU3.
It is stored in the storage circuit 4 under the control of. Stored F
The IB data (multiple information data) a is a CI for each frame.
The scrambling circuit 5 is read in synchronization with the counting of the CIF counter 7, which is a frame counter that counts F.
Scrambled and scrambled FIB in
The data is supplied to the convolutional encoder 6 to be convolutionally encoded and output as FIC data f.

The commands to the MSC encoders 150 and 151 are converted into data that can be easily processed by the encoders 150 and 151 on the CPU 3 and input to the encoder control circuit 8. The control signals d and e output from the encoder control circuit 8 are sent to the convolutional encoder 10 and the multiplexing circuit 12 which is the main service multiplexer, in synchronization with the counting of the CIF counter 7.

The MPEG audio signal c, which is one of the service data inputs supplied to the MSC encoder 150, is supplied to the scramble circuit 9 to be scrambled, and the scrambled MPEG audio signal is convolved under the control of the control signal d. The convolutionally encoded MPEG audio signal supplied to the encoder 10 is supplied to the time interleave circuit 11 and time interleaved.

Similarly, the MPEG audio signal c ', which is the other service data input supplied to the MSC encoder 151, is scrambled and scrambled MPEG.
The audio signal is convolutionally encoded and the convolutionally encoded digital audio signal is time interleaved.

The MPEG audio signal c time-interleaved and output from the MSC encoder 150 and the MPEG audio signal c ′ time-interleaved and output from the MSC encoder 151 are the encoder control circuit 8
Are multiplexed in the multiplexing circuit 12 which is the main service multiplexer controlled by the control signal e from
Converted to MSC data (CIF). Multiplexing circuit 12
The MSC data (CIF) g multiplexed in (1) is further multiplexed with the FIC data f in the multiplexing circuit 13 which is a transmission frame multiplexer and output as a DAB transmission frame.

The operation of the digital signal multiplexing apparatus according to the embodiment of the present invention configured as described above will be described. Corresponding to the two states of multiple reconfiguration, one is called service A, index A, start address A, etc., and the other is called service B, index B.
A name such as the start address B is used.

First, on the controller 1 by the user,
By selecting 〃0〃 or 〃1〃, the multiple reconstruction flag is set to 〃
The position of the occurrence change is specified by specifying one of 0 to 249〃, and the start address A is specified by one of 〃0 to 863〃 by specifying one of 〃0 to 863〃. As a result, index A is 0
The start address B is set by designating one of the numbers 0 to 863, and the index B is set by designating one of the numbers 0 to 63.

Each value designated by the user is directly used as a command b from the controller 1 to the interface circuit 2.
Is sent to the CPU 3 via the, and is converted into data that can be easily processed by the encoder in the CPU 3. The converted data is sent to the control circuit 8.

Further, the FIB data a is generated in the control device 1 based on the respective values designated by the user. This generation is performed by setting the start address, table index, and index (size) in the FIG type “0” and the extension “1” (FIG0 / 1) (see FIG. 11). When the reconstruction flag is set to 〃1〃, that is, when multiple reconstruction is instructed, it is set by the user at the occurrence change position in Fig type 〃0〃, extension 〃0〃 (FIG0 / 0). The value of the set occurrence change is set (see FIG. 12).

The value (0/0) whose value is set in the above
1) and FIG (0/0) are added with FIG headers according to the formats shown in FIGS. 9 and 10, and other F's according to the format shown in FIG.
IG is multiplexed, CRC is added, and it is converted into FIB data a. The FIB data a thus converted and 500 frames are sent to the CPU 3 through the interface circuit 2.

Here, the reason for setting 500 frames is that in the description of FIG. 13, the minimum number of frames between the first and second occurrence positions is specified to be 250 frames. Indicates that at least 250 frames have no change in the multiplexing configuration, and 500 frames can realize the multiplexing state of two service data.

When the multiple reconfiguration flag is set, the start address A and the index A are C / N in one service (A) frame among 500 frames.
Set the flag (see FIG. 10) to FIG (0/1) with “0” (current multiplex configuration) set, and set the C / N flag (see FIG. 10) to 1 for the start address B and index B.
(Next multiple configuration) Set to FIG (0/1).

Further, in the frame of the other service (B) in the 500 frames, the start address B and the index B have the C / N flag (see FIG. 10) set to "0 (current multiplex configuration)" and FIG (0 1), the start address A and the index A are C / N flags (see FIG. 10).
(Refer to) = 1 (next multiple configuration) = (0 /
Set to 1).

When the multiplex reconfiguration flag is not set, that is, when there is no multiplex reconfiguration, the start address and index information are set according to the DAB standard format (FIG (0/1)). Where F
FIG (0/0) and FIG (0/1) in the IB form multiple information data (MCI).

On the other hand, C which counts CIF in frame units
The IF counter 7 is a 13-bit counter, and the upper 5 bits count 0 to 19 and the lower 8 bits 0 to 24.
It is a 5000 (20 × 250) base frame counter that counts nine.

FI in the FIB format generated by the controller 1, the interface circuit 2 and the CPU 3.
The B data a is stored in the storage circuit 4. Here, the storage capacity of the storage circuit 4 is 500, which is the minimum necessary to realize the multiplexed state of two service data as described above.
It is set to the capacity to store the data for the frame.

The storage capacity of the storage circuit 4 will be described. As described above, since the multiplex information is specified to be constant for 250 frames, 500 frames are required to realize the two states. Minute information is required, which determines the storage capacity of the storage circuit 4. On the contrary, since the storage capacity is 500 frames, it is possible to simulate the most severe condition in which the state changes most frequently, that is, the most severe condition in which the state changes every 250 frames.

The contents stored in the memory circuit 4 store the start address and index information according to the DAB standard format (FIG. 0/1). The digital signal multiplexer according to the embodiment of the present invention has two inputs.
If bChld is 1, the start address and index of SubChld = 1 in the format of FIG (0/1),
The start address and index corresponding to the MPEG audio signal c are written. In the example of FIG. 2A, the start address is 0 and the index is 11. The FIG data stored in the memory circuit 4 is CIF.
The data is read in synchronization with the count in the counter 7.

Further, as shown in FIG. 2B, the contents stored in the storage circuit 4 in the case where there is multiple reconfiguration is as follows.
The state of one service A and the state of the other service B are 2
It is switched every 50 frames. The occurrence change is the value of the lower 8 bits of the CIF counter 7 that causes multiple reconstruction. Occurrence change is FIG
It is written in the format of (0/0), and is 100 in this example. Start address and index are written in FIG-(0/0), in this example, for the start address A is one of the services A 0 is,
In the index A, 11 is written, in the other service B, the start address B is 6, and the index B is 10.

The FIB data a, which is the multiplexed data formed as described above and stored in the memory circuit 4, is the CIF.
It is read in synchronization with the counting of CIF by the counter 7, scrambled, scrambled, convolutionally encoded, and sent to the multiplexing circuit 13.

The MPEG audio signal c is one type of service data, which is scrambled by the scramble circuit 9 and convolutionally encoded by the convolutional encoder 10. Upon convolutional encoding, switching of convolutional punctures and the like is controlled according to an index based on the command d output from the encoding control circuit 8. The convolutionally encoded output is time-interleaved in the time-interleave circuit 11,
In the multiplexing circuit 12 which is controlled based on the control signal e output from the encoding control circuit 8, it is multiplexed with other service data and further multiplexed in the DAB transmission format.

Next, the operation of the convolutional encoder 10 will be described. According to the index based on the command d output from the encoding control circuit 8, DAB
As shown in FIG. 14 defined in the standard, MP
The subchannel size, the protection level indicating the error correction strength, and the bit rate are assigned to the EG audio signal c, and the subchannel size (the number of bits per frame) of the output of the convolutional encoder 10 is determined. That is, the convolutional encoder 10 performs punctured according to the index and outputs the punctured code in a specified size.

More specifically, the number of bits input to the convolutional encoder 10 on a frame-by-frame basis depends on the index. Since one frame is 24 ms, for example, in the index 11, data of 56 kbps based on FIG. 14 and 1344 (56 × 24) bits / frame is input to the convolutional encoder 10. The convolutional encoder 10 has 1-bit delay units 21 to 2 as shown in FIG.
It is a convolutional encoder having a constraint length of 7 and a code coding rate of 1/4, which is composed of a shift register 27 composed of 6 and modulo 2 adders 28 to 38, and the input data is 5400 (1344). × 4 + 24) bit mother code.

The first 5376 (128) of 5400 bits
X42) bits are divided into 42 blocks of 128-bit units. 42 blocks of the DAB standard audio service component protection profile shown in FIG.
It is divided into levels (L1 to L4) of 6, 10, 23 and 3 corresponding to the index 11, and punctured indexes (PI1 to PI4) 9, 6, 4 and
5 is assigned.

Further, 42 blocks are divided into sub-blocks of 32 bits, and the punctured index (the first 6 blocks are punctured index 9, the next 10 blocks are punctured index 6 and the next 23 blocks are punctured). The chard index 4 and the last 3 blocks are punctured based on the punctured vector of the DAB standard shown in FIG. 17 using the punctured index 5) as a parameter.
The remaining 24 bits are fixed punctured as tail bits.

In this way, the folding puncture is switched based on the index. That is, the code coding rate is changed using the index as a parameter. The punctured data as described above, 35 CU or 2240 bits in this example, is output. The output from the convolutional encoder 10 is time interleaved. The same operation is performed in the encoder 151.

The time-interleaved outputs sent from the encoders 150 and 151 are supplied to the multiplexing circuit 12 supplied with the start address and size as the control signal e output from the encoder control circuit 8.
Is multiplexed. This multiplexing will be further described. That is, the position to be multiplexed is determined from the start address and the size obtained from the index. FIG. 3 is a diagram showing at which position in the CIF the data is multiplexed.

FIG. 3A shows the case where there is no multiplex reconfiguration, and the start address is 0 and the index is 11, so the subchannel size is 35 in CU units (see FIG. 14).
Therefore, it is multiplexed from 0 CU to 34 CU. CU =
It is 64 bits and the data to be multiplexed is a multiple of 64 bits. 3 (b-1) and 3 (b-2)
Shows the state of service A when there is multiple reconfiguration (see FIG. 3).
(B-1)) and the state of the service B ((b-2) in FIG. 3 is 2)
It switches every 50 frames. In the state of service B, the start address is designated as 6 (CU) (FIG. 3 (b-2)).

When there is no multiplex reconfiguration, the start address and index values are constant. In the case of multiple reconstruction, as shown in FIG. 13, when the bit rate is reduced due to the time interleave relationship, in this example, when the state of service A changes to the state of service B, convolution is performed. The index into the encoder 10 is
Since the data is before time interleave, it can be switched 15 frames before the occurrence change. When the state of the service B is changed to the state of the service A, it is changed by an occurrence change.

Next, regarding the multiplexing circuit 12, since the data is time interleaved in the multiplexing circuit 12, it is always switched by an occurrence change.

These are shown in FIGS. 4 (a) and 4 (b). 4A shows the subchannel size before time interleaving, and FIG. 4B shows the subchannel size after time interleaving. Now, if the lower 8 bits of the count value of the CIF counter 7 are shown, it is as shown in FIG. 5A, and the upper 5 bits LSB (fifth bit) is 250 CIFs as shown in FIG. 5B. Invert when counting. Accordingly, the encoder controller 8 sends an index to the convolutional encoder 10, and the index is switched at the timing shown in FIG. 5C. That is, when the service A is switched to the service B, it is 100 frames to 15 frames before. The encoder controller 8 sends a start address and a subchannel size to the multiplexing circuit 12. The start address and the subchannel size are shown in FIG.
Switching is performed at the timing shown in (d). That is, when switching from the service B to the service A and from the service A to the service B is performed at 100 frames, that is, it is always switched by an occurrence change.

The control device 1 transfers the multiplexed information data equivalent to the contents written in the memory circuit 4 to the CPU 3 as a command. The contents of the command are a multiplex reconfiguration flag, an occurrence change, a start address A, an index A, a start address B and an index B.

The operation of the CPU 3 is shown in the flow chart of FIG. When the command is received,
It is checked whether or not the multiple reconstruction flag is set (step S1). If it is determined in step S1 that the multiplex reconstruction flag is not set,
The sub-channel size of service A is calculated (step S2). Hereinafter, the description that the sub-channel size is calculated means that the sub-channel size is calculated from FIG. Following step S2, the start address A, subchannel size A, and index A are output (step S3). In FIG. 6, the process is marked as “1”.

When it is determined in step S1 that the multiplex reconfiguration flag is set, the subchannel size of service A and the subchannel size of service B are calculated (step S4). Following step S4, it is checked whether the sub-channel size of service A is larger than the sub-channel size of service B (step S5).

If it is determined in step S5 that the sub-channel size of service A is larger than the sub-channel size of service B, start address A, sub-channel size A, index A, start address B, sub-channel size B, index. B, occurrence change A = occurrence change, occurrence change B = occurrence change-15, and occurrence change C = occurrence change are processed and output (step S6). In FIG. 6, the process is marked as “2”.

When it is determined in step S5 that the subchannel size of service A is not larger than the subchannel size of service B, it is checked whether the subchannel size of service A and the subchannel size of service B are equal. (Step S7).

If it is determined in step S7 that the sub-channel size of service A and the sub-channel size of service B are equal, the start address A, sub-channel size A, index A, start address B, sub-channel size B, The processes of index B, occurrence change A = occurrence change, occurrence change B = occurrence change, and occurrence change C = occurrence change are performed and output (step S8). Processing in Figure 6 = 3
Is written.

If it is determined in step S7 that the sub-channel size of service A and the sub-channel size of service B are not equal, start address A, sub-channel size A, index A, start address B, sub-channel size B , Index B, occurrence change A = occurrence change-1
5. Occurrence change B = occurrence change, occurrence change C = occurrence change are processed and output respectively (step S9). In FIG. 6, the process is designated as " 4 ".

The above processing 〃1〃, processing 〃2〃, processing 〃3
The processing output of one of 〃 and processing 〃4〃 is input to the encoder control circuit 8. When the multiplex reconstruction flag = 0 (when the processing output of the processing “1” is transmitted), the index A is sent to the convolutional encoder 10, and the start address A and the size A are sent to the multiplexing circuit 12.

When the multiple reconstruction flag = 1 (Processing 2
When 〃, process 〃 3 〃, or one process output of process 〃 4 〃 is sent, the index sent to the convolutional encoder 10 is an odd frame (of the upper 5 bits of the CIF counter). When the LSB is 0, the index is switched to the index A at the timing of the occurrence change A, and the even frame (the LSB of the upper 5 bits of the CIF counter is
In 1), it switches to index B at the timing of occurrence change B.

In the multiplex circuit 12, the start address A and the sub-channel size A are switched at the timing of occurrence change C in the odd frame and the start address B in the timing of occurrence change C in the even frame.
And switch to size B.

[0065]

As described above, according to the digital signal multiplexer of the present invention, a plurality of service data having different bit rates can be multiplexed in conformity with the multiplexing information designated in advance (by the user). And the bit rate can be changed even during signal transmission.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a digital signal multiplexing apparatus according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining stored contents of a storage circuit in the digital signal multiplexing apparatus according to the exemplary embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining a CIF multiplexing position in the digital signal multiplexer according to the embodiment of the present invention.

FIG. 4 is a schematic diagram for explaining a change in subchannel size at the input / output of the time interleave circuit at the time of multiplex reconfiguration in the digital signal multiplexer according to the exemplary embodiment of the present invention.

FIG. 5 is a schematic diagram for explaining the switching timing at which the encoding control circuit outputs a control signal at the time of multiplex reconfiguration in the digital signal multiplexing device according to the exemplary embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation when the CPU receives a command in the digital signal multiplexing device according to the exemplary embodiment of the present invention.

FIG. 7 is a schematic diagram showing a configuration of a transmission format used in the digital signal multiplexing apparatus according to the embodiment of the present invention.

FIG. 8 is a schematic diagram showing a relationship between a CIF, a sub-channel, and a CU used in the digital signal multiplexing apparatus according to the embodiment of the present invention.

FIG. 9 is a schematic diagram showing a configuration of an FIB format used in the digital signal multiplexing apparatus according to the embodiment of the present invention.

FIG. 10 is a schematic diagram showing a format configuration of a FIG type “0” field used in the digital signal multiplexing apparatus according to the embodiment of the present invention.

FIG. 11 is a schematic diagram showing the configuration of the format of FIG type “0” field / extension “1” used in the digital signal multiplexing apparatus according to the embodiment of the present invention.

FIG. 12 is a schematic diagram showing the configuration of the format of FIG type “0” field / extension “0” used in the digital signal multiplexing apparatus according to the embodiment of the present invention.

FIG. 13 is a schematic diagram for explaining switching at the time of multiplex reconfiguration of the convolutional encoder used in the digital signal multiplexer according to the embodiment of the present invention.

FIG. 14 is a diagram showing a relationship (punctured information) between an index and a sub-channel size in the digital signal multiplexing device according to the exemplary embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a convolutional encoder used in the digital signal multiplexing apparatus according to the exemplary embodiment of the present invention.

FIG. 16 is a diagram showing a relationship between an index and a protection profile in the digital signal multiplexing device according to the exemplary embodiment of the present invention.

FIG. 17 is a diagram showing a punctured vector in the digital signal multiplexing device according to the exemplary embodiment of the present invention.

[Explanation of symbols]

1 control device 2 Interface circuit 3 CPU 4 memory circuits 5 and 9 scramble circuits 6 and 10 convolutional encoders 7 CIF counter 8 Encoder control circuit 11 Time interleave circuit 12 and 13 multiple circuits

Front page continuation (72) Inventor Atsushi Tsurumi 1-14-6 Dogenzaka, Shibuya-ku, Tokyo Kenwood Co., Ltd. (56) Reference JP-A-4-111550 (JP, A) JP-A-6-276169 ( (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 3/00-3/26 H04L 5/22-5/26

Claims (2)

(57) [Claims] In digital signal multiplexing apparatus for multiplexing a plurality of service data to time division 1. A baseband on,
Information generating means for generating multiple information data indicating how the service data is multiplexed based on the instructed information and a command having contents matching the multiple information data; and the multiple information generated by the information generating means. A storage circuit for storing the information data, a conversion means for controlling the writing of the multiple information data to the storage circuit, and a conversion means for converting the command generated by the information generation means into a control signal of an encoder, and read from the storage circuit. A first encoder that encodes the generated multiple information data according to a format, a second encoder that encodes a plurality of service data according to the format based on the control signal converted by the conversion means, and a second encoder Multiplex multiple encoded service data Service data having different bit rates, including a first multiplexing circuit and a second multiplexing circuit that multiplexes the data encoded by the first encoder and the data multiplexed by the first multiplexing circuit. digital signal multiplexing apparatus characterized by multiple multiplexing. 2. The digital signal multiplexer according to claim 1, wherein a plurality of types of multiplexed information data are written in a storage circuit, and a second encoder is supplied with the plurality of types of multiplexed information data read from the storage circuit. includes an encoding control circuit to switch the specified control signal frame, digital signal multiplexing apparatus characterized by periodically changing the state of the multiplexed keep continuity in time.