JP3363679B2 - Pattern formation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine pattern on a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In forming a pattern in a method for manufacturing a semiconductor integrated circuit, a resist material having photosensitivity to an exposure light source is subjected to lithography.
PHY) is used for patterning. In recent years, as the level of integration of semiconductor integrated circuits has increased, the level of steps on the substrate for lithography has increased, while the patterns such as wiring and interlayer contacts have become finer, making it easier for the wiring to break due to surface irregularities. Is becoming difficult to form.

In order to solve this problem, 1986 SP
IE Vol. 631, pp. 34-39, "DESIR
E: a novel dry developed r
2 as shown in FIG.
A process called the ESIRE method has been proposed. FIG. 2 is a cross-sectional process diagram of a conventional method for forming a pattern of a semiconductor integrated circuit, which is called a DESIRE method.

First, as shown in FIG. 2a, a negative reaction of about 1.5 μm, which is sufficient to eliminate the unevenness of the substrate, is formed on the substrate 1 of the semiconductor integrated circuit having the unevenness of about 0.5 μm on the surface due to high integration. The resist 2 is laminated, and then the reaction resist 2 is exposed at a predetermined position by light 4 such as ultraviolet rays through an opening of a mask 3 having a dark field and an opening at a predetermined position in a plane.

As a result, as shown in FIG. 2b, only the surface of the 1.5 μm thick reaction resist 2 is exposed, and the exposed portion 5 becomes a surface latent image along the exposure pattern of 0.5 μm in thickness. To form a rectangle. First, the shape of the exposure unit 5 depends on the opening radius of the mask and the wavelength of light used for exposure.
Secondly, depending on the optical properties of the reaction resist, the exposed portion may be approximated to a rectangle if the opening radius of the mask is 0.3 μm and the light is in the ultraviolet region.

Next, as shown in FIG. 2c, the DESI
Silylation, which is a feature of the RE method, proceeds from the surface of the reaction resist. That is, when the vapor 6 of HMDS (hexamethyldisilazane), which is a kind of silicone, is brought into contact with the entire surface of the reaction resist covering the substrate in a vapor phase to cause a chemical reaction, only the exposed portion is selectively silylated. Then, the semi-circular metamorphic portion 7 is formed.

Generally, the silylation reaction is known as a reaction in which a silicon-containing group chemically bonds to a hydroxyl group of a reactant. Here, since the silylated metamorphic part 7 has a Si-containing group, it becomes a layer resistant to the subsequent O ₂ anisotropic etching. Therefore, when anisotropic etching using oxygen is performed as shown in FIG. 2D, the reaction resist 2 having a line width similar to that of the exposed portion is formed under the metamorphic portion 7.

The above description is a negative resist process using a gas phase reaction of HMDS for the silylation reaction, but in recent years, various other silylating agents have been investigated, and a wafer is silylated depending on the material. A so-called liquid-phase silylation method of immersing in an agent solution may be used. Alternatively, the positive or negative image of the resist pattern finally obtained also differs depending on each process.

Surface exposure using these silylation reactions
The dry development process is currently TSI (Top Surfa).
(Ce Imaging) method, and there are particular expectations for lithography that uses short-wavelength light in which there is a concern that resist light absorption or substrate reflection may increase.

[0010]

However, the TSI method is a very effective forming method when the line width to be formed is about 10 μm, but has a drawback that some problems occur when the line width becomes 1 μm or less. there were. FIG. 3 is a mechanism diagram showing a problem when the line width of the formed pattern is narrow.

The first problem is that the line width of the metamorphic portion to be silylated and the line width of the exposed portion are different from each other by at least 0.2 μm due to the limit of silylation selectivity. The second problem is that since the silylation is caused by diffusion, the cross-sectional area of the silylation is likely to change due to the heat treatment in the subsequent step of the silylation. In FIG. 3, a reaction resist 2 that is easily silylated is formed on a substrate 1 having irregularities, and an exposed portion 5 and a metamorphic portion 7 are located on top of the reaction resist.

Referring to the configuration of FIG. 3, the first problem is that the reaction resist of the lower layer is etched by the line width of the metamorphic portion because the line width of the exposed portion is different from the line width of the metamorphic portion. You can see that Similarly, referring to the arrow in FIG. 3, the silylation in the thickness direction does not pose a problem, but the second problem that the line width tends to change due to the progress of the silylation in the width direction occurs. I understand.

As described above, since the TSI process is a patterning method using the surface exposure region of the single layer resist,
It is extremely difficult to control a fine line width. An object of the present invention is to stably and faithfully form a fine pattern on a highly integrated semiconductor circuit.

[0014]

According to a first aspect of the present invention, there is provided a pattern forming method, comprising: a first step of forming a non-reactive resist inert to a silylation reaction on a substrate; The second step of forming a pattern composed of a reactive resist active against the silylation reaction, and exposing the reactive resist pattern and the exposed surface of the non-reactive resist to a silylation reaction treatment environment to expose the reactive resist pattern . a third step of <br/> Lil reduction, seen including a fourth step of etching the non-reactive resist the reaction resist pattern silylated as a mask, a second step and the
The reaction resist pattern is exposed between the step 3 and
The reaction resist pattern is easily silylated.
It is the gist to carry out the process of putting into a state .

A pattern forming method according to a second aspect is the first aspect.
In the invention described in (1), the gist is that the etching is performed in a state where the substrate is cooled.

[0016]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described with reference to the drawings. (First Embodiment) FIG. 1 is a sectional process drawing of a first embodiment of a pattern forming method of the present invention. FIG. 1 is characterized in that a thin reactive resist is located on a thick non-reactive resist, as compared with the prior art pattern forming method of FIG.

First, a non-reactive resist 8 of 1100 nm thickness made of OFPR-800 (Tokyo Ohka g-line resist) is applied on the substrate 1, and it is placed on a hot plate at 250 ° C.
Hard baking is performed for 90 s to make it inert to the silylation reaction. Then, ZIR-ST11 (i-line resist manufactured by Zeon Corporation) is applied on the inactivated non-reactive resist 8.
A reactive resist 2 which is active against the silylation reaction is formed into a film with a thickness of 490 nm and prebaked at 90 ° C. for 60 s.

Subsequently, as shown in FIG. 1a, a light intensity is obtained by using a mask 3 and an i-line light 4 from the reaction resist side of the substrate in which the substrate 1, the non-reactive resist 8 and the reactive resist 2 are laminated in this order. An exposure of 130 mJcm ^-2 is performed. Next, this substrate is developed under standard developing conditions of ZIR-ST11, and only the exposed portion 5 made of the reactive resist is left on the non-reactive resist 8 as shown in FIG. 1b.

Further, the exposed area 5 scattered on the non-reactive resist 8 is subjected to the entire surface exposure of 150 mJcm ⁻² by using the i-ray light so that the exposed area made of the reactive resist is easily silylated. Then, as shown in FIG. 1c, for a resist having a hydroxyl group on the interface on the substrate, trimethylchlorosilane having an alkylsilyl group, dimethylchlorosilane,
Vapor 6 such as HMDS is brought into contact at 200 ° C. to allow a chemical reaction to proceed, and the exposed portion is silylated to form a metamorphic portion 7.

In this case, the pattern is already formed by the exposed portion of the reaction resist during the silylation reaction, and the exposed portion is all active for the silylation reaction under the above conditions. On the other hand, in the unreacted resist located in the lower layer of the exposed portion, the Si-containing group is not introduced even during the silylation reaction of the upper layer.

This means that after completion of the silylation reaction, S
O ₂ , C on the non-reactive resist without introduction of i group
The reaction resist introduced with Si group resistant to plasma of at least one gas of O ₂ and NH ₃ is formed as a contact type pattern mask, and anisotropic plasma etching is used. Dry development is possible.
Finally, using the ECR etching device, 5 mTorr
O ₂ plasma etching was performed at the gas pressure of
A transfer pattern of the lower non-reactive resist 8 is formed on the substrate 1 as shown in FIG. This and
, Anisotropic dry etching in oxygen or nitrogen is used
By doing so, the resist in the lower layer is accurately etched in the metamorphic area.
You can hunt.

At this time, in order to perform good etching with less side etching, liquid nitrogen is circulated under the sample stage of the substrate to cool the substrate. After forming a conductive layer on a substrate having irregularities by implanting ions into a portion where the non-reactive resist is removed, first 100
By depositing 1 nm of Ti and then 900 nm of Al to dissolve the non-reactive resist, fine metal wiring can be stably and faithfully formed on the highly integrated semiconductor circuit.

In the above embodiment, the non-reactive resist is one layer, but a plurality of layers may be used in order to eliminate the influence of the unevenness of the substrate. In addition, we proposed a silylated part as a metamorphic part and plasma etching as an etching condition. The metamorphic part should have a smaller etching rate / thickness than the lower non-reactive resist, and reactive ion etching can be used. The etching anisotropy may be larger than the aspect ratio of the groove formed in the non-reactive resist.

[0024]

According to the pattern forming method of the present invention,
Since the shape of the region to be silylated is defined in advance by the patterning shape of the reaction resist, the conventional TS
There is no line width variation due to lateral diffusion of silylation in a single layer resist as in the I process, and the line width controllability of the resulting resist pattern is improved.

Alternatively, it becomes possible to provide a highly integrated semiconductor circuit having stable characteristics with good reproducibility. Further, as an individual effect, since the pattern forming method of the present invention utilizes the silylation reaction, the exposed portion can be reacted reliably and can be used as an etching mask.

[0026]

[Brief description of drawings]

FIG. 1 is a pattern forming process diagram of a reactive resist / non-reactive resist structure of the present invention.

FIG. 2 is a pattern forming process diagram of a conventional reactive resist structure.

FIG. 3 is a cross-sectional view showing a problem of a conventional pattern forming method.

[Explanation of symbols]

1 substrate 2 Reaction resist 3 masks 4 light 5 Exposure section 6 steam 7 metamorphosis department 8 Non-reactive resist

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 7/38 G03F 7/40

Claims (2)

(57) [Claims] 1. A first step of forming a non-reactive resist inert to a silylation reaction on a substrate, and a pattern made of a reactive resist active to the silylation reaction on the non-reactive resist. And a third step of exposing the reaction resist pattern and the exposed surface of the non-reactive resist to a silylation reaction treatment environment to silylate the reaction resist pattern , and the silylated reaction. It viewed including a fourth step of etching the non-reactive resist the resist pattern as a mask, a, between the second step and the third step, the reaction
The resist pattern is exposed to the reaction resist pattern.
A method for forming a pattern, which comprises performing a step of making a silane easily silylated . 2. The pattern forming method according to claim 1 , wherein the etching is performed while the substrate is cooled.