JP3363665B2 - CIF compatible video camera - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera,
In particular, for example, a common intermediate format (CI) defined to resolve differences in television systems between regions and to allow all codecs to communicate without being aware of the other party.
F: a CIF compatible video camera that outputs a video signal compliant with Common Intermediate Format). 2. Description of the Related Art The International Telecommunication Union (ITU) has adopted H.264 as a moving picture compression encoding method for a narrowband videophone / videoconference system. 261 is recommended. In this recommendation, 288 (line / frame) × 29.97 (frame / second) is defined as the CIF, and a pixel speed of 6.75 MHz for a video signal is derived from the CIF. On the other hand, in the conventional PAL video camera 1 shown in FIG. 3, a PAL-compatible CCD (C) having 575 vertical effective pixels is provided in accordance with a pulse output from the pulse generator 2 based on a 28.375 MHz master clock.
Harge Coupled Device) 3 operates, whereby the video signal of 25 frames / sec photoelectrically converted is correlated double-sampled by the pre-processing circuit 4 and YC-separated. The luminance signal generation circuit 5 adds a synchronization signal to the luminance signal Y ₁ output from the pre-processing circuit 4 and performs processes such as gamma correction and contour enhancement to generate a luminance signal Y ₂ . On the other hand, the color difference signal chrominance signal generating circuit 6 based on the chroma signal C ₁ from the pre-processing circuit 4 R-Y and B-Y
And gives them to the color encoder 7. Color encoder 7 adds a color burst signal to create a chroma signal C ₂ together with applying a balanced modulation to the color difference signals R-Y and B-Y. Luminance signal Y ₂ and chromaticity signal C ₂
Is then supplied to the YC mixing circuit 9 and the YC mixing circuit 9
Output a composite video signal conforming to the PAL format. In order to generate a digital luminance signal y and digital point-sequential color difference signals u and v based on the CIF from the composite video signal, a YC for separating the composite video signal into a luminance signal Y and a chromaticity signal C is used. A / A for converting the luminance signal Y and the chromaticity signal C into an 8-bit digital luminance signal y and a digital chromaticity signal c
A D converter, a sync separation / PLL circuit for creating a synchronization signal and a color subcarrier from a composite video signal, and creating digital point-sequential color difference signals u and v from a digital chromaticity signal c based on the created color subcarrier. Color decoder, C with phase locked to separation sync signal
A PLL circuit for generating a pixel clock of IF and a digital luminance signal y and digital chromaticity signals u and v are set to 1
It is necessary to further provide a field frame dropping circuit for dropping frames every field. [0005] Therefore, if a video camera for generating a signal conforming to the CIF based on the PAL video camera 1 is to be constructed, a problem arises in that a wasteful circuit configuration results. was there. That is,
The color encoder 7, the color decoder, the YC mixing circuit 9 and the YC separation circuit, and the synchronization addition circuit and the synchronization separation circuit included in the luminance signal creation circuit 5 perform processes opposite to each other, and are useless circuits. SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a CIF-compatible video camera which can be constructed without wasting the circuit. [0007] The present invention provides a 34 MHz
Master clock generating means for generating a master clock of
6.8 MHz clock generating means for generating a 6.8 MHz clock based on the master clock, and 3.4 MHz generating a 3.4 MHz clock based on the master clock
Clock generating means, a PAL-compatible image sensor that operates based on a master clock and outputs a video signal having the same line / frame as that of the PAL system and corresponding to a subject image, and a luminance signal generating unit that generates a luminance signal Y based on the video signal Means for generating color difference signals RY and BY based on a video signal; means for converting a luminance signal Y into a digital luminance signal y in response to a 6.8 MHz clock;
, A multiplexer that receives the color difference signals RY and BY and outputs the dot-sequential color difference signals U and V according to a 3.4 MHz clock, the dot-sequential color difference signals U and V according to a 6.8 MHz clock A second A / D converter for converting V into digital point-sequential color difference signals u and v, and a digital luminance signal y and a digital point-sequential color difference signal u
This is a CIF-compatible video camera including frame dropping means for dropping frames every other field. A PAL-compatible image sensor having 575 vertical effective pixels operates based on a master clock of 34 MHz, thereby outputting a 575 (line / frame) × 29.97 (frame / second) video signal. Is done. The luminance signal generating means generates a luminance signal Y based on the video signal, and the luminance signal Y is converted into a digital luminance signal y by a first A / D converter. Since the first A / D converter operates with a 6.8 MHz clock, the pixel speed of the digital luminance signal y is 6.8 MHz. On the other hand, the color difference signal creating means
Color difference signals RY and BY are created based on a video signal from a PAL-compatible image sensor. The multiplexer is
The color difference signals RY and B according to the 3.4 MHz clock
−Y to generate dot-sequential color difference signals U and V,
/ D converter is a point-sequential color difference signal U with a 6.8 MHz clock.
And V are converted to digital point-sequential color difference signals u and v. Therefore, the pixel speed of each of the digital dot-sequential color difference signals u and v is 3.4 MHz. The digital luminance signal y and the digital dot-sequential color difference signals u and v thus created are dropped every other field by the dropping means, so that, for example, the format of the video signal output from the monitor is 287. 5 (lines / frame) × 29.97 (frames / second), which complies with the CIF. According to the present invention, since the luminance signal Y and the chrominance signals RY and BY are subjected to the processing corresponding to the CIF directly, the circuit is configured to be efficient. Can be. The above and other objects of the present invention,
Features and advantages will become more apparent from the following detailed description of embodiments, which proceeds with reference to the accompanying drawings. Referring to FIG. 1, a CIF compatible video camera 10 of this embodiment includes a master clock generating circuit 12 for generating a master clock of 34.015 MHz. Output pulse. That is, the pulse generator 14
Outputs a clock for driving the CCD to the PAL-compatible CCD 16, and the PAL-compatible CCD 16 operates at approximately 1.2 times the speed of the conventional CCD in response to the clock, and 575 (line / frame) × 29.97 (frame / second) ) Is output. This video signal is applied to the pre-processing circuit 18 and subjected to correlated double sampling and YC separation according to the sampling clock and YC separation clock provided from the pulse generator 14. The chrominance signal generation circuit 20 converts the chrominance signal C ₁ output from the pre-processing circuit 18 into the chrominance signal RY and the chrominance signal RY based on the 1H delay line driving clock and the clamp pulse output from the pulse generator 14. Create BY. On the other hand, the luminance signal creation circuit 22
Applying a process such as gamma correction and edge enhancement on the luminance signal Y ₁ output from, to create a luminance signal Y _2. The luminance signal generation circuit 22 is different from the conventional one in that the luminance signal Y
_No synchronization signal is added to ₁ . That is, conventionally, gamma correction, edge enhancement is applied to the luminance signal Y _1, but the synchronization signal generated by the pulse generator has been added, in this embodiment, the pulse generator 14 is not able to output a synchronizing signal , nor that the synchronizing signal is added to the luminance signal Y ₁ by the luminance signal generation circuit 22. The pulse generator 14 has the same configuration as the conventional one, and specifically, an integrated circuit "CX" manufactured by Sony Corporation.
D1257AR "and" CXD1159Q "as shown in Fig. 2. That is, the integrated circuit 14
a is a 34.015 MHz master clock which is frequency-divided by 与 え る and applied to the integrated circuit 14b. The integrated circuit 14b creates a horizontal synchronizing signal and a vertical synchronizing signal based on the 1/2 frequency-divided clock, and supplies these to the integrated circuit 14a.
Then, the integrated circuit 14a creates a desired pulse based on the horizontal synchronizing signal and the vertical synchronizing signal, and
D16, the preprocessing circuit 18 and the color difference signal creation circuit 20. The master clock output from the clock generation circuit 12 is also frequency-divided by the frequency divider 24 by 5 and the 6.8 MHz clock frequency-divided by 5 is divided by 2 by the frequency divider 30.
Is divided by 2. Then, the A / D converters 26 and 28 operate according to the 6.8 MHz clock, and the multiplexer 32 operates according to the divided 3.4 MHz clock. Therefore, the A / D converter 26 outputs the luminance signal Y
₂ is converted to a digital luminance signal y at a conversion speed of 6.8 MHz. The multiplexer 32 has a frequency of 3.4 MHz.
The dot-sequential color difference signals U and V are created from the color difference signals RY and BY in accordance with the clock, and the A / D converter 28
The dot-sequential color difference signals U and V are converted into digital point-sequential color difference signals u and v at a conversion speed of 6.8 MHz. As a result, the pixel speed of the digital luminance signal y becomes 6.8 MHz, and the pixel speed of each of the digital dot-sequential color difference signals u and v becomes 3.4 MHz. The digital luminance signal y and the digital dot-sequential color difference signals u and v are then converted into a field frame dropping circuit 30.
, Whereby each signal is dropped every other field. Therefore, the number of lines per frame of the video signal generated based on the digital dot-sequential color difference signals u and v and the digital luminance signal y, which have been dropped, is 287.5 lines. By configuring the CIF-compatible video camera 10 in this manner, the PAL-compatible CCD 16 outputs a video signal of 29.97 frames per second,
Satisfies the condition of IF. The pixel speed of the digital luminance signal y output from the A / D converter 26 is 6.8 MHz.
Since the pixel speed of each of the dot-sequential color difference signals u and v output from the A / D converter 28 is 3.4 MHz, the condition of the pixel speed derived from the CIF is satisfied.
Further, the digital luminance signal y and the digital point-sequential color difference signals u and v are
Are dropped every other field, so the number of lines per frame of the video signal output to the monitor is 2
87.5, which also satisfies the condition of CIF. According to this embodiment, the CIF is directly applied to each of the luminance signal Y ₂ and the color difference signals RY and BY.
, The circuit can be configured to be efficient. Further, a PLL circuit for generating color subcarriers and a C
Since a PLL circuit for generating the IF pixel clock is not required, the circuit scale can be reduced. Since the pulse generator 14 has the same configuration as the conventional one, the frequency of the output pulse is 1.2 times that of the conventional one, so that not only the PAL-compatible CCD 16 but also the preprocessing circuit 18 and the color difference signal generating circuit 20 Although it operates at twice the speed, this difference in operating speed is within the permissible range of the pre-processing circuit 18 and the color-difference signal generation circuit 20, so there is no problem in operation.

[Brief description of the drawings] FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a part of the embodiment in FIG. 1; FIG. 3 is a block diagram showing a conventional technique. [Explanation of symbols] 10. CIF compatible video camera 12. Clock generation circuit 20… Color difference signal creation circuit 22 ... luminance signal creation circuit 26, 28 ... A / D converter 32… Multiplexer 34… Field frame dropping circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/00-11/22

Claims (1)

(57) Claims: 1. A master clock generating means for generating a 34 MHz master clock; a 6.8 MHz clock generating means for generating a 6.8 MHz clock based on the master clock; A 3.4 MHz clock generating means for generating a 3.4 MHz clock based on the PAL; a PAL-compatible image sensor that operates based on the master clock and outputs a video signal corresponding to a subject image and having the same line / frame as the PAL system; A luminance signal generating unit that generates a luminance signal Y based on a video signal; a color difference signal generating unit that generates color difference signals RY and BY based on the video signal; the luminance signal according to the 6.8 MHz clock A first A / D converter for converting Y into a digital luminance signal y, the color difference signals RY and It said 3.4MH received a -Y
a multiplexer for outputting dot-sequential color difference signals U and V in response to the z clock; a second A / which converts the dot-sequential color difference signals U and V to digital point-sequential color difference signals u and v in response to the 6.8 MHz clock; A CIF-compatible video camera, comprising: a D converter; and a frame dropping unit that drops the digital luminance signal y and the digital dot-sequential color difference signals u and v every other field.