JP3356211B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a word line driving circuit.

[0002]

2. Description of the Related Art FIG. 6 is a circuit layout diagram showing a conventional example of a semiconductor memory device, FIG. 7 is a circuit diagram showing a portion A in FIG.
FIG. 8A is a circuit diagram showing the contents of SWD in FIG.
7 is a circuit diagram showing the contents of RAID in FIG. 7, and FIG. 9 is an operation waveform diagram showing a conventional example. Here, for convenience, the process of outputting data of the memory cell M0nm connected to SWL00m and BLT0nm in FIG. 7 will be described. However, the present invention can be applied to other memory cell data output or memory cell data input. There is no essential difference in the operation regarding.

FIG. 6 is a circuit layout diagram of a memory cell array using a hierarchical word line system. XDEC indicates an area where a plurality of row decoders are arranged, and YDEC indicates an area where a plurality of column decoders are arranged. Each row decoder selects and drives main word line MWL according to a row address signal input from the outside. Each column decoder applies a column select line Y according to an externally input column address signal.
Select and drive SW. SA indicates an area where a plurality of sense amplifiers are arranged, SWD indicates an area where a plurality of sub-word driving circuits are arranged, and CELL indicates an area where memory cells are arranged in a lattice. Complementary bit lines BLT and BLN are connected to each sense amplifier, and SWD
Is connected to a sub-word line SWL, and each intersection is connected to a memory cell.

FIG. 7 shows a circuit diagram of a portion indicated by A in FIG. When the cell array shifts from the inactive state to the active state, one of the row decoders arranged in row select circuit area XDEC is selected by an external address not explicitly shown in the figure, and main word line MWL0 is selected. Activate. Next, among the sub-word line drive signals RAI0 to RAI3 included in every other sub-word line drive circuit SWD column by an external address not explicitly shown in the drawing, RAI
Activate 0. At this time, the activated sub-word line drive circuits SWD columns are every other column including A, and the sub-word line drive signals RAI connected to the other alternate SWD columns are arranged.
None of 0 to 3 are activated. SWD0 to SWD
n is a sub-word line driving circuit, which is a main word line MWL0 selected and driven by the row decoder XDEC.
And the sub-word line SWL00m selected by both the sub-word line power supply signal RAI0m and the sub-word line power supply signal RAI0m. The sub-word line SWL00m is connected to the sub-word line drive circuit SWD
0 are arranged in two cell areas adjacent to both ends.

In FIG. 7, YDEC0m to YDECi
-1m is a column selection circuit, YSW0m to YSWi-1m are column selection lines, SA00m to SAin + 1m are sense amplifiers,
SWL00m to SWL3nm are sub-word lines, RAI0
m to RAI3m are sub-word lines, RAIB0m to RAI
B and RAIBn are sub-word line inactivation signals, RAID
Denotes a sub word line drive circuit, BLT0 nm to BLTin +
1m, BLN0mm to BLNin + 1m are bit lines, L
IOT00m to LIOT1n + 1m, LION00m to
LION1n + 1m is a local data input / output line, GIOT0
m to GI03m and GION0m to GION3m are wide area data input / output lines.

In FIG. 7, a sub-word line drive circuit SWD0 is provided.
8 (A) shows the contents of SWDn. These are NMO
Since it is a sub-word line drive circuit composed of only S transistors and does not include a PMOS transistor, no PN element isolation region is required on the semiconductor substrate.
Realization is possible with a small area. This circuit is disclosed, for example, in Japanese Patent Application Laid-Open No. 9-63261.

The sub-word line drive circuit RA shown in FIG.
FIG. 8B shows the contents of the ID. This circuit activates the RAI signal corresponding to 3 bits X0 to X2 of the external address among the subword line drive signals RAI0 to RAI3 while the subword line drive timing signal RAE is at a high level. Here, a circuit for activating the RAI signal when X0 is at a low level, that is, when the row address is an even number, has been described. However, for an adjacent SWD column, a circuit for activating the RAI signal when X0 is at a high level Is connected. RAIB0 to RAIB3 are complementary signals of the sub-word line drive signals RAI0 to RAI3, respectively.

Next, the operation of the sub-word line drive circuit SWD will be described. FIG. 9 is an operation waveform diagram of the sub-word line drive circuit SWD. Initial state, sub-word line drive circuit SWD
Of the main word lines MWL0 to MWL3 are at the low level. Therefore, the main word line MW via the transistors T00 to T30 whose gates are fixed at a high level.
The potentials of the nodes N0 to N3 connected to L are also at the low level, and all the drive transistors T01 to T03 are in the off state. Also, the sub word line drive signal RAI
Since 0 to 3 are at the low level in the initial state, all the transistors T01 to T33 are also off. On the other hand, the sub-word line drive signals RAI0 to RAI
The potentials of RAIB0 to RAIB3, which are complementary signals of AI3, are all at the high level, and the sub word line SWL
The potentials 0 to 3 are held at low level by the transistors T02 to T32.

When selecting and activating the sub-word line SWL0, first, the potential of the main word line MWL is set to a high level. As a result, the potentials of the nodes N0 to N3 are respectively applied to the main word line from the high level potential of the MWL by the transistor T.
The potential becomes lower by the threshold voltage of 00 to T30. Next, while the potentials of the sub-word line drive signals RAI1 to RAI3 are fixed at a low level, the potential is driven to a high level by the sub-word line drive signal RAI0. Since the transistor T01 has a capacitance between the sub-word line drive signal RAI0 as the source electrode and the node N0 as the gate electrode, the potential at the node N0 also changes due to the capacitive coupling with the change in the potential of the sub-word line drive signal RAI0. At this time, the potential difference between the node N0 after the change and the potential of the main word line MWL becomes the transistor T00
Current does not flow from node N0 to main word line MWL unless the threshold voltage is exceeded. As a result, the node N
The potential of 0 is higher than the high-level potential of the sub-word line drive signal RAI0 by the threshold voltage of the transistor T01, and the high-level potential of the sub-word line drive signal RAI0 is transmitted to the sub-word line SWL0. At this time, RAIB which is a complementary signal of the sub-word line drive signal RAI0 is used.
0 is driven from the high level to the low level, and the transistor T02 is off.

At this time, all sub-word lines SWL, for example, SWL1 connected to the unselected main word line MWL and connected to the unselected sub-word line drive signal RAI.
nm maintains the low level through the same route as when the cell array is in the inactive state. Further, the sub word line drive signal R which is connected to the selected main word line MWL and is not selected
All the sub-word lines SWL connected to the AI, for example, SWL10 nm, are connected to the same path as when the cell array is in the inactive state, and to the unselected sub-word line drive signal RAI1 via the drive transistor T11. To keep the low level. On the other hand, all the sub-word lines SWL, for example, SWL0nm connected to the unselected main word line MWL and connected to the selected sub-word line drive signal RAI are connected to the unselected main word line MWLn by the transistor T03 and set to the low level. keep. In any case, the selected sub-word line S
Except for WL00m, it keeps the low level potential and becomes unselected.

The activated sub-word line SWL00m stores the contents of the connected memory cells M0nm to Minm to the bit lines BLT0nm to BLTinm to which they are connected.
And the complementary bit line BL initially at the same potential
T0nm to BLTinm and BLN0nm to BLNi
A potential difference is created in nm. SA0nm to SAinm and SA0n + 1m to SAin + 1m are sense amplifiers, respectively, and complementary bit lines BLT0nm to BLTin.
m, BLT0n + 1m to BLTin + 1m and BLN
0 nm to BLNinm, BLN0n + 1m to BLNin
+ 1m difference signal is amplified. Next, the complementary bit line B
LT0nm to BLT1nm, BLT0n + 1m to BLT
1n + 1m and BLN0nm to BLN1nm, BLN
0n + 1m to BLN1n + 1m correspond to the column selection circuit YDEC.
0m, the local input / output lines LIOT0nm to LIOT1nm are respectively selected by the column selection line YSW0m,
LIOT0n + 1m to LIOT1n + 1m and LIO
N0nm to LION1nm, LION0n + 1m to LI
ON1 + 1 nm, and outputs an amplified signal. Each LIOT and LION from which the signal was output is IOSW
n and IOSWn + 1, global data input / output lines GI arranged on SWD region in parallel with sub-word line drive signal RAI and sub-word line deactivation signal RAIB
OT0m to GION3m, GION0m to GION3m
And transmits a signal to the data amplifier DA. The data amplifier DA has GION and G connected to each.
The difference potential of the IOT is amplified, and data is output to the outside of the chip via an output control circuit (not shown).

To deactivate the activated sub-word line SWL0, first, the sub-word line drive signal RAI
0 is changed from a high level to a low level. The charge of the sub-word line SWL0 becomes R through the drive transistor T01.
It is pulled out to AI0 and becomes low level. When the potential of SWL0 is insufficiently lowered, the level of MWL is set to low level, and the transistor T01 is completely turned off. At substantially the same time when RAI0 goes low, the complementary signal RAI0
Since B0 is at a high level, the transistor T0
SWL0 holds the low level through 2.

As described above, sub word line SWL
The drive transistors T01 to T03 play a major role in the sub-word line drive circuit SWD both when activating and deactivating the word line. The other transistors have only a function of compensating for potential fluctuations caused by a minute leak current from the sub-word line SWL in the inactive state, and therefore have a significantly smaller size than the drive transistors.

Although the description has been given of the sub-word line drive circuit SWD in which four sub-word lines SWL are connected to one main word line MWL, even if the number of sub-word lines SWL is changed, there is a problem. There is no. In that case, the sub-word line drive signal RAI and the sub-word line deactivation signal RAIB according to the number of sub-word lines SWL
Will also change.

[0015]

The word line driving circuit SWD as described in the prior art requires a one-to-one complementary signal RAIB for each sub-word line driving signal RAI. The area of the word line drive circuit SWD region is limited, and other wiring, for example, the wide area data input / output line GIO
Since it is necessary to arrange T, GION, and the like, there is a possibility that all of these wirings cannot be arranged after securing a necessary wiring width.

An object of the present invention is to provide a semiconductor memory device in which the number of word line drive signals is smaller than that of a conventional one, and therefore has a small area.

[0017]

A semiconductor memory device according to the present invention comprises a plurality of main word lines, a plurality of sub-word line drive signal lines orthogonal to the plurality of main word lines, and a plurality of main word lines. A first sub-word line disposed in parallel with the first sub-word line, the first sub-word line selectively controlling the sub-word line by the main word line and the sub-word line driving signal line; And a sub-word line deactivating signal line arranged orthogonal to the plurality of main word lines, and a de-energizing potential holding all of the plurality of sub-word lines orthogonal to the sub-word line deactivating signal line. And a third driving means for holding the sub-word lines other than the sub-word lines driven by the first driving means by the sub-word line driving signal line at an inactive potential.
And driving means.

According to the present invention, the corresponding sub-word line drive circuit SW
When all of the sub-word line drive signals RAI connected to D are inactive, the N of the sub-word line drive signal RAI connected to the corresponding sub-word line drive circuit SWD is set to N.
Each sub-word line is kept in an inactive state by OR logic. When any of the sub-word line drive signals RAI connected to the corresponding sub-word line drive circuit SWD is in an activated state, the activated sub-word line drive signal RAI is activated.
I, the sub-word line drive signal R deactivated
The sub-word line connected to AI is kept in an inactive state.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2A is a circuit diagram showing the contents of SWD in FIG. 1, and FIG. 2B is a diagram showing the contents of RAID in FIG. FIG. 3 is a circuit diagram, and FIG. 3 is an operation waveform diagram showing the first embodiment of the present invention. Each circuit arrangement is shown in FIG. 6 as in the conventional example, and the functions of signals and the like, which are not specified, are the same as those in the conventional example. Hereinafter, description will be given based on the drawings.

FIG. 1 shows a circuit diagram of a portion indicated by A in FIG. When the cell array shifts from the inactive state to the active state, one of the row decoders arranged in row select circuit area XDEC is selected by an external address not explicitly shown in the figure, and main word line MWL0 is selected. Activate. Next, one of the sub-word line drive signals RAI0 to RAI3 included in every other row of sub-word line drive circuits SWD is activated by an external address not explicitly shown in the figure. At this time, the sub-word drive signal RAI connected to every other sub-word line drive circuit SWD column
None of 0 to 3 are activated. SWD0 to SWD
n is a sub-word line driving circuit, which is a main word line MWL0 selected and driven by the row decoder XDEC.
And the sub-word line SWL00m selected by both the sub-word line power supply signal RAI0m and the sub-word line power supply signal RAI0m.

In FIG. 1, sub word line drive circuit SWD0
Alternatively, the contents of SWDn are shown in FIG. They are,
Similar to the conventional example, the sub-word line driving circuit is configured only with NMOS transistors, and does not include a PMOS transistor. Therefore, a PN element isolation region is not required on a semiconductor substrate, so that it can be realized with a small area. is there. Although the number of transistors is increased as compared with the conventional example, as will be described later, except for the drive transistors T01 to T31, since the transistors are extremely small transistors for compensating for a small leak current, the overall area increase is not large.

FIG. 2 shows the contents of the RAID in FIG.
It is shown in (B). This circuit includes a sub word line drive signal RAI.
0 to RAI3, 3 bits X0 of the external address
The sub-word line drive signal RAI corresponding to X2 is activated while the sub-word line drive timing signal RAE is at a high level. Here, the circuit for activating the sub-word line drive signal RAI signal when X0 is at the low level, that is, when the row address is an even number, has been described. However, for the adjacent column of sub-word line drive circuits SWD, X0 is at the high level. At this time, a circuit for activating sub word line drive signal RAI is connected. Signal RAIB is equal to RAI generated by NOR circuit NOR.
0 and RAI3 are NOR logic signals.
When all the outputs RAI0 to RAI3 of 1 to AD4 are at a low level, the output goes high.

Next, the sub-word line driving circuit S of this embodiment
The WD circuit operation will be described. FIG. 3 is an operation waveform diagram of the sub-word line drive circuit SWD. In the initial state, the potentials of all the main word lines MWL0 to MWL3 in the sub-word line drive circuit SWD are at the low level. Therefore, the potentials of nodes N0 to N3 connected to main word line MWL via transistors T00 to T30 whose gates are fixed to a high level also become low level, and drive transistors T01 to T03
Are all in the off state. Further, since the sub-word line drive signals RAI0 to RAI3 are also at the low level in the initial state, the transistors T03 to T33, T14 to
T34, T05, T25 to T35, T06 to T16, T
36, T07 to T27 are all in the off state. on the other hand,
The potential of RAIB, which is the NOR logic signal of RAI0 to RAI3, is at the high level, and the sub word line SWL0
3 are held at low level by the transistors T02 to T32.

When selecting and activating the sub-word line SWL0, first, the potential of the main word line MWL is set to a high level. As a result, the potentials of the nodes N0 to N3 are respectively higher than the high level potential of the main word line MWL by the transistor T0.
The potential becomes lower by the threshold voltage of 0 to T30. next,
While the potentials of the sub-word line drive signals RAI1 to RAI1 are fixed at a low level, the potential is driven to a high level by the sub-word line drive signal RAI0. Since the transistor T01 has a capacitance between the sub-word line drive signal RAI0 as the source electrode and the gate electrode N0, the potential of the sub-word line drive signal RAI0 changes due to the capacitive coupling with the change in the potential of the sub-word line drive signal RAI0. At this time, no current flows from node N0 to main word line MWL unless the potential difference between N0 and main word line MWL after the change does not exceed the threshold voltage of transistor T00. As a result, the potential of node N0 is higher than the high-level potential of sub-word line drive signal RAI0 by the threshold voltage of transistor T01 or more, and the high-level potential of sub-word line drive signal RAI0 is transmitted to sub-word line SWL0. At this time, RA which is a NOR logic signal of the sub-word line drive signals RAI0 to RAI3 is used.
IB is driven from high level to low level, and the transistors T02 to T32 are turned off. On the other hand, the transistors T14, T24, T3 are added to the sub-word line drive signal RAI0.
4 are turned on.

At this time, all sub word lines SWL, for example, SWL connected to the unselected main word line MWL and connected to the unselected sub word line drive signal RAI.
1 nm is kept at a low level by the transistor T14 which is turned on when the sub-word line drive signal RAI0 goes to a high level. Also, all the sub-word lines SWL, which are connected to the selected main word line MWL and are connected to the unselected sub-word line drive signal RAI,
For example, SWL10m maintains a low level by being connected to an unselected sub-word line drive signal RAI1 via a drive transistor T11. On the other hand, all the sub-word lines SWL, for example, SWL0nm connected to the unselected main word line MWL and connected to the selected sub-word line drive signal RAI are connected to the unselected main word line MWLn by the transistor T03 and set to the low level. keep. In any case, the selected sub-word line S
Except for WL00m, it keeps the low level potential and becomes unselected.

The activated sub-word line SWL00m stores the contents of the connected memory cells M0nm to Minm to the bit lines BLT0nm to BLTRin to which they are connected.
m, and data is output to the outside of the chip via an output control circuit, not shown in the figure, as in the conventional example.

To deactivate the activated sub-word line SWL0, first, the sub-word line drive signal RAI
0 is changed from a high level to a low level. The electric charge of the sub-word drive signal SWL0 is pulled out by the sub-word line drive signal RAI0 through the drive transistor T01, and becomes low level. When the potential of the sub-word line drive signal SWL0 is sufficiently lowered, the main word line MWL is set to the low level, and the transistor T01 is completely turned off. Substantially simultaneously with the sub-word line drive signal RAI0 attaining a low level, the N of the sub-word line drive signals RAI0 to RAI3 becomes N.
Since the OR logic signal RAIB becomes high level,
Sub-word line SWL0 holds low level through transistor T02. At the same time, the sub-word lines SWL1-SWL
WL3 is also held at a low level through the transistors T12 to T32.

In this embodiment, the sub word line drive signal RAI arranged on the sub word line drive circuit SWD is used.
Irrespective of the number of sub-word line driving signals RAIB, only one sub-word line driving signal RAIB is required, so that the area required for arrangement can be reduced.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. FIG. 5A is a circuit diagram showing the RAID in FIG. 4, and FIG. 5B is a circuit diagram showing the RAIBD in FIG. Unless otherwise specified, signals and the like are the same as in the conventional example or the first embodiment of the present invention.

In the first embodiment, the sub-word line deactivating signal RAIB is the sub-word line driving signal RAI input to the sub-word line driving circuit SWD to which it is connected.
However, in the present embodiment, the sub-word line non-selection circuit RAIBD generates the sub-word line drive timing signal RAE and the sub-word lines SWL0nm and SWL of the row address signal input from the outside.
A bit that distinguishes 0 nm + 1 is generated directly by X0 in this case.

The resulting sub-word line deactivation signal RAIB is similar to that of the first embodiment, and the other operations are the same as those of the first embodiment.

[0033]

As described above, according to the present invention, the number of word line drive signals can be reduced, and a semiconductor memory device having a small area can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention.

2 is a circuit diagram showing the SWD in FIGS. 1 and 4 (FIG. 2);
(A)) and a circuit diagram showing the RAID in FIG. 1 (FIG. 2)
(B)).

FIG. 3 is an operation waveform diagram showing the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing the RAID in FIG. 4 (FIG. 5A)
FIG. 5 is a circuit diagram showing RAIBD in FIG. 4 (FIG. 5B).

FIG. 6 is a circuit layout diagram showing a conventional example and first and second embodiments of the present invention.

FIG. 7 is a circuit diagram showing a conventional example.

FIG. 8 is an operation waveform diagram showing the SWD in FIG. 7 (FIG. 8);
(A)) and an operation waveform diagram showing the RAID in FIG. 7 (FIG. 8).
(B)).

FIG. 9 is an operation waveform diagram showing a conventional example.

[Explanation of symbols]

XDEC row select circuit area MWL0 to MWLm main word line YDEC column select circuit area YDEC0m to YDECi-1m column select circuit YSW0m to YSWi-1m column select line SA sense amplifier area SA00m to SAin + 1m sense amplifier SWD00m to SWDnm sub word line drive circuit SWD drive Circuit area SWL00 to SWL3 nm Subword line RAI0m to RAI3m Subword line drive signal RAIB0m to RAIB3, RAIBm Subword line deactivation signal RAID subword drive circuit RAIBD Subword line nonselection circuit X0 to X2 Part of row address signal RAE Subword line drive timing signal M0nm to Minm memory cells BLT0nm to BLTin + 1m, BLN0nm to BL
Nin + 1m bit line LIOT00m to LIOT1n + 1m, LION00m
~ LION1n + 1m local data input / output lines GIOT0m ~ GIO3m, GION0m ~ GION3
m Wide area data input / output line DA Differential amplifier circuit AD1 to AD4 AND circuit NOR NOR circuit

Claims (4)

(57) [Claims] A plurality of main word lines; a plurality of sub word line drive signal lines arranged orthogonal to the plurality of main word lines; and a plurality of memory cells arranged in parallel to the main word line. A sub-word line for controlling data input / output of the first word line; first driving means for selectively driving the sub-word line by the main word line and the sub-word line driving signal line; An arranged sub-word line inactivating signal line, a second driving unit that holds an inactivating potential of all of the plurality of sub-word lines orthogonal to the sub-word line inactivating signal line, and the sub-word line driving signal line And a third driving unit for holding the sub-word lines other than the sub-word lines driven by the first driving unit at an inactive potential. 2. The semiconductor memory device according to claim 1, wherein said sub-word line deactivating signal is generated by an inverted signal of a logical sum of said sub-word line drive signal lines. 3. The sub-word line deactivating signal is generated by a part of bits of a row address signal for selecting the sub-word line drive signal line in a row address signal. Semiconductor storage device. 4. The semiconductor memory according to claim 1, wherein said first driving means, said second driving means, and said third driving means are constituted only by transistors having the same polarity. apparatus.