JP3353786B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a built-in memory circuit for realizing a large-scale and high-speed parallel distributed processing. In particular, the present invention relates to an information processing device that performs neural network information processing.

[0002]

2. Description of the Related Art Parallel and distributed information processing using a neural network called neurocomputing
(Hereinafter referred to as "neural network information processing"), Complex Systems 1 (1987), p.
8 pages (Sejnowski, TJ, andRosenberg, CR 198
7. Parallel networks that learn to pronounce Engl
As described in ish text. Complex Systems 1, PP. 145-168) or neural network information processing (Sangyo Tosho, written by Hideki Aso), it has attracted attention in fields such as speech and image processing. In neural network information processing, a large number of arithmetic elements called neurons connected in a network form exchange information through transmission lines called connections to perform advanced information processing. In each neuron, a simple operation such as a product or a sum is performed on information (a neuron output value) sent from another neuron. The operation in each neuron and also the operation of different neurons can be performed in parallel, and in principle, it has the feature that information processing can be performed at high speed. Nature 323-9, (1986a) pages 533 to 53
5 pages (Rumelhart, DE, Hinton, GE, and William
s, RJ 1986a. Learningrepresentations by bac
k-propagation errors. Nature 323-9, pp. 533
-536), or neural network information processing
(Sangyo Tosho, written by Hideki Aso) As described in Chapter 2, etc., algorithms (learning) for setting weights of connections connecting neurons to perform desired information processing have been proposed. Various information processing can be performed according to the purpose.

[0003]

First, the principle of operation of a neural network will be described for two typical types of networks, a hierarchical network and a Hopfield network. FIG. 2A shows the structure of a hierarchical network, and FIG. 4A shows the structure of a Hopfield network. These are both composed of connections between neurons and neurons. Here, the term neuron is used, but in some cases, it is also called a node or an operation element. The direction of the connection arrow indicates the direction in which the neuron output value is transmitted. Figure 2 shows a hierarchical network.
As shown in (a), neurons are arranged in a plurality of layers, and the neuron output value is transmitted only in the direction from the input layer to the output layer. On the other hand, a hop-field network is a network in which the neuron output value is fed back to the same neuron and the neuron output value is transmitted in both directions between any two neurons, as shown in FIG. is there. Fig. 2 (b), Fig. 4 (b)
Shows the principle of the operation performed in the neuron. Since the operation principle is the same in both networks, FIG.
The hierarchical network will be described with reference to FIG.
FIG. 2B is an enlarged view of the j-th neuron in the (S + 1) -th layer. The output values V1S,..., V1S,.
Here, nS indicates the number of neurons in the S-th layer. , ViS,..., VnSS of the input neuron and the connection weight value TSj
1,..., TSj1,..., Product with TSjns V1STSj
, ViSTSj1, ..., VnSSTSjnS are calculated by the multiplier MT. Next, the sum of the product and the offset ΘjS + 1 is calculated by the adder ADD. The offset ΘjS + 1 may be omitted in some cases. Further, the result is input to the nonlinear function circuit D to obtain an output value VjS + 1 of the neuron. The nonlinear function circuit D has characteristics as shown in FIG. 3A or FIG. 3B, and outputs an output g (x) with respect to an input x.
FIG. 3A is an example of a nonlinear function that outputs a binary output g1 or g2 depending on whether the input x exceeds a certain threshold value xth, and FIG. 3B shows a non-linear function using a sigmoid function. Give continuous output in the example. In the nonlinear function circuit D,
Other characteristics may be provided as needed. In some cases, a linear characteristic may be provided. The principle of the above calculation is the same in a Hopfield network as shown in FIG. However, in the Hopfield network, the output values of all neurons, not just the neurons one layer before, are input to one neuron.

As can be seen from FIGS. 2 (a) and 2 (b), in the hierarchical network, first, the output value of the neuron of the input layer is given, and then the output value of the new pixel in the next layer is updated. Further, the output value of the neuron in the next layer is updated, and one process ends. On the other hand, in a Hopfield type network as shown in FIG. 4A, since there is no layer, each neuron can update an output value at an appropriate timing. In this Hopfield-type network, all neuron output values are given appropriately, and updating of the neuron output values is continued until the neuron output values reach an equilibrium state. The one that updates the output values of all neurons simultaneously is called a synchronous Hopfield network, and the one that each neuron updates the output values at arbitrary timing is called an asynchronous Hopfield network.

[0005] A method using software and a method using hardware have been used to perform the operation of the neural network as described above. In the method using software, neuron operations are performed by a program written in a computer language, so that the number of neurons and the structure of the network can be easily changed according to the purpose. However, there is a drawback that the information processing time increases rapidly when the number of neurons is increased because the calculation is performed sequentially. For example, in a Hopfield network using n neurons, n products must be calculated to update the output value of one neuron. Therefore, in order to update the output values of all neurons at least once, it is necessary to calculate n2 products. That is, the amount of calculation increases in the order of n2 as the number n of neurons increases. As a result, if the multiplication is performed sequentially, the information processing time also increases on the order of n2.

In the method using hardware, the time required for the operation can be shortened by making the neuron that performs the operation such as multiplication into hardware. Further, attempts have been made to further increase the speed by performing operations in parallel by using a large number of hardware neurons. However, when the number of neurons is increased, the number of wirings corresponding to signal lines between neurons increases in the order of n2.
Large networks have been difficult to achieve.

As an example of a method for solving the wiring problem, see Nikkei Micro Devices, March 1989, p. 123-12
The principle of what is described in FIG. 9 is shown in FIG. FIG. 5 shows an example in which an analog neuroprocessor ANP and an SRAM are used to form a three-layer hierarchical network using three neurons in each layer. The ANP is such that the multiplier MT and the adder ADD in FIG. 2B are each integrated, and the nonlinear function circuit D and the like are integrated on one chip. The SRAM, which is another chip, stores connection weight values belonging to each neuron. Neurons of different layers are connected by using one signal line called an analog common bus. Since the neuron output value of the input layer is input from the outside, ANP and SR corresponding to the neuron of the input layer
AM is omitted.

The operation is as follows. First, a connection weight value for each ANP necessary for desired information processing is read from the outside into each SRAM. Next, an input analog signal corresponding to the output value of one neuron in the input layer is input from the input signal line. The input signal goes directly into parallel to the ANP corresponding to the neurons in the hidden layer. The weight data is read from the SRAM to each ANP in synchronization with the input signal. Next, the product of the two signals is calculated and the result is stored in each ANP. Subsequently, an input analog signal corresponding to the output value of another neuron in the input layer is input, a product is similarly calculated, and the result is added to the value stored in each ANP in the intermediate layer. After performing the same operation on the input analog signal corresponding to the output value of the last neuron in the input layer,
The neuron output values V12, V22 and V32 of the intermediate layer are represented by A
The signals are sequentially output to the intermediate layer analog common bus by the nonlinear function circuit in the NP, and the same operation as described above is continued. Finally, neuron output values V13, V23, V33 of the output layer are sequentially output to the output layer analog common bus by the nonlinear function circuit in the ANP of the output layer.

As described above, according to the conventional example shown in FIG. 5, the wiring problem can be avoided by driving the common bus in a time-division manner. In addition, since the multiplication by the number of neurons in one layer can be performed in parallel, the speed of information processing can be significantly increased in comparison with the method using software, in combination with the increase in operation speed by hardware. .

However, it is difficult to realize a large-scale network at a high density because the ANP and the SRAM are separate chips. The above Nikkei microdevice 1
March 989 p. 129 as described in 129
Even if it is possible to integrate 32 neurons on a mm-square chip, adders, multipliers,
Since it is necessary to prepare nonlinear function circuits one by one, it is difficult to integrate hundreds or thousands of neurons on one chip.

Further, the above conventional example has the following problem when applied to an actual problem. As an application example of a hierarchical network, an example of inputting English characters to a three-layer network and outputting its pronunciation and accent is described in Complex Systems 1 (1987), pages 145 to 168 (Se
jnowski, TJ, and Rosenberg, CR 1987.Para
llel networks that learn to pronounce English tex
t. Complex Systems1, PP.145-168). A code of seven alphabetic characters is set as the neuron output value of the first layer, and a code corresponding to the pronunciation and accent of the central character of the seven characters is output as the output value of 26 neurons of the third layer. It is. In such an example, depending on the input, the output value of the neuron in the output layer may not match the predefined pronunciation and accent codes, resulting in an ambiguous value. Therefore, it is necessary to compare the obtained output with all the pronunciation and accent codes to find the closest code and make it the correct answer. Such a comparison between the output value and the expected value of the output (pronunciation and accent codes in the above example) is also necessary for pattern recognition using a neural network. This point is not taken into consideration in the above-mentioned conventional example, which is inconvenient when applied to an actual problem.

Further, in the above conventional example, a connection weight value required for desired information processing is obtained by an external computer, and the result is written in the SRAM of FIG. Therefore, it is difficult to perform learning at high speed because all learning is performed by software.

An object of the present invention is to provide an apparatus for calculating a neuron output value at high speed using a small number of circuits in a network including many neurons. Another object of the present invention is to provide the device with a function of comparing a neuron output value and an expected value at high speed. Still another object of the present invention is to provide the device with a function of processing at least a part of an operation necessary for learning. Other objects of the present invention will become apparent from the following description and drawings.

[0014]

According to the present invention, there is provided a memory circuit for storing a neuron output value, a connection weight value, an expected output value, data necessary for learning, and the like. An input / output circuit for writing information or reading information from the memory circuit, an operation for obtaining a neuron output value such as a product-sum and non-linear conversion using the information stored in the memory circuit, and an output value. An operation circuit for performing operations required for comparison and learning of the expected value, a memory circuit, an input / output circuit, and a control circuit for controlling operations of the operation circuit are provided. The arithmetic circuit includes at least one of an adder, a multiplier, a non-linear function circuit, a comparator, and the like. I was able to do it. Moreover, these circuits are shared by a plurality of neurons, and are operated in a time-sharing manner to obtain a plurality of neuron output values. Further, the comparator compares the calculated neuron output value and the expected output value in parallel.

An adder included in the arithmetic circuit as described above;
Since the multiplier and the non-linear function circuit are shared by a plurality of neurons, a device for calculating a neuron output value in a neural network using a large number of neurons can be realized with a small number of circuits. Further, since at least a part of the neuron operation such as the product-sum operation is performed in parallel by the arithmetic circuit, information processing can be performed at high speed. Also,
With the above comparator, the obtained output value and the expected value of the output can be compared in parallel, so that the distance between the obtained output value and the expected value (the degree of coincidence between the obtained output value and the expected value) , A so-called Hamming distance) can be obtained at high speed. Further, since at least a part of the operation necessary for the learning is performed by the hardware of the device, the speed of the learning can be increased.

[0016]

FIG. 1 shows an embodiment in which an information processing apparatus according to the present invention is integrated on a semiconductor chip. A memory circuit that stores information, an input / output circuit that performs at least one of an operation of writing information to and reading information from the memory circuit, an operation for obtaining a neuron output value, an output value and an expected value, (The degree of coincidence between the obtained output value and the expected value, that is, calculation of the so-called Hamming distance), or an arithmetic circuit that performs an operation necessary for learning using information stored in the memory circuit, the memory circuit described above. A control circuit for controlling operations of an input / output circuit and an arithmetic circuit is integrated on a semiconductor chip. The bus connecting each block is not limited to one wire, but is composed of a plurality of necessary wires. The memory circuit can store a connection weight value, a neuron output value, an expected output value, data necessary for learning, etc. necessary for neural network information processing. According to the present embodiment, neural network information processing such as calculation of a neuron output value, comparison of an output value with an expected value, or calculation required for learning can be performed as follows. First, a method of calculating a neuron output value will be described. First, the control circuit
A connection weight value and a neuron output value or an offset necessary for performing an operation for neural network information processing are read out in parallel from the memory circuit to the arithmetic circuit through the bus 1. Next, operations such as multiply-accumulation and non-linear conversion necessary for obtaining a neuron output value are performed in parallel by an arithmetic circuit, and the obtained result is written to a memory circuit through an input / output circuit. The above operation is repeated the required number of times to obtain a neuron output value. In the arithmetic circuit, one operation
One or more neuron output values may be determined simultaneously, or a part of the calculation for determining the neuron output values may be performed. In this way, it is possible to perform information processing by various neural networks such as a hierarchical network or a synchronous or asynchronous Hopfield network. In a synchronous Hopfield network, the output values of all neurons are updated synchronously, so the output values of all previous neurons must be stored until the output values of all neurons are updated. is there. In this case, the output values of all previous neurons may be stored in the memory circuit and used for updating the output values of the neurons. According to the present embodiment, the necessary number of multipliers, adders, and non-linear function circuits required to calculate the neuron output value may be provided in the arithmetic circuit and used repeatedly, so that these circuits are provided for each neuron. The number of circuits can be greatly reduced as compared with the case of preparing. For example, in order to realize a three-layer hierarchical network in which each layer is composed of 100 neurons, in the conventional example shown in FIG.
In this embodiment, at least one multiplier, one adder, and one non-linear function circuit may be prepared. 1 to increase speed
Even if the multiplication necessary to update one neuron output value is performed in parallel, 100 multipliers, one adder and one nonlinear function circuit may be prepared. Therefore, according to this embodiment, the number of circuits can be reduced as compared with the conventional example. Note that the above difference becomes larger as the network becomes larger. The situation is the same for other networks such as the Hopfield type.

The information processing speed for obtaining the neuron output value largely depends on the amount of operations performed in parallel in addition to the operation speed such as multiplication. As described above, for example, a Hopfield network using n neurons has to calculate n2 products to update the output values of all neurons. Therefore, if the multiplication is performed sequentially, it takes n2 times as long as at least one multiplication to update the output values of all the neurons. As a result, the time required for multiplication increases rapidly with the order of the square of the number of neurons as the number of neurons increases. The situation is the same in a hierarchical network. Therefore, it is desirable to calculate many multiplications in parallel. In the following, a description will be given of an embodiment of an arithmetic method for increasing the information processing speed by parallelizing multiplication in order to obtain a neuron output value in the embodiment of FIG.

FIG. 6 illustrates a hierarchical network (a) and a Hopfield network (b) for one method of performing operations in parallel. In the present embodiment, as shown in the figure, a product necessary for obtaining one neuron output value is calculated in parallel. That is, the neuron output value and the connection weight value input to one neuron are read from the memory circuit in parallel, and their product is calculated in parallel. For this reason, the time required for multiplication increases in the order of the first power of the number of neurons as the number of neurons increases. Therefore, the information processing time can be greatly reduced as compared with the case where the multiplication is performed sequentially. In FIG. 6, only the multiplication necessary for updating the output value of one neuron is performed in parallel. However, the embodiment of FIG. 1 is not limited to this, and the arithmetic circuit May be added to update the output values of a plurality of neurons in parallel. In that case, information processing can be performed at higher speed. In addition, as shown in FIG. 7, the operation can be performed in parallel by another method. FIG. 7 shows an embodiment in which multiplication is performed in parallel for a plurality of neurons to which the output value of one neuron is input in the hierarchical network (a) and the Hopfield network (b). In this method, the neuron output value and the connection weight value are read from the memory circuit in parallel, and the operation necessary for updating the neuron output value is performed little by little on a plurality of neurons. For this reason, an asynchronous Hopfield network cannot be realized, but the time required for multiplication increases in the order of the first number of neurons as the number of neurons increases as in the method of FIG. The information processing time can be greatly reduced as compared with the case where the above is performed. In the conventional example shown in FIG. 5, calculations are performed in parallel by this method. However, as described below, the configuration shown in FIG. 1 can be realized with a smaller number of circuits than the conventional example. In the method shown in FIG. 7, one neuron is connected to each neuron as shown by hatching in the figure.
Only one multiplier operates in parallel. Therefore, in the embodiment of FIG. 1, it is sufficient to provide multipliers in the arithmetic circuit as many as the number of neurons that perform the operation at one time, and the number of multipliers is smaller than that in the conventional example in which all multipliers are provided for each neuron. The circuit can implement this scheme. For example, in a hierarchical network having three layers and three neurons in each layer, when the embodiment of FIG. 1 is used as compared with the conventional example in which six multipliers, adders, and six nonlinear function circuits are provided, for example, a multiplier,
Similar parallelization can be realized only by using three adders and three non-linear function circuits.

Thus, according to the embodiment shown in FIG.
By using the adder, multiplier, and nonlinear function circuit included in the arithmetic circuit for a plurality of neurons, it is possible to realize a device that performs information processing similar to a neural network using a large number of neurons with the minimum necessary circuit. Can be. Further, by performing calculations such as sum of products in parallel by the above calculation circuit, information processing can be performed at high speed. Note that, when the operation is parallelized, it is necessary to increase the number of bus lines between the memory circuit and the operation circuit and send a large amount of data to the operation circuit at a time. However, in FIG. Since the arithmetic units are arranged, the number of bus lines can be easily increased.

The method of calculating the neuron output value has been described above. However, according to the embodiment of FIG. 1, the neuron output value can be compared with its expected value. For this purpose, the expected value may be stored in the memory circuit in advance, and the calculation of the distance from the output value obtained by the above method may be performed by the arithmetic circuit. This calculation is for calculating the degree of coincidence between the expected value and the calculated value. At this time, by increasing the number of buses 1, it is easy to simultaneously read the expected value and the output value composed of a large number of bits into the arithmetic circuit and process them in parallel. As described above, according to the embodiment of FIG. 1, it is possible to perform information processing such as pattern recognition at a higher speed as compared with the case where the comparison is performed bit by bit using an external computer.

Further, according to the embodiment shown in FIG. 1, the arithmetic operation required for the learning is performed by the arithmetic circuit, so that the learning can be performed at a higher speed than in the case where the operation is performed by software. Specific examples will be described later.

Neural network information processing has the advantage that various information processing can be performed by changing the connection weight value. According to the embodiment shown in FIG. 1, this advantage can be easily utilized by rewriting the connection weight value stored in the memory circuit. Further, by making the capacity of the memory circuit larger than the amount required for calculating the neuron output value, several types of connection weight values required for different information processing can be stored in advance. In this case, there is a merit that different types of information processing can be continuously performed without losing time for rewriting the connection weight value. In addition, when performing information processing on a large number of input data continuously, necessary input data and obtained data can be stored in a part of the memory circuit in advance. If you do this,
Read data into the memory circuit for each input data,
Compared to the case where the operation of performing the calculation and outputting the result to the outside of the apparatus is repeated, the number of times of switching between the operation modes of reading, calculation and output is small, and the processing time can be reduced.

Next, a more specific embodiment based on the embodiment of FIG. 1 will be described. For simplicity, first, a case will be described in which the arithmetic circuit has a function of calculating a neuron output value, and finally, a method of having a function of comparison or learning will be described.

FIG. 8 shows an embodiment in which a memory circuit having a grid-like memory cell array is used in the embodiment of FIG. In FIG. 8, A is a memory cell array having a plurality of data lines, a plurality of word lines arranged to intersect the data lines, and memory cells arranged at desired intersections thereof. , The signals of the plurality of different memory cells can be read out on a plurality of data lines. Reference numeral 12 denotes an arithmetic circuit. Reference numerals 10, 11, 13, 14, 15, and 16 correspond to the control circuit of FIG. Reference numerals 10 and 15 denote address buffers for X-system addresses and Y-system addresses, respectively.
Reference numerals 1 and 14 denote a decoder and a driver for an X-system address and a Y-system address, respectively. Reference numeral 13 denotes an array control circuit for controlling the memory cell array, and reference numeral 16 denotes a clock generation circuit, which generates a clock for controlling the operation of the memory based on an externally input signal. OUT and W
R is a read circuit and a write circuit, respectively. Chip select / CS is a selection signal for this chip. The write control signal / WE is a signal for switching between a write operation and a read operation, and the write operation is performed at a low level and the read operation is performed at a high level. / NE is an arithmetic circuit control signal. The arithmetic circuit is activated at a low level, and is stopped at a high level to operate as a normal memory. Hereinafter, the state where / NE is at a high level is referred to as a memory mode, and the state when / NE is at a low level is referred to as a calculation mode. In memory mode,
A desired memory cell can be selected based on the X-system address and the Y-system address, and write data DI can be written to the cell, or information can be read from the cell and output as read data DO. In the operation mode, information stored in the memory cell can be read out to the operation circuit 12, and the result of the operation of the operation circuit 12 or data corresponding to the operation result can be written to the memory cell through the input circuit.
According to this embodiment, by selecting one of the word lines, the information of all the memory cells on that word line is output to the data lines. Therefore, a large amount of information can be easily taken into the arithmetic circuit 12, and many operations can be performed in parallel. To calculate the neuron output value according to the present embodiment, first, the arithmetic circuit is stopped in the memory mode, and the necessary connection weight value, neuron output value, offset, and the like are written in the memory circuit. Next, the arithmetic circuit is started in the arithmetic mode, and necessary information is read out to the arithmetic circuit by selecting one word line. Next, the result is written to the memory circuit. If you continue reading the information necessary for the operation and writing the result as many times as you need,
Neural network information processing can be easily performed at high speed. As described above, according to the embodiment shown in FIG. 8, a large amount of information can be read into the arithmetic circuit at one time. Are suitable. As described above, according to this embodiment, neural network information processing can be performed at a high speed because calculations are performed in parallel. Further, by repeatedly using the arithmetic circuit 12, the calculation circuit of the output value can be shared by a plurality of neurons, so that high integration can be easily achieved.

In the case where arithmetic operations are performed in parallel using information stored in memory cells on a plurality of word lines, a register for primary storage is provided in an arithmetic circuit, and the word lines are obtained by raising the word lines. The information can be stored in the register once, another word line can be started up, and the operation can be performed together with the information read as a result.

Further, two memory circuits A and B can be provided as in the embodiment shown in FIG. In FIG. 9, 13A and 13B are array control circuits for controlling the memory cell arrays A and B, respectively. Other circuits, such as a decoder, are not shown in the figure. According to the configuration of FIG. 9, by selecting one word line in each of the memory cell arrays A and B, information of the memory cells on both word lines can be read into the arithmetic circuit. If the configuration of FIG. 9 is used, the memory cell array A can store the neuron output value and the memory cell array B can store the connection weight value.
Controls such as writing can be simplified. In the embodiment shown in FIGS. 8 and 9, a plurality of write data DI and a plurality of read data DO can be handled in parallel, or the read circuits OUT and the write circuits WR are separately used in the arrays A and B.
May be provided.

In the embodiments shown in FIGS. 8 and 9, selection of a word line or a specific memory cell can be performed in the same manner as in a normal memory by an address. Therefore, by changing the address selection order, it is possible to flexibly cope with various types of networks or various parallel operation methods.

In the embodiments shown in FIGS. 8 and 9, a highly integrated semiconductor memory such as a DRAM or an SRAM can be used as a memory circuit. In this case, since a large amount of information can be stored in the memory circuit, a large-scale network can be integrated on one chip.

Next, a method for realizing a hierarchical network using the configuration of FIG. 9 will be described in detail. As a method of the parallel operation, the method of FIG. 6A is taken as an example. The number of layers is m and the number of neurons in each layer is n. For the sake of simplicity, the offset の of each neuron shown in FIG. 2B or FIG. 4B is omitted here. However, as is clear from FIG. 2 (b) or FIG. 4 (b), the offset の of each neuron is increased by one neuron output value inputted for each neuron, and the value is increased by the offset の of each neuron, By setting the corresponding connection weight value to 1 and adding the product to the sum of the products of the other neuron output values and the connection weight values, it can be handled in the same manner as the output values from other normal neurons.

FIG. 10 shows one embodiment of the correspondence between memory cells, connection weight values and neuron output values. D is a nonlinear function circuit, c1, c2,... Cn are adders, and m1, m2,. c1, c
2,... Cn together constitute a multi-input adder ADD in FIG. 2B. The memory cell array A stores a neuron output value, and the memory cell array B stores a connection weight value. In the figure, only memory cells for storing neuron output values and connection weights are shown, but memory cells for storing other data such as offset の of each neuron and data necessary for learning may be used as necessary. Of course, it may be provided. As shown in the figure, the neuron output value Vis is stored in the memory cell at the intersection of the word line s and the data line i in the memory cell array A. That is, neuron output values of the same layer are arranged on the same word line. In the memory cell array B, the word line (s, j)
Weight T is applied to the memory cell at the intersection of
sij is stored. FIGS. 11A and 11B show an embodiment of the input / output characteristics of the nonlinear function circuit D. FIG. FIG.
1 (a) is an embodiment having binary outputs of g1 and g2. x1 and x2 represent a lower limit value and an upper limit value of the input x, respectively. In FIG. 11A, when the input x exceeds xth, the output becomes g2, and when it is less than xth, the output becomes g1, which is suitable when a binary memory cell is used. FIG.
1 (b) is a quaternary embodiment having ga and gb outputs between g1 and g2. In the present embodiment, 4 memory cells are used.
This is a good example when using values. g1, ga, g
Although the intervals between b and g2 are equal in the drawing, it is needless to say that the intervals may be changed as necessary. When a memory cell that can store information of a continuous value, that is, a so-called analog value, is used as a nonlinear function circuit D in FIG.
A material having the characteristics as shown in FIG. FIG.
FIG. 2 shows an embodiment corresponding to the word line selection method and the write destination address for obtaining the neuron output value of the final layer from the neuron output value of the input layer in the embodiment of FIG. Hereinafter, the operation of FIG. 10 will be described with reference to FIG. First, the word line of s = 1 in the array A and the word line of (s, j) = (1, 1) in the array B are simultaneously activated. Then, the data lines i = 1, 2,..., N of the array A are connected to the neuron output values V11, V21,.
n1 is output. On the other hand, the data line i of array B = 1,
, N include connection weight values T111, T112,.
11n is output. These are multipliers m1, m2, ...,
mn to T111V11, T112V21, ...,
T11nVn1 and these are the adders c1, c2,.
cn. As a result (T111V11 + T11
2V21 +... + T11nVn1) is input to the nonlinear function circuit D. The output of the non-linear function is supplied to the write destination address (s,
i) = written into the memory cell corresponding to (2, 1). Thus, the value of the first neuron output value V21 of the second layer is calculated. Next, the s = 1 word line of the array A and the (s, j) = (1, 2) word line of the array B are simultaneously activated. Then, the data line i of array A =
, N are the neuron output values V1 of the input layer.
, Vn1, ..., Vn1 are output. On the other hand, the connection weight value T121,
, T12n are output. They are multipliers m
, Mn and T121V11, T1
, T12nVn1 and these are the adders c
, C2, ..., cn. As a result (T121
V11 + T122V21 +... + T12nVn1) are input to the nonlinear function circuit D. The output of the non-linear function circuit is written to the memory cell corresponding to the write destination address (s, i) = (2, 2) in the array A through a write circuit (not shown). Thus, the value of the second neuron output value V22 of the second layer is calculated. By continuing the above operation according to FIG. 12, all neuron output values can be obtained. According to the present embodiment, a single neuron output value can be obtained by performing a read operation and a write operation once in the operation mode, so that neural network information processing can be performed at high speed. Further, since the arithmetic circuit can be shared by all neurons, high integration is possible. FIG. 12 shows an example of memory cell allocation, and various modifications are possible without being limited to this. For example, a plurality of input data can be processed continuously as described above. In this case, a plurality of sets of neuron output values of the input layer are required. Therefore, neuron output values of the input layer corresponding to a plurality of input data may be written in advance on a plurality of word lines in different arrays A and used in order. With this configuration, it is not necessary to read the neuron output value of the input layer every time information processing is performed, so that high-speed information processing can be performed continuously.

Here, one memory cell is used to store the neuron output value and the connection weight value. Therefore,
When a binary memory cell is used, only a binary value can be obtained as a neuron output value and a connection weight value. As described above, by using a multi-valued memory cell, the value of the neuron output value and the value of the connection weight can be increased. It is possible. In such a case, a plurality of memory cells can be used to store neuron output values and connection weight values, as described below.

FIG. 13 shows an embodiment in which p memory cells are used to store one neuron output value and q memory cells are used to store one connection weight value.
Subscripts indicating neuron output values such as i, j, and s and connection weights in the figure correspond to the subscripts in the embodiment shown in FIG. In the embodiment of FIG. 13, one neuron output value is represented by p consecutive memory cells on one word line in the array A, and q continuous memory cells on one word line in the array B are represented by one memory cell. Represents one connection weight value. The calculation of the neuron output value is performed as follows. First, FIG.
In the same manner as the embodiment of FIG. 0, the word line of s = 1 in the array A and the word line of (s, j) = (1, 1) in the array B are simultaneously activated. Then, information representing neuron output values V11, V21,..., Vn1 of the input layer is output to the data line group i = 1, 2,. Are input to adders a1, a2,..., An. On the other hand, a data line group i = 1, 2,..., N composed of q data lines of array B has a connection weight value T111,
Information representing T112,..., T11n is output and input to the adders b1, b2,. The adders a1, a2,..., An, b1, b2,.
bn, neuron output values V11, V21,.
, T11n are combined and input to the multipliers m1, m2,..., Mn as shown in the figure, and T111V11, T112V21,.
n1 is obtained. These are input to the adders c1, c2,..., Cn, and as a result, (T111V11 + T112V21
+ ... + T11nVn1) is input to the nonlinear function circuit D. The output of the non-linear function circuit is passed through a write circuit WR (not shown), and the write destination address (s, i) in the array A is written.
= (2,1) is written to p memory cell groups. By continuing the same operation using the same address as in FIG. 12, the output values of all neurons can be obtained. According to the above embodiment, consecutive neuron output values are represented by p consecutive memory cells on one word line in array A, and continuous q memory cells on one word line in array B are represented. By expressing a single connection weight value by, a multi-valued neuron output value and a connection weight value can be expressed using a binary memory cell. Therefore, even when a multi-valued value is used as the neuron output value and the connection weight value, it can be realized by using a binary memory cell. Also, in the above embodiment, the number of times of address switching is the same as in the embodiment of FIG.
The information processing can be performed at high speed as in the embodiment. In order to write the result of the non-linear function circuit to p memory cells representing neuron output values, p write operations may be performed continuously, but by providing p write circuits, the write operations are performed in parallel. It can be done easily. In this case, time loss due to writing to a plurality of memory cells can be avoided. It is needless to say that the speed of the reading operation can be increased by providing a plurality of reading circuits. In the embodiment of FIG. 13, if a multi-input circuit is used as the multipliers m1,..., Mn, a similar circuit can be realized without providing the adders a1,..., An, b1,. In addition, the configuration of the arithmetic circuit can be variously modified.

In the embodiment of FIG. 13, p memory cells are used to store neuron output values, and q memory cells are used to store connection weight values. That is, the neuron output value is represented by p bits, and the connection weight value is represented by q bits. Since there are various methods for expressing information with a plurality of bits, an expression method may be selected as necessary, and the characteristics of an adder, a multiplier, or a nonlinear function circuit may be designed accordingly. For example, the neuron output value can be represented by the number of memory cells whose contents are 1 among the p-bit memory cells representing the neuron output value. FIG.
The fourth embodiment is an embodiment of the input / output characteristics of the nonlinear function circuit D suitable for such a case. In FIG. 14, g
1, g2,..., Gp indicate p outputs of the nonlinear function circuit D. Each output takes a value of 0 or 1, and writes 0 or 1 to the corresponding p memory cells through a write circuit WR (omitted in the figure). g1, g
2,..., Gp are inputs xth1, xth2,
.., Xthp becomes 1 and 0 otherwise.
xth1, xth2,..., xthp are input upper limits x
The interval may be set at an equal interval between 1 and the lower limit x2, or may be set at an arbitrary interval. For example, xthk and xt
By setting the interval of hk + 1 (k = 1,..., p−1) as shown in FIG. 15, a nonlinear function circuit g having a sigmoidal characteristic can be realized. According to the present embodiment, one neuron output value can have p values by using p memory cells. In this embodiment, p memory cells representing neuron output values are treated equivalently. That is, even if the information of any of the p memory cells is inverted or fixed, the effect on the neuron output value is equal.
Therefore, the influence on the neuron output value due to the destruction of information of one memory cell can be reduced as compared with a general binary expression. In the following, such an expression will be referred to as an equivalent expression. Here, the neuron output value has been described. Of course, the above equivalent expression can be used for the connection weight value.

Of course, a binary representation can also be used.
In this case, since 2p values can be expressed by p bits, it is suitable for expressing many values with a small number of memory cells. FIG. 16 shows an embodiment in which a binary expression is used for the neuron output value and the connection weight value. In the array A, only the memory cells on the data line where i = h (h = 1, 2,... N), and in the array B, the data line with i = h and s = f (f = 1, 2,. Only memory cells on the word line m-1) are shown. In FIG. 16, WT
Is a weighting circuit, which weights the signal of the memory cell and transmits it to the adders ah and bh. Here, the weighting coefficient is 1 to 2p for the neuron output value as shown.
The connection weight value is changed from 1 to 2q for each memory cell. As a result, the neuron output value and the connection weight value input to the multiplier mh can take 2p and 2q values, respectively. The method of selecting an address for calculating the neuron output value may be in accordance with FIG. 12 as in the embodiment of FIG. FIG. 17 shows one example of the characteristics of the nonlinear function circuit D in the embodiment of FIG. g1
Is 0 and 1 each time the input changes by (x2-x1) / 2p
Are alternately repeated, and g2 is 0 and 1 at twice the cycle of g1.
Is alternately repeated. In the same manner, gp is changed by changing the cycle by twice.
In this example, the value is set to be from 0 to 1 with (x2-x1) / 2 as a boundary. That is, the nonlinear function circuit D may be designed to operate as an A / D converter. In addition,
Also in this embodiment, the nonlinear function circuit D can be designed so that the neuron output value increases nonlinearly with respect to the input. For example, to increase the neuron output value in the form of a sigmoid function with respect to the input, the period at which each output changes is decreased as the input increases while the ratio of the periods between different g is kept constant. Is (x2-x1) /
From the point beyond 2, the period may be increased as the input increases. As described above, FIG.
According to the embodiment shown in FIG. 7, p and q memory cells are used to represent the neuron output value and the connection weight value, respectively, and the neuron output value and the connection weight value are respectively 2 and 2.
It can have p, 2q values. Therefore, it is suitable for giving a large number of neuron output values and connection weight values with a small number of memory cells. Also in this embodiment, a multi-input circuit is used as the multipliers m1,..., Mn, and the weighting circuit WT and the adders a1,.
Of course, various modifications are possible, such as giving the functions of 1,..., Bn to the multiplier. Here, an embodiment using an equivalent expression and a binary number has been described. However, there are various other methods of expressing a negative number using a sign bit and expressing information by a plurality of bits. So you can use them as needed.

Next, a dynamic memory cell (DRA) composed of one MOS transistor and one capacitor
An example in which (M cells) are used in a memory circuit will be described.

FIG. 18 shows the embodiment shown in FIG.
This is an embodiment configured using M cells. In FIG. 18, an array A and an array B are a plurality of data line pairs DA1, / DA1,..., DAn, / DAn, DB1, which cross each other.
/ DB1,... DBn, / DBn and a plurality of word lines WA
1, WA2,..., WAm, WB1,1, WB1,2,.
, WB2,2,..., WBm-1, n, and memory cells MC provided at intersections thereof. The memory cell MC is provided at one of the intersections of a pair of a data line and a word line. In the figure, PR, SA, RSA, and WS are a precharge circuit, a sense amplifier, a read sense amplifier, and a write switch, and correspond to the array control circuits 13A and 13B in FIG.
MT in the operation circuit is a multiplication circuit. Reference numeral 16 denotes a clock generation circuit which is an address ADD given from outside the chip.
A, ADDB and chip select signals / CSA, /
Clock for controlling other circuits by CSB etc.
A, ΔB, etc. are generated.

The operation of the embodiment shown in FIG. 18 will be described below with reference to FIGS. 19, 20 and 21. FIG. 19 shows an embodiment of the relationship between the operation mode and the external signal. As described above, in the first half of the operation mode, the word lines of the memory cell arrays A and B are activated one by one, and in the latter half, one word line of the memory cell array A is activated.
In the memory mode, reading and writing are performed independently in the memory cell arrays A and B. In FIG. 19, the operation modes are further subdivided in order to easily perform these controls. AR, AW, BR, BW in the memory mode are:
These modes are for reading from array A, writing to array A, reading from array B, and writing to array B, respectively. Also, NR, NW in the calculation mode
Are the first half of reading data and performing the calculation, and the second half of writing the calculation result. In this embodiment, in order to switch these six modes, the chip select signals / CSA and / CSB and the write control signal / W
E, four external input signals of the arithmetic circuit control signal / NE were used. The chip select signals / CSA and / CSB specify selection of a chip and selection of arrays A and B. / CS
A and / CSB are both H (high level), the chip is unselected, / CSA is L (low level) and array A is / CS
When B is L (low level), the array B is in the selected state. As described above, the write control signal / WE is a signal for switching between writing and reading, and the reading operation is performed at H and the writing operation is performed at L. As for / NE, as described above, H indicates the memory mode, and L indicates the calculation mode. Therefore, for example, / CSA and / CSB are both L, / WE is H, / NE
Let L be the mode NR in the first half of the calculation mode in which reading is performed from both arrays A and B. Since the switching of the arrays A and B is specified by the chip select signal, the address signals can be divided into an address group ADDA for selecting the memory cells of the array A and an address group ADDB for selecting the memory cells of the array B. . Here, the address group ADDA includes an X-system address for selecting the word line of the array A and a Y address for selecting the data line of the array A.
This is a general term for a group of system addresses. Similarly, the address group ADDB is a general term for a group of an X-system address for selecting a word line of the array B and a Y-system address for selecting a data line of the array B. In each operation mode, these address groups are applied to the address pins according to FIG. According to the embodiment of FIG. 19 described above, two chip select signals are provided and the array A,
B was switched, and the addresses were separated between arrays A and B. Therefore, since the arrays A and B can be selected independently, it is possible to easily control each operation mode in which both or one of the arrays A and B needs to be selected. Note that FIG.
Other than that, the relationship between the operation mode and the external signal can be realized in various modifications. For example, the chip select signal is set to only / CS, and an address for switching between the arrays A and B is added. The X address for selecting the word line of the array B in the mode NR may be generated by a counter provided inside the chip.

FIG. 20 shows an example of the waveform of FIG. 18 in the memory mode, and FIG. 21 shows an example of the waveform of FIG. 18 in the calculation mode.

The operation in the memory mode is the same as the ordinary DRAM read / write operation. FIG. 20 shows a read operation for a memory cell at the intersection of word line WA1 and data line DA1 in array A in the memory mode.
(Mode AR) and the voltage waveform when the write operation (mode AW) is performed successively. In the figure, Vcc is
It shows a positive potential. Since the operation mode is the memory mode, the operation circuit control signal / NE is at a high level, whereby the operation circuit start signal ΦN is fixed at a low potential and the operation circuit 12 is off. Before starting the read operation, PPA and PNA
Is set to Vcc / 2, so that the sense amplifier SA is off. Still, the precharge signal ΦpA
Is at a high potential, the precharge circuit PR is turned on, the data line pair of DA1, / DA1,..., DAn, / DAn is short-circuited and the potential is set to the precharge potential VH. VH is set to Vcc / 2. When the chip select signal / CSA becomes low potential, the precharge signal ΦpA falls, the precharge circuit PR is turned off, and the word line WA1 selected by the address signal ADDA and the read Y selection signal YRA1 transition to high potential. . As a result, the MOS transistors of all the memory cells MC connected to the word line WA1 are turned on, and the data line pair DA1, / DA1,
.., DAn and / DAn each have a slight potential difference. This potential difference is detected by the read sense amplifier RSA to which the read Y selection signal YRA1 is input, and the read lines OA,
/ OA. The input / output circuit converts this to a voltage difference, amplifies it, and reads the potential corresponding to 1 or 0 as the content of the memory cell.
Output as In parallel with these operations, a so-called rewrite operation is performed as follows. Data line pair DA1,
After a slight potential difference occurs between / DA1,..., DAn, and / DAn, the sense amplifier SA is activated by transitioning PPA to a high potential and PNA to a low potential. Therefore, a slight potential difference generated in the data line pair is amplified, and the data line on the high potential side transitions to Vcc and the data line on the low potential side transitions to 0V. As a result, the potential corresponding to the information before reading is written again to the capacitances of all the memory cells MC connected to the word line WA1. After the end of the rewrite operation, when the chip select signal / CSA becomes high potential, the selected word line WA1 and the read Y select signal YRA1 transition to low potential, and then PPA and PNA transition to Vcc / 2. The sense amplifier SA is turned off, and the precharge signal ΦpA transitions to a high potential. As a result, the data line pair is short-circuited, the potential is set to the precharge potential VH, and the data line pair returns to the original state. The above is the reading operation.

Subsequently, a write operation to the same cell (mode A)
Move to W). In the write operation, the chip select signal / C
When SA becomes low potential and the write control input / WE becomes low potential, the information given to the write data DI is written to the selected memory cell in the array A. In the write operation, first, the chip select signal / CSA
Becomes low, the precharge signal ΦpA falls, and the precharge circuit PR is turned off. Next, the word line WA1 selected by the address signal ADDA and the read Y selection signal YRA1 transition to a high potential. as a result,
The MOS transistors of all the memory cells MC connected to the word line WA1 conduct, and the data line pairs DA1, / DA1,..., DAn, /
A slight potential difference occurs between DAn. The subtle potential difference generated in the data line pair is amplified by the sense amplifier SA. Subsequently, the input circuit start signal ΦWA generated by the transition of the write control input / WE to the low potential.
R transitions to a high potential. As a result, the write data DI
Is transmitted as a differential signal to the write line pair IA, / IA. Also, the write Y selection signal YWA1
Transitions to a high potential, and the write switch WS connected to the memory cell at the write destination is turned on. As a result, the write line pair IA, / IA is electrically connected to the data line pair DA1, / DA1, respectively. As a result, the data line pair DA1, / DA1 is set to a potential corresponding to the information given to the write data DI. Thereafter, the input circuit activation signal φWAR transitions to a low potential, but the potential of the data line pair is maintained by the sense amplifier SA. In the data line pair in which the write switch WS is not turned on, the signal read first is amplified by the sense amplifier as it is, and rewriting is performed. After the end of the rewrite operation, when the chip select signal / CSA becomes high potential,
The selected word line WA1 and the write Y selection signal YWA1
Changes to a low potential, and then PPA and PNA are changed to Vcc / 2.
And the sense amplifier SA is turned off, and the precharge signal ΦpA is changed to a high potential. As a result,
The data line pair is short-circuited, the potential is set to the precharge potential VH, and the data line pair returns to the original state. The above is the writing operation.

Here, the case where the read operation and the write operation are successively performed on the same memory cell in array A has been described. However, the read operation or the write operation can be performed successively, respectively. A
Of course, by switching W, BR, and BW, a read operation or a write operation can be performed on a memory cell at a desired position in a different memory array every time a read operation or a write operation is performed.

Next, the operation in the operation mode will be described.
FIG. 21 shows operation waveforms for obtaining the neuron output value V12. It is assumed that necessary connection weight values, neuron output values, and the like have already been written by the writing operation in the memory mode. First, in order to set the mode NR, the chip select signals / CSA and / CSB are set to low level, the write control signal / WE is set to high level, and the arithmetic circuit control signal / NE is set to low level. Address ADD
A and ADDB are the word line WA1 of the array A and the array B
Is set to select the word line WB1. / CSA
And / CSB go low, the precharge signals .PHI.PA and .PHI.PB go low, and / NE goes low, causing the arithmetic circuit start signal .phi.N to go high. Subsequently, the word lines WA1 and WB1 rise and WA
Neuron output value V stored in the memory cell on
, Vn1, and connection weight values T111, T1
, T11n are read out on the data lines. Thus, the neuron output value read from the array A and the connection weight read from the array B are input to the multiplication circuit MT activated by the operation circuit activation signal ΦN as shown in FIG. In the multiplication circuit MT, the data line on the array A side and the data line on the array B side are connected to the gates of MOS transistors, and these MOS transistors are connected to each other through a switch MOS transistor to which an arithmetic circuit start signal ΦN is input. It is connected to the product-sum output line NO and the dummy line DM. One end of the product-sum output line NO is connected to the power supply VM through the load RM1, and one end of the dummy line DM is grounded. The signal read to the data line is applied to Vcc or 0 V by the sense amplifier SA.
Is amplified, the product of the neuron output value and the connection weight value becomes 1
, The current flows from the power supply VM to the ground electrode through the load RM1. Therefore, the potential of the product-sum output line NO falls in proportion to the number of combinations in which the product of the neuron output value and the connection weight value is 1. The product-sum output line NO is
It is input to the nonlinear function circuit D. Nonlinear function circuit D
Detects whether the sum of the product of the neuron output value and the connection weight value is large and the potential of the product-sum output line NO falls below the reference voltage VR, and outputs the result to NV. In the waveform of the product-sum output line NO shown in FIG. 21, a solid line indicates a case where the result of the product-sum is small, and a broken line indicates a case where the result of the product-sum is large.
The input / output circuit detects the result of the nonlinear function circuit D, and outputs a neuron output value V12 to be written to the next memory cell to the write line pair IA, / IA. FIG. 21 shows the waveform of the IA. The IA is at a high level as indicated by a broken line when the sum of products is large, and is at a low level as indicated by a solid line when the sum of products is small. / IA is in opposite phase to IA. Write line pair I
When the neuron output value is output to A and / IA, the latch signal ΦL transitions to a high potential. As a result, the potential output to the write line pair IA, / IA is latched by the latch circuit provided in the input / output circuit IO. Latch signal ΦL
Receives I / O in response to the fall of the arithmetic circuit activation signal / NE.
What is necessary is to delay and start up until a signal appears at A, / IA. Subsequently, the arithmetic circuit start signal ΦN transitions to a low potential to turn off the arithmetic circuit, and after the word line falls, the data line is recharged as in the memory mode.
At this time, the latch signal ΦL is kept at the high potential, and the neuron output value output to the write line pair IA, / IA is kept.

Next, the process proceeds to the mode NW which is the latter half of the operation mode. First, the chip select signal / CSA and the write control signal / WE are set to low level,
B is set to a high level so that a memory cell to which a neuron output value in array A is to be written is selected.
Switch A. The arithmetic circuit activation signal / NE is kept at a low level. As a result of the fall of / CSA, the precharge signal ΦPA becomes low level, and the array A can be written. Subsequently, the selected word line WA
2. The write Y selection signal YWA1 rises. As a result, the neuron output value V12 output to the write line pair IA, / IA is written to the memory cell connected to the word line WA2 and the data line DA1. Finally, all the word lines are dropped to perform precharge. Further, when the arithmetic circuit control signal / NE rises, the latch signal φL falls and the latch is released. Thus, the next operation is prepared. The above is the operation in the operation mode. By continuing the same operation with changing the address according to FIG. 12, all neuron output values can be calculated.

In the above, the dummy line D of the multiplier MT
The circuit connected to M may be omitted, but the multiplier MT
If the gate capacitance or the like of the MOS transistor is attached to only one of the data lines, the data line capacitance becomes unbalanced and, in some cases, may hinder the operation of the sense amplifier. In such a case, if the data line capacitance is unbalanced as shown in FIG.

Next, an embodiment of a circuit suitable for use in FIG. 18 will be described. FIG. 22A shows an embodiment of the nonlinear function circuit D. In this embodiment, the bipolar transistor Q7
20, Q719, a resistor R72 and a MOS transistor Q721, and an inverter INV75.
And MOS transistors Q715, Q716, Q71
7, Q718, a resistor R71 and a diode D71. This circuit is started when the signal ΦN becomes high potential. FIG. 22B shows the potential of the product-sum output line NO, which is the input of the nonlinear function circuit D, and the output N.
5 shows the relationship between V potentials. When the potential of the product-sum output line NO is lower than the reference potential VR, the output NV is high, and when the potential of NO is higher than the reference potential VR, the output NV is low. According to the present embodiment, since a bipolar transistor is used for the differential amplifier, it is possible to realize a non-linear circuit having a characteristic with a sharp rise with respect to an input change. Further, by setting the reference potential VR to a desired value, the characteristics of the nonlinear function circuit D can be easily changed. Note that the output of the differential amplifier cannot be so large to avoid saturation of the bipolar transistor Q719. Therefore, if the output of the differential amplifier is directly connected to the subsequent inverter, the inverter may not operate. Therefore, a resistor R71 and a diode D71 are provided to lower the potential input to the MOS transistor Q717.

FIG. 23 shows an embodiment of the input / output circuit IO. As shown in FIG. 23, the write circuit WR includes an input buffer INBUF and write changeover switches SWA and SW.
B, latch circuit LAT and inverter INVIA, I
It consists of NVIB. The write changeover switches SWA and SWB are used to switch between the memory cells of the array A and the array B to write the write data DI. When the switching signal ΦWRA is at a high potential, the write data DI
Array A from write line pair IA, / IA through BUF
Is written to the memory cells in the cell. Switching signal ΦWRB
Is high potential, the write data DI is written to the memory cells in the array B from the write line pair IB, / IB through the input buffer INBUF. Latch circuit LA
T latches the information output to the output NV of the non-linear circuit D in the operation mode, and sets the write line pair IA, / IA
This is for writing data into the memory cells in the array A. As is apparent from the figure, the relationship between the output NV of the nonlinear circuit D and the potential relationship between the write line pair IA and / IA is in-phase, so the relationship between the product sum output line NO of the nonlinear function circuit D and the potential of the input common line IA. Have an inversion relationship as shown in FIG. As described above, in the embodiment of FIG. 18, since the potential of the product-sum output line NO decreases as the product sum of the neuron output value and the connection weight value increases, the relationship between the product-sum output line NO and the potential of the input common line IA Are configured to have an inverting relationship. When the potential of the product-sum output line NO is designed to increase as the product sum of the neuron output value and the connection weight value increases, the relationship between the product-sum output line NO and the potential of the input common line IA becomes an in-phase relationship. Needless to say, the circuit may be configured as described above.

FIG. 25 shows an embodiment of the read circuit OUT. The read circuit OUT is a current-voltage conversion circuit IVOUT
1, level shift circuit LS, read latch circuit OUTL
T and an output buffer BUFOUT.
In the current-voltage conversion circuit IVOUT1, the read lines OA, /
The information read as the difference in impedance between OA and the read lines OB and / OB is OA 'and / OA', respectively.
Alternatively, it is converted into a voltage difference between the read lines OB 'and / OB'. In the level shift circuit LS, the current-voltage conversion circuit IV
The voltage of the information read from OUT1 is shifted to a level at which the bipolar transistor in the subsequent read latch circuit OUTLT is not saturated, and transmitted to the read latch circuit OUTLT.

FIG. 26 shows a detailed embodiment of the read latch circuit OUTLT. The read differential amplifiers AMPA and AMPB in the read latch circuit OUTLT connect the memory cells of the array A to the read lines OA and / OA through the read lines OA and / OA.
To switch which of the information read out from the memory cell of the array B and the information read out from the memory cells of the array B into the read lines L3 and L4 through the read lines OB and / OB as the read data DO. When the switching signal ΦA is at a high potential,
When the information read from the memory cells of array A is high and the switching signal ΦB is at a high potential, the information read from the memory cells of array B is output as read data DO. In read latch circuit OUTLT, when read latch signal φLR transitions to a potential higher than voltage VB2, bipolar transistor Q1A turns off and Q1B turns on. Therefore, the differential amplifiers AMPA and AMPB are turned off,
The PC turns on. As a result, the read information is latched by the differential amplifier AMPC and the level shift circuit LSC.
That is, according to the present embodiment, after the read information is determined, the read latch signal ΦLR transitions to a potential higher than the voltage VB2, thereby enabling the read data DO for a desired period.
Can be latched and output.

In the embodiment of the multiplier MT shown in FIG. 18, the data line pair of the array A is connected to the gate of the MOS transistor farther from the ground electrode than the data line pair of the array B. Therefore, when taking the product, the neuron output value and the connection weight value are not treated equivalently. If this poses a problem, the embodiment of FIG. 27 may be used.
In FIG. 27, data line DAi is connected to MOS transistor Q7.
C3, Q7C6, and DBi are connected to the gates of Q7C5 and Q7C4. In both cases, the MOS closer to the ground electrode
Since the transistor is connected to the farthest MOS transistor, the neuron output value and the connection weight value are treated equivalently when taking the product.

As described above, according to the embodiment shown in FIG. 18, the embodiment shown in FIG. 10 can be realized using a DRAM cell composed of one MOS transistor and one capacitor. Since the occupied area of the DRAM cell can be made very small, there is an advantage that the DRAM cell can be realized with high integration on a chip.

Although not described in the above description, as is well known, in a DRAM cell using one transistor and one capacitor, it is necessary to compensate for a decrease in accumulated charge due to current leakage of the capacitor within a certain period of time. Requires a refresh operation. Also in the present invention, the refresh operation can be easily performed as necessary regardless of the memory mode and the operation mode, similarly to a normal DRAM.

In the above embodiment, the memory cells are DR
Although an AM cell is used, the present invention is not limited to this, and a similar information processing device can be realized using another memory cell. Next, an embodiment using an SRAM cell will be described. FIG.
(A) and (b) are embodiments of an SRAM cell, and both of them do not require a rewrite or refresh operation unlike DRAM cells, and thus have the advantage that control can be performed more easily than in the case of using DRAM cells. . FIG. 29 corresponds to FIG.
FIG. 10 shows an example in which the SRAM cell shown in FIG.
This is one embodiment for realizing the embodiment of the present invention. In FIG. 29, MCS is an SRAM cell, and LD is a data line load. 30 and 31 show examples of operation waveforms. FIG.
FIG. 31 shows an example in which the read operation and the write operation are continuously performed on the cells connected to data lines DA1, / DA1 and word line WA1 in the memory mode. FIG. 31 shows the operation on word line WA1 in the operation mode. The neuron output values V11, V21,..., Vn1 stored in the memory cells
, T1n1 stored in the memory cell on the word line WB1 and the calculation value of the neuron output value V12. The basic operation is the same as in the case of the DRAM cell described above, and a description thereof will be omitted. An SRAM cell has an advantage that control is simpler than that of a DRAM cell because a rewrite operation and a refresh operation are not required. Further, since the rewrite operation is not required, there is an advantage that the read / write speed in the memory mode and the cycle in the operation mode can be increased.

The example of the circuit configuration for realizing the embodiment of FIG. 10 using the DRAM cell and the SRAM cell has been described above. Next, an example of a circuit configuration for expressing a neuron output value and a connection weight value using a plurality of memory cells will be described. Hereinafter, an embodiment using a DRAM cell will be described, but it is needless to say that the same can be realized by using an SRAM cell.

Next, an example of a circuit configuration for expressing a neuron output value and a connection weight value using a plurality of memory cells using DRAM cells will be described.

In FIG. 32, a pair of data lines DA11, / DA11, DA12, / DA12,.
A1P and / DA1P correspond to the data line pairs in the array A input to the adder a1 in FIG. Also, a pair of data lines DAn1, / DAn1, D in array A
, DAnP, / DAnP correspond to the data line pairs in the array A input to the adder an in FIG. The same applies to array B. As shown in the input / output circuit DIO10, the input terminal
R of O1,..., DOr, output terminals are DI1,.
By providing r r (where r is the larger of p and q), p-bit or q-bit information representing a neuron output value or a connection weight value can be simultaneously read or written in the memory mode. ing. In the operation mode, in the array A, the information for each p bit read out to the data line by the rise of the word line is synthesized by the adder ADD, and the neuron output value output lines VO1, VO2,. Is output. Also in the array B, the q-bit information read to the data line by the rise of the word line is synthesized by the adder ADD, and the connection weight value output line TO
The connection weight value is output to 1, TO2,..., TOn. These are input to BLK2, where a product-sum operation is performed and input to the nonlinear function circuit D10. The output of the nonlinear function circuit D10 corresponding to the neuron output value is the input / output circuit DIO.
10 is latched by the latch signal φL. Subsequently, the address is switched so as to select the p cells to which the obtained neuron output values are to be written, the write Y selection signal YWAi is raised, and the latched neuron output values are paralleled to the selected p cells. Write to. By continuing such an operation, the neuron output value can be updated in the same manner as in the embodiment of FIG. According to the present embodiment, the embodiment of FIG. 13 can be realized by equivalently adding information of a plurality of memory cells input to the adder ADD. Further, the information of the plurality of memory cells input to the adder ADD is weighted for each bit and added, thereby realizing the embodiment of FIG. 16 in which the neuron output value and the connection weight value are represented by a binary number of a plurality of bits. be able to. In addition, since it is possible to easily deal with the case where the neuron output value and the connection weight value are represented by a plurality of bits by another method, various information processing can be performed according to the purpose. In this embodiment, the DRA
Since M cells are used, high integration can be achieved.
Further, in both the memory mode and the operation mode, the information of a plurality of memory cells is handled in parallel, so that the neuron output value and the connection weight value are represented by a plurality of bits, but are represented by one bit. High-speed information processing. Here, signals of a plurality of memory cells are combined by an adder in BLK1, and the result is input to BLK2 which is a product-sum circuit. However, various modifications are possible, such as omitting the addition in the BLK1 and inputting in parallel the information of a plurality of memory cells representing the neuron output value or the connection weight value to the product-sum circuit BLK2 to perform the product-sum operation.

In the following, a method for realizing the embodiment shown in FIG. 13 in which the neuron output value and the connection weight value are represented by a plurality of equivalent bits according to the embodiment shown in FIG. 32 will be described. FIG. 33 shows an example of the BLK1 of FIG. Here, BLK1 connected to the data lines DA11,... DA1P of the array A is shown. The same circuit can be used for the other BLK1 of the array A. In the array B, if the number of data line pairs, read line pairs, or write line pairs is changed from p to q and the number of p provided circuits such as the precharge circuit PR is changed to q, the circuit of this embodiment is used. be able to. In this embodiment, p read line pairs OA1 and / OA are connected so that writing or reading can be performed on p memory cells in parallel.
1,..., OAp, / OAp and p pairs of write line pairs IA
1, / IA1,..., IAp, / IAp. The read sense amplifier RSA and the write switch WS are sequentially connected to the read line pair OA in the same BLK1 as shown in FIG.
, OAp, / OAp, and p write line pairs IA1, / IA1, ..., IAp, / IAp. That is, as for a pair of read lines or write lines, every p pairs are connected to a data line pair. The addition circuit ADD includes a load circuit LD103 and p voltage-current converters VI. In the voltage-current converter VI, the data lines DA11, DA12,
.., DA1p are connected to the gate of the MOS transistor. The MOS transistor is connected in series with the MOS transistor to which the arithmetic circuit start signal ΦN is input to the gate, and the ground electrode and the neuron output value output line VO are connected.
Connected to 1. The neuron output value output line VO1 is connected to a power supply VM01 through a resistor in a load circuit. Therefore, when the amplification of the data line potential is completed in a state activated by the arithmetic circuit activation signal ΦN, the potential of the neuron output value output line V01 decreases by a voltage in proportion to the high potential, that is, the number of data lines that have become Vcc. . Therefore, according to the present embodiment, the neuron output value can be represented by the potential drop of the neuron output value output line V01. Note that one side of the data line, / DA11,.
The reason why a similar circuit is provided in DA1p is to avoid imbalance in data line capacitance for the same reason as in the multiplier MT of FIG. According to the above embodiment, a neuron output value or a connection weight value represented by a plurality of memory cells can be read out to a neuron output value output line or a connection weight value output line.

FIG. 34 shows an embodiment of the block BLK2 for calculating the product sum of the neuron output value and the connection weight value and the nonlinear function circuit D10. In FIG. 34, a block BLK2 includes a load circuit LD102 and a multiplier M
It is composed of T10. Neuron output value output line V
O1, VO2,..., VO and connection weight value output line TO
, TO2 are connected to the gates of the MOS transistors M16c1 and M16c2 in the MT10.
MOS transistor M16c having its gate input
3 is connected in series to connect the ground electrode and the product-sum output line NO. On the other hand, the product-sum output line NO is connected to the load circuit LD102.
Is connected to the power supply VM02 through the resistor R02. Therefore, when the arithmetic circuit activation signal .PHI.N goes high and the circuit is activated, the corresponding neuron output value output lines VO1, VO2,... VO and the connection weight value output lines TO1, TO2,. The larger the sum of the potential products, the lower the potential of the product-sum output line NO. As described above, the neuron output value output lines VO1, VO2,.
Since the potential of O and the connection weight value output lines TO1, TO2,..., Ton decrease almost in proportion to the neuron output value and the magnitude of the connection weight value, the product sum of the neuron output value and the connection weight value is large. The higher the sum-of-products output line NO is, the higher the potential is. The product-sum output line NO is input to the nonlinear function circuit D10. The nonlinear function circuit D10 can be configured by connecting n circuits as shown in FIG. 35 in parallel. FIG.
Is a combination of a differential amplifier and an inverter as in the case of the nonlinear function circuit D of FIG. However, since the polarities of the product-sum output line NO and the product sum of the neuron output value and the connection weight value are different in the embodiments of FIGS. 18 and 32, 33, and 34, the resistance Rx of the differential amplifier is set in FIG. The resistor R72 shown in FIG. For this reason, in FIG. 35, the product-sum output line NO
When Rx (x = 1, 2,..., P) is exceeded, the output NVx transitions to a high potential. Such a nonlinear function circuit DSx is represented by p
By changing the reference voltage VRx as shown in FIG. 36 and changing the reference voltage VRx as shown in FIG. 36, the change amount of the product-sum output line NO can be indicated by the number of the p-outputs NVx having a high potential. According to the present embodiment, the characteristics of the nonlinear function circuit can be easily changed by changing the value of the reference voltage VRx. In the case where the circuit shown in FIG. 34 is used as the multiplier MT10, the potential change of the product-sum output line NO depends on the magnitude of the product sum of the neuron output value and the connection weight value due to the characteristics of the MOS transistor. Generally, it is not linear. Therefore, the value of VRx may be set in consideration of the characteristics of the multiplier or the adder so that the characteristics of the nonlinear function circuit have a desired shape. In some cases, it may be difficult to accurately know the characteristics of individual chips due to fluctuations in manufacturing conditions and the like. In such a case, the known neuron output value and the connection weight value are actually written in the arrays A and B, operated in the operation mode, the potential of the product-sum output line NO is measured, and the value of VRx is calculated according to the result. May be trimmed to meet desired characteristics.

Although the details of the input / output circuit DIO10 in FIG. 32 are omitted here, FIGS.
5, by using a plurality of circuits similar to the read circuit OUT or the write circuit WR shown in FIG. 26, a circuit for reading or writing data in parallel to a plurality of memory cells can be easily realized. Although the configuration of the clock generation circuit 16 is also omitted, it can be easily realized in the same manner as a circuit used for a normal memory.

Next, a method for realizing the embodiment shown in FIG. 16 in which the neuron output value and the connection weight value are represented by a plurality of bits in binary representation will be described with reference to the embodiment shown in FIG. As shown in FIG. 16, in order to add information represented by a plurality of bits in binary notation, it is necessary to add information by weighting information of a plurality of memory cells for each bit. For this purpose, in FIG.
, VI2,..., MO connected to data lines in VIp
The ratio of the gate width of the S transistor is 1: 2: 4:...: 2p
, The potential of the neuron output value output line VO1 becomes 2
Decreases in proportion to the magnitude of the neuron output value in hexadecimal notation. Therefore, if the same circuit is used for other neuron output values or connection weight values, weighted addition as shown in FIG. 16 can be realized. As for the multiplier, the block BLK2 shown in FIG. 34 can be used as it is. It is necessary for the nonlinear function circuit to have an AD converter function in order to convert the operation result output to the product-sum output line NO into binary display again and write the result into a plurality of memory cells. For this purpose, an embodiment as shown in FIG. 37 can be used. In the embodiment of FIG. 37, z (hereinafter, z = 2p) nonlinear function circuits D are used.
S1, DS2,..., DSz are combined with an encoder. Non-linear function circuits DS1, DS2, ..., DSz
In this case, the circuit shown in FIG. 38 is used to adjust the reference voltage VRx using the circuit shown in FIG. Then, as in the embodiment of FIG. 34, outputs NA1, NA2,.
The magnitude of the product sum of the neuron output value and the connection weight value can be known from the number of the high-potential NAz. In this state, the equivalent display of z bits is performed, so that the encoder outputs the binary data of p bits by the encoder and outputs p output lines N
V1, NV2,..., NVp need to be transmitted to the write circuit. Therefore, the encoder of FIG. 37 may have the input / output relationship as shown in FIG. Such an encoder can be easily realized. FIG. 40 shows a configuration example when p = 3. This embodiment can be easily extended even when p = 3.

The above description has been made with reference to a hierarchical neural network as an example. However, the present invention is not limited to a hierarchical neural network,
The embodiments described so far can be applied to other types of networks. FIGS. 41 (a) and (b), and
The embodiment of FIGS. 42 (a) and (b) is an embodiment for realizing information processing by a Hopfield network by the algorithm of FIG. 6 (b). FIG.
(A) is an embodiment for realizing an asynchronous hopfield type network using one memory cell for expressing a neuron output value and a connection weight value.
As described with reference to FIGS. 2 and 4, the basic arithmetic method is the same for a hierarchical neural network and a Hopfield network. However, in a Hopfield type network, calculations are performed using neuron output values from all neurons including itself. Therefore, in FIG. 41A, all neuron output values are stored in one word line in the array A. As shown in the figure, the array B stores the connection weight values necessary for calculating one neuron output value so as to be arranged on the same word line. Updating of the neuron output value can be performed as follows. For example, to update the neuron output value V1, the word line WA of the array A and the j of the array B
= 1 is activated. As a result, g (T11V1 + T12V2 +... + T1nVn), which is a new V1, is calculated. This is expressed as i = 1 on the word line WA of the array A.
What is necessary is just to write to the memory cell at the position of. The same applies to the update of other neuron output values. For example, to update V4, the word line WA of array A and j =
4 word line is activated. As a result, g (T41V1 + T42V2 +... + T4nVn), which is a new V4, is calculated. This may be written to the memory cell at the position of i = 4 on the word line WA of the array A. In this way, by updating the neuron output value Vi in a desired order, the operation of the asynchronous Hopfield network can be performed. To perform the operation of the synchronous Hopfield type network, the memory cell on the word line WA1 is used to store the current neuron output value in the array A as shown in FIG. This can be easily realized if the memoll cell is used to store a new neuron output value. First, the word line WA1 of the array A and the word line j = 1 of the array B are activated. As a result, g (T11
V1 + T12V2 +... + T1nVn) are calculated. This may be written to the memory cell at the position of i = 1 on the word line WA2 of the array A. Subsequently, the neuron output values V2, V3,..., Vn are updated and written to the memory cells on the word line WA2 of the array A. When all the neuron output values have been updated, this time, the roles of the word lines WA1 and WA2 of the array A are changed, and when calculating the neuron output values, the word line WA2 is started up and the neuron output values are stored. The updating of the neuron output value is continued by raising the word line WA1. Less than,
Similarly, the process proceeds while changing the roles of the word lines WA1 and WA2 of the array A. As described above, according to the embodiment of FIG. 41B, it is possible to perform the operation of the synchronous Hopfield network.

Similarly, a Hopfield-type network can be realized by using a plurality of memory cells to express neuron output values and connection weight values. FIG.
(A) is an embodiment for realizing an asynchronous hopfield type network by using p and q memory cells equivalently to express a neuron output value and a connection weight value, respectively. As in FIG. 41A, the array A
All the neuron output values are stored in one of the word lines. However, one neuron output value is represented by p cells. In the array B, the connection weight values necessary for calculating one neuron output value are stored such that they are arranged on the same word line every q cells. Updating of the neuron output value may be performed in the same manner as in the embodiment of FIG. However, since p memory cells are used to express the neuron output value, p output lines of the nonlinear function circuit D are provided so that the operation result can be written in p cells in parallel. As shown in FIG. 41B, a synchronous hop field network can be easily realized as shown in FIG. 42B by using two word lines of the array A. Similarly, as shown in FIG. 16, synchronous and asynchronous Hopfield networks are realized by using a binary representation of p and q memory cells to represent the neuron output value and the connection weight value, respectively. Of course, you can.

FIGS. 10 and 41 (a) and (b) and FIGS. 13 and 42 (a) and (b) have the same basic configuration. Therefore, if the embodiments of FIGS. 18 to 40 are used, FIGS. 41 (a) and (b) and FIGS.
The information processing according to the embodiment (b) can be easily realized. In a Hopfield type network, in the process of continuously updating the neuron output value, the neuron output value may not change because it falls into a state where energy is minimized instead of being minimized, that is, a so-called local minimum. It is possible. To avoid this, a well-known pseudo-annealing method can be used. As described on page 122 of neural network information processing (Sangyo Tosho, written by Hideki Aso), a method of gradually changing the shape of a nonlinear function to realize a pseudo-annealing method is known. According to the present invention, the above-described method can be easily realized by providing a plurality of nonlinear function circuits D having different characteristics, switching the characteristics, or externally controlling the characteristics of the nonlinear function circuit D.

Until now, neuron output values, mainly in hierarchical or Hopfield networks,
Although an example has been described in which the connection weight value is treated as a positive number, depending on the application object, it may be more convenient to assume that both or one of them can take both a positive value and a negative value. The present invention can be easily applied to such a case. FIG. 43 shows an embodiment of the present invention in which both the neuron output value and the connection weight value can take positive and negative values. FIG.
, The neuron output value is stored in a memory cell array A, and the connection weight value is stored in a memory cell array B. Each value is represented by p or q bits representing the magnitude of the absolute value and 1 bit representing the sign. The sign (hereinafter, sign bit) represents a sign “1” and a positive “0” representing a negative. Of the neuron output value and the connection weight read out in the same manner as described above, the p or q bit portion representing the magnitude of the absolute value is an adder, a1,..., An and b1,. bn, and becomes an analog value and is input to the multipliers m1,..., mn. When the neuron output value and the connection weight value are expressed in binary notation, p- and q-bit data input to the adders a1,..., An and b1,. What is necessary is just to input with weighting in the same way as in. On the other hand, the sign bit is
As shown in FIG. 43, the signals are input to exclusive OR (exclusive OR) circuits EOR1,..., EORn. When the sign bits do not match, that is, when the result of the multiplication is negative, the output of the exclusive OR circuit goes high, and when they match, that is, when the result of the multiplication is positive, the output of the exclusive OR circuit goes low. Become. Switch SW1,
, SWn transmit the output of the multiplier to the adders c1,..., Cn when the output of the exclusive OR circuit is at a low level, and transmit the output of the multiplier to the adders c1 ',. Works like that. As a result, the product-sum output line NO:
The sum of positive multiplication results is output to the product-sum output line NO ', and the sum of negative multiplication results is output to the product-sum output line NO'. The nonlinear circuit D converts the difference between the signal of the product-sum output line NO and the signal of the product-sum output line NO 'into a p-bit digital value,
The sign bit is determined based on the magnitude of the signal on the product-sum output line NO and the product-sum output line NO 'and output to the bus SIGN. 14 or FIG. 1 according to the expression of the neuron output value.
The provision of the non-linear characteristic as shown in FIG. 7 can be easily realized by the same method as described above. According to the present embodiment, both the neuron output value and the connection weight value can take positive and negative values. Therefore, there is an advantage that the applicable range of the information processing is expanded. Here, both the neuron output value and the connection weight value take positive and negative values, but modifications such as limiting only one of them to a positive value can be easily realized.

The embodiment has been described in which the product-sum function and the non-linear function circuit required for calculating the neuron output value are realized as the arithmetic circuit. However, a circuit for performing another operation can be added to the operation circuit. For example, the information processing apparatus according to the present invention can be applied to a so-called classification problem in which an input pattern is divided into several sets, such as voice recognition and character recognition using a hierarchical network. In such a case, it is convenient to provide the comparator in the arithmetic circuit as described above. In the classification problem, when an input pattern is clearly classified into a certain class, an expected value corresponding to the class can be obtained as an output. However, when the input pattern is classified into any one of a plurality of classes or is delicate, it may be an intermediate value between the expected values of the plurality of classes. For example, when the input speech in speech recognition is 'K', a neuron output value (expected value) of 1111 is obtained in the output layer with respect to the speech waveform encoded and supplied to the input layer. Is "C", the neuron output of the output layer is given when an intermediate sound waveform of "K" or "C" is given when the connection weight value is set so as to output an output value (expected value) of 0000. Value is 0
Intermediate values such as 001 and 1110 may be output.
In such a case, the neuron output value of the output layer and 'K'
Can be interpreted as a measure that gives the proximity of the input voice to 'K' or 'C'. Therefore, it is convenient to provide a circuit for comparing the neuron output value of the output layer and the expected value of the class in the arithmetic circuit and obtain a distance between the output result and the expected value.

FIG. 44 shows an embodiment in which an arithmetic circuit 12a for comparing a neuron output value and an expected value and an arithmetic circuit 12b for calculating a neuron output value are integrated on one semiconductor chip. In FIG. 44, the expected value is stored in the memory circuit TG, the neuron output value is stored in the memory circuit A, and the connection weight value is stored in the memory circuit B. In order to calculate the neuron output value, the neuron output value is read from the memory circuit A, the connection weight value is read from the memory circuit B, and the neuron output value is calculated by the arithmetic circuit 12b. The result may be written in the memory circuit A. In order to perform the comparison, the neuron output value is read from the memory circuit A, the expected value is read from the memory circuit TG, the distance is obtained in parallel by the arithmetic circuit 12b, and the result is written to the memory circuit TG or output through the input / output device. . In this embodiment, since the memory circuits TG and A and the arithmetic circuit 12a are all on the same chip, the number of buses 1 and 2 can be easily increased and a large number of bits can be processed in parallel. Therefore, there is an advantage that the distance can be calculated at a high speed. In such a configuration, it is convenient to divide the operation mode into a neuron output value calculation mode for calculating a neuron output value and a comparison mode for comparing a neuron output value with an expected value to obtain a distance. Switching of the operation mode is performed, for example, by using two operation circuit control signals / NE1.
And / NE2. That is, when both / NE1 and / NE2 are at the high level, the memory mode, / NE1 is at the low level, / NE2 is at the high level and the neuron output value calculation mode, / NE1 is at the high level,
NE2 may be set to the low level and the comparison mode may be set. In FIG. 44, the memory circuit is divided into three and the arithmetic circuit is divided into two. However, it is needless to say that these may be mixed and configured on a chip. As described above, according to this embodiment, the distance between the neuron output value and the expected value can be obtained at high speed. Therefore, the information processing speed can be increased when it is necessary to compare the neuron output value and each expected value to obtain the distance, such as in pattern recognition using a hierarchical network.

FIG. 45 shows an embodiment of the arithmetic circuit 12a of FIG. 44, which is a circuit for comparing the neuron output value of the output layer with an expected value and calculating the magnitude of the Hamming distance.
In the following, the memory circuits TG, A of FIG.
Alternatively, as shown in FIG. 32, information of a memory cell is read out to a data line pair.
Suppose you have an array A. FIG. 45 shows a comparator CMP
And a comparison result conversion circuit COMPOUT. The comparator CMP includes a comparison circuit CMPU and a load resistor RCMP provided in parallel, and includes a comparison result conversion circuit COMP.
OUT is a differential amplifier AMP211, AMP212,.
It is composed of AMP21Z. In the comparator CMP,
Array TG data lines DTG1, / DTG1,..., DT
Gr, / DTGr and data line DA1, / of array A
DA1,..., DAr, / DAr are input. Here, r is the number of memory cells on one word line, and is equal to the product of n and p when the neuron output value is represented by 1 bit and when the neuron output value is represented by p bits. According to the present embodiment, the data lines DTG1, / DTG1,.
r, / DTGr, and the Hamming distance between the information read on data lines DA1, / DA1,..., DAr, / DAr of array A can be calculated. The operation of this embodiment is as follows. First, the clear signal ΦC is raised, the MOS transistor Q216 is turned on, and the gate voltage of the MOS transistor Q215 is lowered. After the clear signal ΦC falls and the signal is read out to the data line and the data line potential becomes Vcc or 0 V, the comparator is activated by the comparator activation signal ΦCMP. Then, the data line (DTG) input to the comparison circuit
1, DA1), (DTG2, DA2), ..., (DTG
r, DAr) is exclusive OR (EXCLU)
(SIVE-OR) logic. As a result, the gate of the MOS transistor Q215 remains at the low potential when the information is matched between the data line on the array TG side and the data line on the A side. Transition. For this reason, in the comparator CMPU in which the information does not match between the data line on the array TG side and the data line on the A side, MO
S transistor Q215 turns on. As a result, the data lines (DTG1, DA1), (DTG2, DA2),.
As the number of mismatches in each set of (DTGr, DAr) increases, a current flows from the power supply VCMP to the ground electrode through the load resistor RCMP. Therefore, the potential of the comparison line CO decreases as the number of mismatches increases. Comparison line CO
Are differential amplifiers AMP211, AMP212,..., AMP21Z provided in the comparison result conversion circuit COMPOUT.
It is connected to the. The reference voltage VR of these differential amplifiers
If C1, VRC2, and VRCZ are set to appropriate values, the number of the comparison result output lines DCO1, DCO2,... That is, the comparison result conversion circuit COMP
OUT operates as one type of AD converter. As described above, according to the embodiment of FIG. 45, it is possible to compare the information read to the plurality of data lines of the array TG with the information read to the plurality of data lines of the array A to determine the magnitude of the Hamming distance. it can. Therefore, if one word line is selected in each of the array TG and the array A, the same information stored in the memory cells on the selected word line can be compared. Therefore, if each expected value is stored in the memory cell on the word line of the array TG, the neuron output value is compared with the neuron output value stored in the memory cell on one word line of the array A. You can know how close to what expected value. Therefore, even when the obtained neuron output value does not match the expected value corresponding to the class, it is possible to quickly know which class and how close to it.

In the embodiment shown in FIG. 45, the result output to the comparison result output line may be output to the outside of the chip through the input / output circuit every time the comparison is made, or the capacity of the memory circuit TG may be stored as an expected value. It is also possible to set a larger value than necessary for writing, write the data there, and output it collectively.

Finally, an embodiment for further speeding up the device of the present invention using a register will be described. As described above, in the present invention, the operation of calculating necessary neuron output values is continued from the memory circuit, the operation circuit obtains the neuron output values, and the result is written back to the memory circuit. to continue. That is, one operation mode (neuron output value operation mode) cycle includes a read operation and a write operation, and the operation circuit is at rest during the write operation. Therefore, if the time during which the operation circuit is at rest is shortened, the operation mode can be further speeded up. FIG. 46 shows an embodiment in which the operation mode is speeded up based on the above viewpoint. FIG.
6 is the same as the embodiment of FIG.
.., SWr. According to the embodiment of FIG. 46, the neuro output value can be calculated at high speed using the algorithm of FIG. In the following, a description will be given taking a hierarchical network as an example, but the same effect can be obtained in a Hopfield network. In the embodiment of FIG. 46, in order to calculate the output value of the first neuron of the s-th layer, one word line of the memory cell array A is activated to read the neuron output value of the s-th layer, and the switch SW
, SWr are closed and the neuron output value of the s-1th layer is written into the register 14, and the switches SW1,.
Open Wr. Next, one word line of the memory cell array B is started up, and the neurons in the s-1th layer and the first
The connection weight value between the neurons is read out, the neuron output value of the s-1th layer is read out from the register 14, and the output value of the first neuron of the sth layer is calculated by the arithmetic circuit 12. The result is written to the memory cell array A. At this time, one word line of the cell array B is simultaneously activated to read out the connection weight value between the neuron of the s-1th layer and the second neuron of the s-th layer.
The neuron output value of the -1st layer is read out, and the arithmetic circuit 12 calculates the output value of the second neuron of the s-th layer. Hereinafter, the output values of the neurons in the s-th layer are calculated in the same manner.
Next, in order to calculate the output value of the neuron of the s + 1-th layer, one word line of the memory cell array A is activated, and the neuron output value of the s-th layer previously obtained is read out, and the switch SW
, SWr are closed, the neuron output value of the s-th layer is written into the register 14, and the calculation proceeds in the same manner.
As described above, according to the present embodiment, writing and reading can be performed at the same time by providing the register 14, thereby realizing high-speed operation.

Up to now, the method of calculating the neuron output value by using the present invention has been described, and it has been assumed that the necessary connection weight values have already been given. The required connection weight value may be easily given from the beginning depending on the task, but may need to be obtained by so-called learning. For example, in learning for a hierarchical network called back propagation, several neuron output values (test patterns) in the input layer are prepared in advance, and the desired neuron output values are output for the test pattern. The connection weight value as obtained for the layer can be determined. Also, as described in Chapter 2 of Neural Network Information Processing (Sangyo Tosho, written by Hideki Aso), even in a Hopfield type network, a connection weight value is set so that an equilibrium state of neuron output values becomes a desired state. Learning algorithms are known.
To apply such learning to the present invention, 3
There are two ways. The first method is a method in which learning is performed using an external computer, and the obtained connection weight value is written in the information processing apparatus according to the present invention. This method has an advantage that the learning algorithm can be easily changed because the learning can be performed by software, but it is difficult to increase the learning speed. A second method is a method in which an arithmetic circuit for learning is provided in an arithmetic circuit of the device according to the present invention, and learning is performed on-chip. In this method, learning can be performed at high speed, but it may be difficult to integrate all circuits necessary for learning on the same chip. The third method is an intermediate between the first method and the second method, in which a part of the operation required for learning is performed by the apparatus of the present invention, and the remaining part of the operation required for learning is performed by an external computer. How to do. This method has an advantage that the learning speed can be increased as compared with the first method, and the arithmetic circuit of the device of the present invention can be simply configured. Hereinafter, the third method will be specifically described. As a learning method, a back propagation method in a hierarchical network is taken as an example. In the back propagation method (hereinafter referred to as BP method), the connection weight value is updated according to the following equation.

TSij = TSij + εdjSViS−1 djm = (tj−Vjm) g ′ (Ujm) djS = g ′ (UjS) Σi (TS + 1ijdiS + 1) (3) (s = m−1,..., 2) Is a small positive number, tj is a target value of the neuron output value Vjm of the final layer, g ′ is a derivative of the nonlinear function g,
UjS is a quantity before passing the nonlinear function g in the s-th layer j-th neuron and is defined by the following equation.

UjS = Σi (TS-1 jiViS-1 + Θjs) (4) The update of the connection weight value is performed by obtaining the update amount by the above formulas (1) to (4) for each input data for learning. Alternatively, the update amount may be totaled for all the input data for learning, and the update may be performed using the total amount. The update may be performed by adding the following term called the inertia term to the equation (1).

ΜΔTSij ′ (5) Here, μ is a small positive constant, and ΔTSij ′ is a correction amount at the time of the previous update. Learning is continued until the error between the neuron output value of the final layer and its target value becomes sufficiently small.

The above learning can be executed by the embodiment shown in FIG. 44 and an external computer as follows. In the following, a case will be described in which the update is performed based on the total update amount of all the input data, but the same applies to a case in which the connection weight is updated for each input data. Hereinafter, a three-layer network will be described, but the same applies to a case of three or more layers.

First, all input data for learning and their target values are written to the memory circuits A and TG, respectively. Next, a random number having a small absolute value is written to the memory circuit B as an initial value of the connection weight value. Further, the first input data is read as the neuron output value of the first layer to the arithmetic circuit 12b, and similarly, the connection weight value between the first layer and the second layer is read from the memory circuit B to the arithmetic circuit 12b. Multiplication is performed in parallel by the above-described method, and the neuron output value of the second layer is calculated and written to the memory circuit A. Subsequently, the neuron output value of the third layer is calculated and written to the memory circuit A. The above calculation is performed for all the learning input data, and the neuron output value of each layer for each input data, the expected value for each input data, and the connection weight value are read out to a memory outside the chip. Next, an update amount of the connection weight value is calculated by an external computer, and the updated connection weight value is written to the memory circuit B of the device according to the present invention. Note that g '(UjS) in the equations (2) and (3) is also used in the neuron output value VjS in the apparatus according to the present invention.
May be calculated from UjS which is manually applied to the nonlinear function circuit D, or may be calculated by an external computer as g ′ (UjS) = g ′ (g−1 (VjS)) (6) You can also. Further, in order to add the inertia process of the formula (5), the correction amount of the connection weight value is stored in the memory outside the chip every time the update is performed, and the newly obtained correction amount is calculated by the formula (5).
What is necessary is just to add according to a formula.

Learning can be advanced by repeating the above update. To know the progress of the learning, the distance between the neuron output value of the final layer for each input data and its expected value can be used as a guide. This distance can be calculated at high speed by using the embodiment of FIG. Therefore, it is easy to confirm the progress of the learning.

As described above, according to the present invention, the calculation of the neuron output value for the learning input data can be performed at high speed in the apparatus of the present invention. Further, in the present invention, since a memory device composed of a memory array is used for the memory circuits TG, A, and B, all input data, expected values, neuron output values of the previous layer, and the like can be easily stored. By starting up, many bits can be read out in parallel. Therefore, the transfer of information to the external memory can be performed collectively and at high speed. For this reason, learning can be advanced at high speed.

In the present invention, if the capacity of the memory circuit is made sufficiently large, the number of neurons can be easily changed according to the application. In this case, if the number of neurons is significantly changed, the dynamic range of the nonlinear function circuit may need to be changed. In this case, a plurality of non-linear function circuits having different characteristics are provided and switched for use, or
The reference voltage of the amplifier in the nonlinear function circuit can be switched and used. Even when the number of neurons differs for each layer in the hierarchical network, it may be necessary to change the dynamic regime of the nonlinear function circuit for each layer. This case can be dealt with in a similar manner.

Note that, so far, a so-called one-transistor, one-capacitor DRAM cell or a DRAM cell of FIG.
Although the embodiment using the SRAM cell as shown in FIG. 1B has been described, other memory cells can of course be used in the present invention. For example, it is not necessary to frequently rewrite the portion for storing the connection weight value during information processing, so that a non-volatile memory cell is used. You can also change the cell type.

When a memory circuit is highly integrated, a part of memory cells sometimes does not operate due to use of minute wiring. The neural network has a feature that even if the connection weight value is slightly changed, the effect on the function is small. However, when the memory cell storing the neuron output value does not operate, the information processing may be hindered. In order to avoid such a problem, a redundant word line or a data line as used in an ordinary highly integrated semiconductor memory can be provided so that a defective cell is not used.

In FIGS. 22A, 25, 26, 35, etc., bipolar transistors are used.
It can also be realized by OS. Furthermore, it goes without saying that the present invention may be realized by other devices other than the bipolar transistor and the MOS transistor.

Although the description has been given mainly of the hierarchical and hopfield networks as examples, the present invention is not limited to these, and can be applied to neural network information processing using various types of networks. For example, a network such as a Boltzmann machine in which neuron output values are updated stochastically can be realized. As described on page 27 of neural network information processing (Sangyo Tosho, written by Hideki Aso), the Boltzmann machine has a network shape similar to that of a Hopfield type network, but the neuron output value
(0 or 1) is not uniquely determined by the product sum of the neuron output value input to the neuron and the connection weight value,
It has the feature of being determined stochastically. The probability P that the neuron output value becomes 1 is expressed as P = 1 / (1 + exp (−I / T)). Here, I is the product sum of the neuron output value input to the neuron and the connection weight value, and T is a parameter called temperature. According to the present invention, the above Boltzmann machine can be easily realized. For example, the reference voltage VRx of the non-linear circuit D shown in FIG. 35 may be changed over time not in a steady value but in a fluctuation range of the product-sum output line NO. In this way, the neuron output value can be determined stochastically. By changing the changing speed, the same effect as changing the temperature T can be obtained.

Further, when comparing FIG. 12 with FIGS. 41A and 41B, if the capacity of the memory circuit is sufficient, the address of the memory cell storing the neuron output value and the connection weight value is changed. Alone can realize various types of networks with the same device. Therefore, the present invention has high versatility.

Although the application to neural network information processing has been described above, the present invention is not limited to this. Information processing is performed by connecting a large number of arithmetic elements having similar arithmetic functions in a network. Such a device can of course be realized with a high degree of integration.

In the above-described embodiments, an arithmetic circuit that performs analog arithmetic has been mainly described.
The analog operation circuit has advantages of high speed and small circuit scale. However, the present invention is not limited to this, and a digital arithmetic circuit can be used without changing the gist of the invention. In that case, since the digital arithmetic circuit is used, highly accurate calculations can be performed.

[0085]

As described above, according to the present invention, by combining a memory circuit and an arithmetic circuit and performing parallel arithmetic with the arithmetic circuit, a large number of arithmetic units performing relatively simple arithmetic operations can be implemented in a network. A device that performs the same information processing as a parallel distributed processing device such as a neural network connected to a computer can be realized with high integration without increasing the speed.

[Brief description of the drawings]

FIG. 1 is an embodiment showing a configuration when an information processing apparatus according to the present invention is realized on a semiconductor chip.

FIGS. 2A and 2B are diagrams showing the principle of a hierarchical neural network.

FIGS. 3A and 3B are diagrams illustrating examples of characteristics of a nonlinear function circuit D. FIGS.

FIGS. 4A and 4B are diagrams showing the principle of a Hopfield type neural network.

FIG. 5 is an example of a conventional neural network information processing apparatus using a plurality of chips.

6 (a) and 6 (b) show one embodiment of a method for performing operations in parallel on a hierarchical neural network and a Hopfield neural network, respectively.

FIGS. 7 (a) and 7 (b) show a second embodiment of a method for performing operations in parallel on a hierarchical neural network and a Hopfield neural network, respectively.

FIG. 8 is an embodiment showing a configuration in a case where an information processing apparatus according to the present invention is realized by using a memory array capable of reading out a large amount of information onto a data line by selecting one word line.

FIG. 9 is a diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention using two memory arrays capable of reading out a large amount of information on data lines by selecting one word line; .

FIG. 10 shows a neuron output value and a connection weight value in one embodiment showing a correspondence relationship between a neuron output value and a connection weight value and a memory cell when a hierarchical neural network is realized using the embodiment of FIG. An embodiment represented by one memory cell.

11 (a) shows one embodiment showing characteristics of a nonlinear function circuit D suitable for using a binary memory cell in the embodiment of FIG. 10, and FIG. 11 (b) shows the characteristics of the embodiment of FIG. One embodiment showing characteristics of a non-linear function circuit D suitable for using a four-valued memory cell.

FIG. 12 is an embodiment showing a method of selecting a word line and a memory cell in the operation mode in the embodiment of FIG. 10;

FIG. 13 is a second embodiment showing the correspondence between the neuron output value, the connection weight value and the memory cell in the case of realizing a hierarchical neural network using the embodiment of FIG. 9; An embodiment in which a weight value is expressed by a plurality of memory cells.

FIG. 14 shows a neuron output value,
1 is an embodiment showing characteristics of a non-linear function circuit D suitable for expressing a connection weight value equivalently by a plurality of memory cells.

FIG. 15 is an embodiment showing a method of setting Xth1,..., Xthp in FIG.

16 is a third embodiment showing the correspondence between neuron output values, connection weight values and memory cells when a hierarchical neural network is realized using the embodiment of FIG. 9; FIG. An embodiment in which a weight value is expressed by a plurality of memory cells in a binary display.

FIG. 17 shows a neuron output value,
1 is an embodiment showing characteristics of a nonlinear function circuit D suitable for a case where a connection weight value is expressed by a plurality of memory cells in a binary display.

FIG. 18 shows a case where a DRA is added to a memory cell in the embodiment of FIG.
One embodiment using M cells.

FIG. 19 is a diagram illustrating a relationship between an operation mode and an external signal according to an embodiment;

FIG. 20 is an example of an operation waveform in a memory mode of the embodiment of FIG. 18;

FIG. 21 is a diagram illustrating an example of operation waveforms in the calculation mode of the embodiment of FIG. 18;

22A is an embodiment of a nonlinear function circuit D suitable for the embodiment of FIG. 18 and the like, and FIG. 22B is an embodiment showing characteristics of the nonlinear function circuit D of FIG. 22A.

FIG. 23 shows an input / output circuit IO suitable for the embodiment shown in FIG.
One embodiment of.

24 shows a product-sum output line NO and a write line L when the nonlinear function circuit of FIG. 22A and the write circuit of FIG. 23 are used;
One embodiment showing the potential relationship of A.

FIG. 25 is a read circuit OU suitable for the embodiment such as FIG.
One embodiment of T.

FIG. 26 shows an embodiment of a read latch circuit OUTLT suitable for the embodiment of the read circuit OUT of FIG. 25;

FIG. 27 shows a second embodiment of the multiplication circuit MT in FIG. 18;

FIGS. 28A and 28B are examples of an SRAM cell.

FIG. 29 is a circuit diagram of the embodiment shown in FIG.
(A), (b) shows an embodiment in which SRAM cells are used.

FIG. 30 is an example of an operation waveform in the memory mode of the embodiment in FIG. 29;

FIG. 31 is a diagram illustrating one example of an operation waveform in the calculation mode of the embodiment in FIG. 29;

FIG. 32 shows an embodiment in which a DRAM cell is used as a memory cell in the embodiment of FIG. 13 or the embodiment of FIG.

FIG. 33 shows an embodiment of the configuration of a block BLK1 in the embodiment of FIG. 32;

FIG. 34 shows an embodiment of the configuration of a block BLK2 and a non-linear function circuit D10 in the embodiment of FIG. 32.

FIG. 35 shows a non-linear function circuit D1 in the embodiment of FIG. 34;
0, each nonlinear function circuit DSx (x = 1,
2, embodiment, p).

FIG. 36 shows a non-linear function circuit D1 in the embodiment of FIG. 34;
0, each nonlinear function circuit DSx (x = 1,
2, one example of the characteristic of p).

FIG. 37 shows the neuron output value,
One embodiment showing a configuration of a nonlinear function circuit D10 suitable for a case where a connection weight value is represented by a plurality of memory cells in a binary display.

FIG. 38 shows a non-linear function circuit DS in the embodiment of FIG. 32;
One embodiment of the characteristic of x (x = 1, 2,..., z).

FIG. 39 is a diagram illustrating one example of the characteristics of the encoder in the embodiment of FIG. 40;

40 shows an embodiment of the configuration of the encoder in the embodiment of FIG. 37.

FIG. 41 (a) is an embodiment showing a correspondence relationship between a neuron output value, a connection weight value and a memory cell when an asynchronous Hopfield type neural network is realized using the embodiment of FIG. 9; , Neuron output value, and connection weight value are represented by one memory cell, (b)
FIG. 9 shows an example of the relationship between the neuron output values and the connection weight values and the memory cells when a synchronous Hopfield type neural network is realized using the embodiment of FIG. An embodiment in which a value is represented by one memory cell.

FIG. 42 (a) is an embodiment showing a correspondence relationship between a neuron output value, a connection weight value and a memory cell when an asynchronous Hopfield type neural network is realized using the embodiment of FIG. 9; , A neuron output value, and a connection weight value are represented by a plurality of memory cells. FIG. 9B shows a neuron output value when a synchronous Hopfield type neural network is realized using the embodiment of FIG.
In this embodiment, the correspondence between the connection weight value and the memory cell is shown, and the neuron output value and the connection weight value are represented by a plurality of memory cells.

FIG. 43 shows an embodiment in which both positive and negative neuron output values and connection weight values can be taken using sign bits.

FIG. 44 shows an embodiment in which the device according to the present invention has a function of comparing a neuron output value with an expected value.

FIG. 45 shows a memory cell array TG and a memory cell array A
Is an embodiment of a comparison circuit for comparing information read to a plurality of data line pairs and calculating the degree of coincidence.

FIG. 46 shows an embodiment in which registers are provided to speed up updating of neuron output values.

[Explanation of symbols]

A, B, TG: memory circuit, D: nonlinear function circuit, 1
2, 12a, 12b: arithmetic circuit, OUT: readout circuit, m1, m2: multiplier, a1, a2, ... adder, b
1, b2: adder, c1, c2: adder, c1 ', c
2 ': adder, SW1, SW2: switch, WR: write circuit, NE: arithmetic circuit control signal, Vis, Vi: neuron output value, Tij, Tilj: connection weight value, PR
... precharge circuit, SA ... sense amplifier, RSA ... read sense amplifier, WS ... write switch, MT ...
Multiplier, LAT: Latch circuit, OUTLT: Read latch circuit, NO: Product-sum output line, NV: Nonlinear function circuit output line, WAi, WBi, j: Word line, DAi, / DA
i: data line, DBi, / DBi: data line, DTG
i, / DTGi: data line, IA, IA: write line, I
B, IB: write line, OA, OA: read line, OB,
OB: read line, DI: write data, DO: read data, ΦL: latch signal.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshiki Kawajiri 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (56) References JP-A-1-128296 (JP, A) JP-A-1 JP-A-159890 (JP, A) JP-A-63-39191 (JP, A) JP-A-1-30091 (JP, A) JP-A-1-201764 (JP, A) JP-A-2-91881 (JP, A) JP-A-63-76194 (JP, A) JP-A-63-228498 (JP, A) JP-A-63-234497 (JP, A) JP-A-62-145418 (JP, A) 14624 (JP, A) JP-A-63-126018 (JP, A) JP-A-57-43238 (JP, A) JP-A-2-501167 (JP, A) International publication 89/2134 (WO, A1) ( 58) Fields surveyed (Int.Cl. ⁷ , DB name) G06N 1/00-7/08 G06G 7/60 G11C 11/34 G11C 7/0 0 G06F 12/00-12/06 G06F 7/00 G06T 1/00-17/00 G06F 9/30 G06F 15/78 G06F 1/00 332 CSDB (Japan Patent Office) JST file (JOIS)

Claims (7)

(57) [Claims] A plurality of data lines, a plurality of word lines arranged to intersect the plurality of data lines, and a plurality of memory cells arranged at intersections of the plurality of data lines and the plurality of word lines. A memory cell array, an operation circuit for performing an operation using information stored in the memory cell array, and a first circuit for connecting the memory cell array to the operation circuit
A bus, an input / output circuit including a latch circuit, and a second bus connecting the arithmetic circuit and the input / output circuit
And a third bus connecting the memory array and the input / output circuit.
Graphics and, provided with a conversion circuit, a integrated information processing device on a semiconductor chip, or information the memory information by using the third bus is written into the memory cell array from the outside of the chip a first mode read from the cell array to the outside of the chip, and a second mode, in the second mode, the memory by using the first bus
The information is read from the cell array to the arithmetic circuit, and
Operation from the arithmetic circuit to the latch circuit using two buses
An operation of outputting data according to the result, and an operation result in the latch circuit using the third bus.
The conversion circuit performs an operation of writing the corresponding data to the memory array, and the conversion circuit performs the operation of reading the information read by the arithmetic circuit.
The number of data and the operation result written to the memory array.
Operation result so that the number of bits of the
An information processing apparatus characterized in that the information is exchanged . 2. The information processing apparatus according to claim 1, wherein the first mode and the second mode are selected according to a signal from outside the chip. 3. The arithmetic circuit further includes an arithmetic unit and a MOS transistor having a source / drain path between a power supply and the arithmetic unit, and when the first mode is selected, the MOS transistor transistor information processing apparatus according to any one of claims 1 to 2, characterized in that that will be controlled to be turned off. 4. When there are a plurality of said memory cell arrays and said first mode is selected, one of said plurality of memory cell arrays is selected, and said arithmetic unit is one of said plurality of memory arrays. Is arranged between the two memory arrays, and the arithmetic circuit outputs the outputs of the two adjacent memory arrays.
The information processing apparatus according to claim 1, wherein the information processing apparatus receives the information. 5. The information processing apparatus according to claim 1, further comprising a comparison circuit for comparing the operation result with an expected value. 6. The semiconductor device according to claim 1 , further comprising a register provided between said memory array and said arithmetic circuit, wherein said read operation and said write operation are performed simultaneously in said second mode. 6. The information processing apparatus according to any one of claims 1 to 5, 7. Each of the plurality of memory cells is one
4. The semiconductor device according to claim 1, wherein said plurality of data lines comprise a plurality of data line pairs, and each of said plurality of data line pairs is connected to a sense amplifier and a precharge circuit. The information processing device according to claim 6.