JP3352557B2 - How to monitor the electronic control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates, for example those concerning the monitoring method for monitoring the control data at the prototype stage, etc. In the electronic control unit for controlling the control target fuel injection engine and transmission of the electronic control type is there.

[0002]

2. Description of the Related Art In general, for example, in an electronically controlled fuel injection engine mounted on a vehicle, an electronic control unit having a RAM, a ROM and a control CPU is provided for the control, and various sensors are provided for the RAM. Data such as the detected momentarily changing intake air amount and engine speed, as well as predetermined control data such as a control program and various constants and coefficients are stored in the ROM. The fuel injection amount and the like of the engine are controlled by a signal.

[0003] Various data stored in the RAM are stored as data for setting optimum values in accordance with vehicle acceleration, fuel consumption, noise, and the like at the stage of engine design and trial production. Need to be monitored.

In order to monitor the RAM data in the electronic control unit with a personal computer, the applicant has previously provided a monitor device for connecting a terminal of the electronic control unit to the personal computer as a tool. It has been proposed that a RAM monitor section and its control section be provided so that the data in the RAM of the electronic control unit can be easily and exclusively monitored by a tool (see Japanese Patent Application Laid-Open No. 6-284161).

[0005]

However, in the above-mentioned proposal, the monitor CPU of the personal computer directly accesses the control CPU of the electronic control unit. There was a problem that it could not be done, and there was room for improvement.

The present invention has been made in view of the above points, and an object of the present invention is to change the above-described method of monitoring the electronic control unit and the configuration of the monitor device so that even if the electronic control unit is sped up, the speed of the electronic control unit can be increased. To be able to cope well.

[0007]

In order to achieve the above object, according to the present invention, an electronic control unit and a controller for monitoring its RAM data are connected by a DPRAM (Dual Port RAM) accessible from two directions. The monitoring is performed between the control CPU and the controller via the DPRAM.

More specifically, according to the first aspect of the present invention, the electronic control unit that controls a predetermined control object by the control CPU has control data stored in the RAM in the control CPU and has a monitor CPU. A monitoring method for monitoring by a controller is premised, and has the following configuration.

That is, in this method, the monitoring CPU of the controller and the control C of the electronic control unit are used.
A DPRAM accessible from both PUs is prepared.

First, the monitoring CPU of the controller sets a monitoring condition including at least a monitor cycle, a monitor address, and a monitor command in the DPRAM.

Next, the control CPU reads the monitor conditions of the DPRAM and starts a monitor service routine.

[0012] In addition, in control for the CPU reads the monitor address of the DPRAM by the monitor service routine, after you write the RAM data of the control CPU based on the monitoring address in the data area of the DPRAM, control
CPU monitors the DPRAM monitor check data.
Update by incrementing the data check counter.
You. Next, the control CPU interrupts the DPRAM.
Write the code and transfer the controller
Sends an interrupt signal to the CPU for CPU. In addition,
The monitoring CPU on the roller side
Update data for DPRAM monitor check data
Data when the interrupt signal is received.
Electronically based on the PRAM monitor check counter
Command issued by the controller to the control unit
Performs such command-based processing or in the control CPU
To determine whether to perform monitor-related processing for the RAM data
You.

Finally, a monitor CPU on the controller side
Is the control C in the DPRAM based on the determination result.
Read the RAM data of the PU .

According to a second aspect of the present invention, the first aspect of the present invention is provided.
Of monitoring the electronic control unit in the same way as
First, the CPU for monitoring the controller and the electronic control
D that can be accessed from both the control CPU of the control unit
Prepare a PRAM and control the DPRAM.
The monitor CPU of the
Set monitor conditions including address and monitor command, and
Your CPU reads the monitor conditions of the DPRAM and
Activates the monitor service routine and raises the control CPU.
The monitor service routine of the DPRAM
Read the dress and control based on the monitor address
Write RAM data of CPU to data area of DPRAM
After that, the control CPU checks the DPRAM monitor
Control data is updated, and then the control CPU
Write the interrupt code to M and copy it from DPRAM.
Sends an interrupt signal to the monitoring CPU on the controller side.
You. Then, the monitoring CPU on the controller side is
Monitor check of DPRAM based on interrupt signal
Read the update data for the electronic control unit
Commands related to commands issued by the controller to
System processing or RAM data in the control CPU.
It is determined whether to perform the processing of the monitor system related to the data. Finally,
The monitoring CPU on the controller side
DPRAM read based on the interrupt signal
The monitor check data of the above command and monitor
When it is determined that both processes of the
Control within the DPRAM so that system processing is performed with priority
Reads the RAM data of the CPU.

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

According to the first aspect of the present invention, when data stored in the RAM of the electronic control unit is monitored by the controller, at least a monitor cycle, a monitor address, When the monitor conditions including the monitor command are set, the control CPU thereafter controls the DPRAM.
And the monitor service routine is started. The monitor service routine reads the monitor address of the DPRAM and writes the RAM data of the control CPU to the data area of the DPRAM based on the address. Finally, monitor CPU
Thus, the RAM data of the control CPU in the DPRAM is read.

Thus, when monitoring the RAM, the monitoring CPU
Is used to write and read data between the control CPU and the control CPU via the DPRAM.
U can freely adjust the DPR at the timing when the original control is not performed.
Data can be read and written by accessing the AM, and the RAM data can be easily monitored while speeding up the control CPU.

Further, when the RAM monitor as described above, after the RAM data is written into the data area of the DPRAM by the control CPU, DPRA by the control CPU
The monitor check data of M is updated, and then DP
An interrupt code is written to the RAM. As a result, an interrupt signal is sent from the DPRAM to the monitor CPU on the controller side, and the monitor CPU that receives the interrupt signal reads update data of the monitor check data of the DPRAM, and the electronic control unit.
Commands related to commands issued by the controller to the
Monitor related to RAM data in the control system or the control CPU.
It is determined which processing of the data system is to be performed. After a while
The R of the control CPU in the DPRAM is determined by the monitor CPU.
AM data is read. By updating the monitor check data of the DPRAM by the control CPU and reading the update data of the monitor check data by the monitor CPU, the processing involved in the interrupt is determined by software, so that the DPRAM and each CPU can be determined. In this case, only one interrupt circuit is required, so that the circuit configuration can be simplified and the cost can be reduced.

Further, the DPR is controlled by the control CPU.
The monitor check counter is incremented as the AM monitor check data. On the other hand, the monitor CPU that has received the interrupt signal determines whether to perform command-based or monitor-based processing based on the DPRAM monitor-check counter. Is determined. By determining which process should be performed based on the increase in the counter value of the monitor check counter, both processes can be easily identified on a program.

[0028] In the second aspect of the present invention, when the monitor checking data of DPRAM based on the interrupt signal is determined to be processed in both of the frame <br/> command system and monitoring system, the processing of the monitoring system Since the priority is given to the processing, the monitor data does not drop out in time series as in the case where the command processing is prioritized.
By monitoring the M data without omission, it is possible to obtain data with no deviation in analysis.

[0029]

[0030]

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a tool as an adjustment device or a monitor device of an electronic control unit according to an embodiment of the present invention. This tool is used at the stage of development of a control target and the like. The electronic control unit 1 includes an evaluation board 2, a relay box 13 as a relay unit, and a controller 22. The electronic control unit 1 is provided along with a control target. Will be equipped separately from

That is, in FIG. 1, an electronic control unit 1 controls a predetermined control object such as an electronically controlled fuel injection engine. The electronic control unit 1 has an evaluation board 2 mounted thereon. Is the control CP
U3, program ROM4, emulation RAM
5, a memory switching unit 6 for switching between the program ROM 4 and the emulation RAM 5, a unit-side DPR
AM7 (dual port RAM) and evaluation board 2
For example, a relay terminal 8 of 16 bits as a connector located at an end is attached.

The control CPU 3 performs the original control of the control object and, in the meantime, performs the signal processing for the tool in the last priority lower in priority than the original control and other controls. It is. This control CPU 3
Has a built-in RAM (not shown) that stores variables required for control that are detected by sensors not shown and change every moment.

The program ROM 4 is a ROM referred to in the present invention.
And stores a control program necessary for the control CPU 3 to control a control target and predetermined basic control data such as various constants and coefficients.
On the other hand, the emulation RAM 5 stores the program R
In order to rewrite the control data of the OM 4, the control data is temporarily stored. These program ROMs
The emulation RAM 4 and the emulation RAM 5 are connected to the control CPU 3 via a data bus 9 and an address bus 10. The memory switching unit 6 includes a control CPU
3 for selectively switching between the program ROM 4 and the emulation RAM 5. A ROM selection signal is transmitted from the memory switching unit 6 to the program RO.
By outputting the program ROM4 to M4,
By outputting an AM selection signal to the emulation RAM 5, each of the emulation RAMs 5 is selected.

The unit-side DPRAM 7 is different from a normal RAM in that it has two ports and is a RAM that can be accessed from both directions of each port, and has a predetermined capacity (for example, 32 kbytes). One of the ports is connected to the control CPU 3 via the data bus 9 and the address bus 10. Unit side DPRAM7
Is connected to the relay terminal 8 via, for example, a 16-bit bus.

The emulation RAM 5, memory switching unit 6, DPRAM 7, and relay terminal 8 on the evaluation board 2 are provided on the evaluation board 2 until the control data of the program ROM 4 is determined at the stage of development of the control object. For the mass-produced product to be controlled whose data in the program ROM 4 is determined, the electronic control unit 1 is provided with an evaluation board on which only the control CPU 3 and the program ROM 4 are not mounted, such as the emulation RAM 5 and the like.

The relay box 13 has relay terminals 12 and 18 for parallel communication and serial communication, a communication CPU 16 and a serial receiver / driver 17 disposed at the end of the board. . The relay terminal 12 for parallel communication has, for example, 16 bits. The relay terminal 8 on the evaluation board 2 of the electronic control unit 1 has a relatively short length (for example, 10 to 20 cm) of 16 bits (16). Parallel communication cable 1
Can be connected via 2, 12,....

The communication CPU 16 converts parallel communication data and serial communication data. One port of the communication CPU 16 is connected to the parallel communication relay terminal 14 via a 16-bit bus 15, for example. Are connected to a relay terminal 18 for serial communication via the serial receiver / driver 17. The serial receiver / driver 17 is attached to the communication CPU 16 and is used to make input / output data of the communication CPU 16 conform to a standard of a serial communication cable 20 described later. One end of one serial communication cable 20 can be connected to the relay terminal 18 for serial communication, and the other end of the serial communication cable 20 can be connected to the controller 22. In the relay box 13, when, for example, current-driven serial communication data is transmitted from the controller 22 to the electronic control unit 1, the communication CPU 16 converts the serial communication data into parallel communication data and converts the serial communication data into parallel communication data. Unit side DPRA on 1 evaluation board 2
While writing to a predetermined address in M7, communication C
The PU 16 reads parallel communication data at a predetermined address in the DPRAM 7 of the electronic control unit 1 and converts it into serial communication data.
2 is transmitted.

The controller 22 is connected to the I / F box 2
3 (interface box) and a personal computer 30 connected thereto. The personal computer 30 includes a personal computer body 31 having a built-in CPU (not shown) for data analysis (for monitoring), a display 33 connected to the personal computer body 31, and an external input device 32 such as a keyboard.
Consists of The I / F box 23 is for performing serial communication with the relay box 13, and has a relay terminal 24 for serial communication disposed at an end of the board, a communication CPU 26, a serial receiver / driver 25,
An I / F board-side DPRAM 27 and a system bus 28 are mounted. Relay terminal 24 for serial communication
Can be connected to the serial communication relay terminal 18 of the relay box 13 via the serial communication cable 20 as described above. This serial communication cable 20
Is, for example, a current-driven type that converts data into a large or small current and transmits the data. The cable length is, for example, 5 to 6 m.
Therefore, the length of each of the parallel communication cables 12 is set to be longer.

The communication CPU 26 is the same as the communication CPU 16 in the relay box 13 and converts parallel communication data and serial communication data. One port of the communication CPU 26 is connected to the communication CPU 2.
6 is connected to a relay terminal 24 for serial communication via the serial receiver / driver 25 attached to the 6.

The DPRAM 27 on the I / F board side has the same structure as the DPRAM 7 in the electronic control unit 1,
A RAM having a predetermined capacity which can be accessed from each port in two directions, one port of which is connected to the other port of the communication CPU 26, and the other port of the DPRAM 27 is a system bus. 28
It is connected to the.

The system bus 28 of the I / F box 23 is connected to the personal computer 30. This allows the personal computer 30 to rewrite control data stored in the program ROM 4 of the electronic control unit 1 for rewriting the control data.
C for controlling OM emulation and electronic control unit 1
When a command for monitoring various data in the RAM (RAM monitor) in the PU 3 is issued, the RO
M emulation and RAM monitoring are performed.

The control CPU 3 on the evaluation board 2 and the personal computer 30 in the electronic control unit 1 are connected to the DPRAM 7 and the relay terminal 8 on the evaluation board 2, the parallel communication relay terminal 12 on the relay box 13, and the communication CPU.
16, serial communication relay terminal 18, serial communication relay terminal 24 of I / F box 23, communication CPU
26, the DPRAM 27, and the system bus 28 are connected by a one-channel interrupt cable 35, and the interrupt cable 35 transmits and receives an interrupt command.

Here, the configuration of each of the DPRAMs 7 and 27 will be specifically described. As shown in FIG. 2, the DPRAMs 7 and 27 include a command block used for command processing for the electronic control unit 1, a monitor block used for RAM monitoring of the electronic control unit 1, and a status block used for interrupt processing from the personal computer 30. Blocks and are assigned to.

A command area, an option area, a data area, and a status area are allocated to the command block. The command area is an area for writing a command code from the personal computer 30 to the electronic control unit 1. To prevent a read error on the electronic control unit 1, the personal computer 30 replaces the same code with the upper code (H) and the same code. While writing to the lower code (L), the electronic control unit 1 reads them twice.

The option area is an area for storing options (address, number of data, etc.) as auxiliary information for the command. The data area is used to store data for commands (ROM data, monitor addresses, etc.).
Is an area for storing. The status area stores a status code such as an end result or an error after processing the command on the electronic control unit 1 side.

A monitor setting area, a monitor address area and a monitor data area are allocated to the monitor block. In the monitor setting area, turn the monitor ON / O
A switch for FF and a monitor switch / channel number area for setting the number of channels and a set value preset on the electronic control unit 1 side are set from the personal computer 30 side (this data is read by the electronic control unit 1 side, Change the monitor cycle and trigger mode) Monitor cycle / trigger mode area, address setting mode switch area to specify the monitor address setting mode, and the number of pages (upper address) when the monitor address setting mode switch is in the standard mode And a page area for storing.

The monitor address area includes an extended mode area in which a monitor address is specified by 4 bytes including a spare for each channel, and a standard mode in which the monitor address is specified by 3 bytes. The monitor data area is an area for storing monitor data.

The status block is assigned a status area and an interrupt area. The status area includes a status code area, a monitor status code area, a monitor status area, a command check counter, and a monitor check counter. The status code stores a status code (return code) processed by a command. When the personal computer 30 receives an interrupt from the DPRAMs 7 and 27, the personal computer 30 determines the processing system based on the code.

The monitor status code is an area for storing a monitor status code in the monitor processing. When the personal computer 30 receives an interrupt from the DPRAMs 7 and 27, the monitor processing code is determined based on the code.

The monitor status code is an area for writing the status after the monitor service routine processing.

The command check counter is read at the time of interrupt processing on the personal computer 30 side.
To check the number of command error communications, etc.
This represents information for determining the priority of the interrupt processing on the personal computer 30 when the time difference from the monitor and command interrupts from the electronic control unit 1 is small. Then, on the electronic control unit 1 side, a command service routine to be described later is started, and the counter is incremented each time the status is returned.

The monitor check counter is also provided by the personal computer 3.
It is read at the time of interrupt processing on the 0 side, and is used to check for monitor errors and the like.
Represents the information for determining the priority of the interrupt processing on the side. The counter is incremented each time a monitor service routine described later on the electronic control unit 1 side is started.

On the other hand, in the interrupt area, data for generating an interrupt signal on the electronic control unit 1 side is written.
Used to tell the side. That is, when data is written to this interrupt area, the DPRAMs 7 and 2
7, the interrupt flag is set and the DPRAM
An interrupt signal is output from each of the interrupters 7, 27, and the interrupt signal is transmitted to the personal computer 30 through the interrupt cable 35. Upon receiving this interrupt signal, the personal computer 30 executes a command-based or monitor-based process, and then reads the interrupt area. At this time, the interrupt signals of the DPRAMs 7 and 27 are reset. This interrupt area includes a command interrupt identification code, a monitor interrupt identification code, and an interrupt code.

Next, a method of ROM emulation in which the control data stored in the program ROM 4 of the electronic control unit 1 is rewritten from the personal computer 30 side, and the data stored in the RAM of the control CPU 3 are monitored on the personal computer 30 side. The method of the RAM monitor will be specifically described. Note that two Ds are provided between the analysis CPU of the personal computer 30 and the control CPU 3 of the electronic control unit 1.
Although the PRAMs 7 and 27 and the communication CPUs 16 and 26 are connected, basically, an analysis CPU and a control CP
U3 accesses the DPRAMs 7 and 27, writes and reads data, and the like. In the following description, the operations of the communication CPUs 16 and 26 are omitted.

(ROM Emulation) In order to perform this ROM emulation, a command service routine as a communication program provided in the control CPU 3 of the electronic control unit 1 is used. Is performed at a stretch when no control is performed. The emulation RAM 5
On the other hand, when rewriting the ROM data, the control CPU 3 performs the original control or the like based on the control data of the program ROM 4 from the start of this change until the determination is made. Further, in the ROM emulation, until the rewriting of data in the emulation RAM 5 is completed, the control of the control CPU 3 by the memory switching unit 6 is performed.
Is switched to be connected to the program ROM 4,
The control CPU 3 performs the original control based on the ROM data of the program ROM 4.

In the above command service routine, FIG.
The following processing operation is performed as shown in FIG. That is, in the first step S1, the upper command code (H) of the command area in the command block of the DPRAMs 7, 27 is
And the lower command code (L) is read in step S2, and it is determined in step S3 whether both command codes (H) and (L) are different (double check). If the determination is YES, the process proceeds to step S5, where a predetermined code is written in the status area of the command block, and then the process proceeds to step S1.
Go to 0.

On the other hand, if the decision in the step S3 is NO, a command discriminating process is performed in a step S4, each command is processed in accordance with the discriminated result in a step S6, and then, in a step S7, it is determined whether or not an error has occurred. Is determined. If the determination is YES, an error code is written in the status area of the command block in step S8, as in step S5, and then the determination is NO.
In step S9, a predetermined code is written in the status area in step S9, and the process proceeds to step S10. In step S10, a command code write processing command is written to the command status code in the status area of the status block. In the next step S11, the command check counter in the status area of the status block is incremented. In step S12, a predetermined code is written in the command interrupt identification code in the interrupt area of the status block. In the last step S13,
After a predetermined code is written in the interrupt code in the interrupt area, the process ends.

The ROM emulation is performed in the processing order described below, and the processing order for the DPRAMs 7 and 27 is indicated by numbers in FIG. FIG. 5 is a flowchart of ROM emulation.

(1) First, from the personal computer 30 side of the tool,
Prior to the ROM data change command, the change address to be changed, the number of data (how many bytes of data), etc.
DPRAM 7, 27
(Step X1 in FIG. 5).

(2) Next, the personal computer 30 writes the ROM data to be changed into the data area in the command block of the DPRAMs 7 and 27 (step X).
2).

(3) The personal computer 30 writes the ROM data transfer change command in the command area in the command block of the DPRAM 7, 27 (step X3).

(4) A predetermined code is written into the interrupt code of the DPRAMs 7 and 27 from the personal computer 30 by the interrupt cable 35, and the DPRAMs 7 and 27 are written.
Sends an interrupt command to the control CPU 3 of the electronic control unit 1, and the control CPU 3 receiving the interrupt command reads the command code in the option area of the DPRAMs 7 and 27 and recognizes a command for data rewriting ( Step X4).

(5) Next, the control CPU 3 of the electronic control unit 1 reads the options of the DPRAMs 7 and 27 and obtains options such as a changed address and the number of data (step X5).

(6) The control CPU 3 reads the data of the data area in the command block of the DPRAMs 7 and 27 based on the read options and writes them to the data of the designated address on the emulation RAM 5 to read the ROM. Data is rewritten (steps X6 and X7). At this time, the current load of the control CPU 3 (for example, if the control target of the electronic control unit 1 is an engine, the engine speed stored in its RAM) is read and can be changed from the load of the control CPU 3. Read the number of data. The relationship between the load on the control CPU 3 (engine speed and the like) and the number of data that can be changed is set such that the number of data changes decreases as the load on the control CPU 3 increases, as shown in FIG. Thus, even if the number of changed data increases, the processing in the electronic control unit 1 is not delayed.

(7) After the processing of (4) to (6) above, the control CPU 3 sends the status (processing result) to the DPRAM.
Write to the status area in the command blocks 7 and 27. At this time, for example, each code is changed between when the processing ends in a normal state and when the processing ends in an abnormal state (error code) (step X8).

(8) The control CPU 3 uses DPRAMs 7 and 27
To the command status code in the status area of the status block.

(9) The control CPU 3 controls the DPRAMs 7 and 27
Of the command check counter of the status area in the status block of (1).

(10) The control CPU 3 writes a predetermined data value in the interrupt code area in the status block of the DPRAMs 7 and 27 in order to notify the personal computer 30 of the end of the command. Because of this, DPRAM
An interrupt signal is output to the personal computer 30 from 7, 27 (step X9).

(11) The personal computer 30 has the DPRAM
After receiving the interrupt signals from the interrupt cables 7 and 27 through the interrupt cable 35, the command check counter and the monitor check counter of the DPRAMs 7 and 27 are read to determine which processing of the command system or the monitor system is to be performed.

(12) The following processes (12) to (15) are for the case where the above determination is a command-based process, and the personal computer 30
The command processing code is determined by reading the status code in the status area in the status blocks M7 and M27. Also, the number of changed data N on the personal computer 30 side
t is compared with the change data Ne on the electronic control unit 1 side, the remaining data number and the start address are obtained from the change data number in the electronic control unit 1 until Nt> Ne, and then the processing (1 ) To (9) are repeated (step X
10 to X13).

(13) The personal computer 30 reads the status in the status area in the command block, and determines whether the operation is completed normally or abnormally.

(14) The personal computer 30 writes an unprocessed code in the command code area of the command block.

(15) Finally, the personal computer 30 reads the interrupt code in the interrupt area in the status block and clears the interrupt signal.

In response to such ROM emulation, a label name, label type, data length, physical quantity conversion formula, effective grid corresponding to the address of the ROM data are previously stored in a predetermined storage unit (not shown) in the personal computer 30. Emulation information such as numbers is provided.

The details of the emulation information are as exemplified in Table 1.

[Table 1]

That is, the type of emulation information is represented by a label type, and constants, tables, maps, and the like are distinguished by the label type. A label name is given to the emulation information, and an address address is shown for a constant, and a head address is shown for a table or a map. The length of the target data is represented by a byte length, a word length, or the like.

Since the numerical values to be subjected to ROM emulation are basically hexadecimal numbers on a computer, a physical quantity conversion formula for converting the numerical values into meaningful physical quantities is specified. LSB in this conversion formula is a basic physical quantity per bit, and offset represents a physical quantity corresponding to 0 in hexadecimal. Therefore, there is a numerical value having a word length of, for example, “4a00” in hexadecimal and “LSB”.
= 0.1, offset = 10 ”, the corresponding physical quantity is calculated as follows.

Conversion from hexadecimal to decimal: 4a00 → 18944 Conversion of physical quantity: 18944 × 0.1 + 10 = 1904.4 Further, a one-dimensional or two-dimensional axis data range of a table or a map is represented as an effective grid number. ing.

At the time of ROM emulation, when a label name is inputted by the operator from the input device 32 of the personal computer 30 of the controller 22, information corresponding to the input label name is retrieved from a plurality of emulation information. The emulation screen and the cursor position are optimally set on the display 33 of the personal computer 30 according to any one of the information constant, the table, and the map.

Specifically, FIG. 7 shows an emulation settable area screen related to constants (label name “KEENG” in the example shown in Table 1) shown on the display 33 of the personal computer 30. And the cursor C
When you move, the address is automatically moved.

FIG. 8 exemplifies the case of a table (the label name “TDENG” in the example shown in Table 1). The emulation-settable area is changed according to the number of effective grids (10 in the example shown). C is moved to the table head address.

Further, FIG. 9 illustrates the case of a map (label name “MDENG” in the example shown in Table 1), and the emulation-settable area is changed according to the number of effective grids (8 × 5 in the example shown). Then, the cursor C is moved to the map start address. In this way, an automatic search for an address based on a designated label, automatic movement to an emulation address, and automatic adjustment of an emulation settable area are performed.

Incidentally, even when a RAM monitor described later is performed, it can be displayed on the screen of the display 33 using the above-described emulation information.

(RAM Monitor) In order to perform the RAM monitor, a monitor service routine as a communication program and a start-up routine thereof are provided in the control CPU 3 of the electronic control unit 1. In the monitor service routine, the following processing operation is performed as shown in FIG.

That is, in the first step T1, the DPRA
A monitor switch for determining whether to start or stop monitoring (whether or not to send information) is read in the monitor setting area of the monitor block of M7, M27, and it is determined in next step T2 whether the monitor switch is ON. I do. When the determination is NO, that is, when the monitor is in the stopped state, the process ends as it is. When the determination is YES, the process proceeds to step T3 to set the number N of monitor channels.
In step T5, the upper, middle, and lower monitor addresses for n channels are set to DPRAM7,
27 from the monitor address area. Step T
In step 6, upper data of n channels is written in the monitor data areas of the DPRAMs 7 and 27, and in step T7, lower data of n channels is written. In step T8, the channel number counter n is decremented to n-1.

Thereafter, in step T9, it is determined whether or not all the n channels have been completed and n ≦ 0. When this determination is NO, the process returns to step T5,
Steps T5 to T8 are repeated. Therefore, step T5
T9 is repeated by the number of channels n.

Then, when all of the n channels are completed and n ≦
When the value becomes 0, the basic monitoring process ends, and the process proceeds to post-processing. First, in step T10, the DPRAMs 7, 2
The monitor status (for example, the number of monitor channels in a normal state, and a predetermined code in an abnormal state) is written in a status area of the status block 7. Next, in step T11, a monitor status code is written in the status area, and in step T12, the monitor check counter in the status area is incremented. This confirms the execution of the monitoring process. Then, in step T13, the monitor interrupt identification code in the interrupt area is written with a predetermined code, and in step T14, the interrupt code is written, and the process ends.

On the other hand, in the start routine of the monitor service routine, the following processing operation is performed as shown in FIGS. FIG. 11 shows a case where time synchronization processing is performed.
At step U1, a normal control process is performed. Next step U2
It is determined whether the timing of the monitor processing has come. If the determination is NO, the monitor service routine (see FIG. 10) is executed in step U3 as it is, and the process proceeds to step U4.
In this step U4, it is determined whether or not the command processing timing has come. When the determination is NO, the command service routine (see FIG. 3) is processed as it is.

FIG. 12 shows a case in which an interrupt process is started, and a normal control process is performed in step V1. In the next step V2, it is determined whether or not the timing of the monitor processing has come. When the determination is NO, the monitor service routine (see FIG. 10) is executed in step V3, and the process is terminated.

The RAM monitor is performed in the following order. Basically, a so-called soft handshake is performed while confirming data transmission and reception between the analysis CPU of the personal computer 30 and the control CPU 3 of the electronic control unit 1. It is a method. The processing order for the DPRAMs 7 and 27 is indicated by numbers in FIG.

(1) First, the personal computer 30 sets the monitor cycle data / trigger, address setting mode switch, page,
A monitor command such as a monitor address, the number of channels, and a monitor switch is output and written in a data area in a command block of the DPRAMs 7 and 27 (monitor condition setting write).

(2) Control CPU 3 of electronic control unit 1
Receives the monitor command and receives the DPRAMs 7 and 2
The value of the data area in the command block of No. 7 is read.

(3) The control CPU 3 has the DPRAMs 7 and 2
The setting value is written in the monitor setting area corresponding to the command in the monitor block 7.

(4) The control CPU 3 uses the monitor service routine startup program (see FIG. 11 or 12) to execute the DP.
The monitor setting values are read from the RAMs 7 and 27, and the monitor service routine (see FIG. 10) is started.

(5) The control CPU 3 reads the monitor address in the monitor address area of the DPRAMs 7 and 27 by the monitor service routine.

(6) Next, the control CPU 3 converts the monitor data into DPRAMs 7 and 2 based on the monitor address.
7 is repeatedly written in the monitor data area by the number of channels.

(7) The control CPU 3 controls the DPRAMs 7 and 2
A predetermined status (for example, a monitor data transmission code at the time of normal end, a monitor data error code at the time of abnormal end)
Write.

(8) The control CPU 3 is the DPRAM 7, 27
Write the next monitor status code to the status area in the status block.

(9) The control CPU 3 is the DPRAM 7, 27
The monitor check counter in the status area in the status block of (1) is incremented.

(10) The control CPU 3 transmits the DPRAMs 7 and 27 to the personal computer 30 to notify the end of the monitoring process.
A predetermined data value is written to the interrupt code area in the status block of (1). This allows DPRA
An interrupt signal is output to the personal computer 30 from M7 and M27.

(11) The personal computer 30 has the DPRAM
After receiving the interrupt signals from the interrupt cables 7 and 27 through the interrupt cable 35, the command check counter and the monitor check counter of the DPRAMs 7 and 27 are read to determine which processing of the command system or the monitor system is to be performed.

(12) The personal computer 30 has the DPRAMs 7 and 27
The status code of the status area in the status block is read to obtain the monitor processing code.

(13) The personal computer 30 performs processing (such as acquisition of monitor data) based on the processing code of the status area in the command block.

(14) Finally, the personal computer 30 reads the interrupt code in the interrupt area of the status block and clears the interrupt signal. Thus, one sampling is completed, and the above processes (4) to (14) are repeated until the monitor switch is turned off.

The above ROM emulation and RA
Table 2 summarizes the M monitor method.

[0107]

[Table 2]

In the control CPU 3 of the electronic control unit 1, the command service routine (see FIG. 3) and the monitor service routine (see FIG. 10) operate asynchronously.
Occurs within the interrupt processing time of the
The interrupt processing on the 0 side cannot be performed in time, an error occurs, and there is a concern that monitor data may be missed. Therefore, the processing operation on the personal computer 30 side when an interrupt signal (Lo level in this embodiment) is generated from the control CPU 3 of the electronic control unit 1 will be described with reference to FIG. 14 (ROM emulation processing sequence (11) and Processing order of RAM monitor (11)).

(1) First, when an interrupt signal is received from the DPRAMs 7 and 27 via the interrupt cable 35, the value of the command check counter in the status area in the status block of the DPRAMs 7 and 27 is read and compared with the previous counter value. .

(2) The value of the monitor check counter in the status area is read and compared with the previous counter value.

(3) It is checked which counter value of the command system or the monitor system has been updated, and interrupt processing of the updated system is started.

(4) When the counter value of both the command and the monitor has been updated, the monitor-based interrupt processing is performed with priority, and the command-based interrupt processing is not performed.

More specifically, in the state of FIG. 14A, only the command check counter is updated, so that the command-related interrupt processing is updated, and in the state of FIG. 14B, only the monitor check counter is updated. Therefore, interrupt processing of the monitor system is performed. In the state of FIG. 14C, since both the command check counter and the monitor check counter have been updated, only the interrupt processing of the monitor system is performed and the processing of the command system is not performed. This unprocessed command processing is performed after the monitor processing interrupt processing is completed.

(Tool Failure Diagnosis) In this embodiment, the processing operation when diagnosing a tool failure from the personal computer 30 (performed as needed) is shown in FIG.
5 will be described.

In the flowchart shown in FIG. 15, first, at step W1, a diagnosis of the entire apparatus is performed.
In step 2, it is determined whether or not there is a failure. Specifically, data corresponding to all addresses corresponding to the capacity of the DPRAMs 7 and 27 is transmitted to the electronic control unit 1 via the relay box 13 from the personal computer 30 of the controller 22 as a starting point. The electronic control unit 1 receiving this data transmits the same received data to the personal computer 30, and the personal computer 30 receives the data via the relay box 13. Then, the transmission data and the reception data are compared in the personal computer 30, and if the contents of the two data are different, it is determined that a failure has occurred.

When the determination in step W2 is NO, it is determined in step W13 that the state is normal, and the processing is terminated.
In the case of, the fault location is specified in the following steps W3 to W12. That is, at step W3, the personal computer 30 and the I / O
Diagnosis of a failure with the DPRAM 27 of the F box 23 is performed, and it is determined in step W4 whether or not there is a failure. Specifically, after the personal computer 30 writes the diagnostic data (a value that can confirm all bits) to all the addresses of the DPRAM 27, the PC 30 reads the value of the DPRAM 27 and compares it with the written value. Then, when the two values are different, it is determined that there is a failure between the personal computer 30 and the DPRAM 27 of the I / F box 23 (writing failure or contact failure to the DPRAM 27).

When the determination in step W4 is YES,
In step W14, the failure determination is made after the code is sent to the personal computer 30. If NO, the failure diagnosis between the DPRAM 27 of the I / F box 23 and the communication CPU 26 of the box 23 is performed in step W5. This is performed by the handshake method, and it is determined in step W6 whether there is a failure. The specific operation is as shown in FIG. 16, and FIG. 16A shows the personal computer 30 side, and FIG. 16B shows the communication CPU 26.
First, in the personal computer 30, as shown in FIG. 16A, a diagnostic command is sent to the communication CPU 26 in step W51, and a diagnostic command is issued to the I / F box 23. Next, in step W52, the I / F box 2
3 from the communication CPU 26 (step W56).
) Is waited for a certain period of time, and if there is no signal, the process proceeds to step W55 to determine that the communication CPU 26 has failed. When there is a transmission signal from the communication CPU 26, the process proceeds to step W53, and waits for a predetermined time for the end command (see step W58) from the communication CPU 26 of the I / F box 23. When there is no signal, the process proceeds to step W55. Is judged as failure. On the other hand, for communication C
When there is an end command from PU 26, step W54
To determine the failure of the communication CPU 26 based on the determination data sent from the I / F box 23, and this determination is NO
In the case of, the process proceeds to step W55 to determine that a failure has occurred,
While the code is sent to the personal computer 30, the process ends when the answer is YES.

On the other hand, as shown in FIG.
The communication CPU 26 of the I / F box 23 responds to the diagnostic command for transmitting the reception confirmation signal of the signal transmitted from the personal computer 30 (see step W51) to the personal computer 30 in the first step W56, and then returns to step W57. Then, the fault diagnosis is started by the method of step W3 in FIG. 15, and in the next step W58, the end command and the judgment data are transmitted to the personal computer 30, and thereafter the process is ended.

Thus, the DP of the I / F box 23
After performing the failure diagnosis between the RAM 27 and the communication CPU 26, the process proceeds to step W7 in FIG.
3 and the communication CP of the relay box 13
Diagnosis of a failure including the serial communication cable 20 with the U16 is performed, and it is determined in step W6 whether or not there is a failure. Specifically, steps W5 and W6 (FIG. 1)
6), a handshake method is used in which both communication CPUs 16 and 26 confirm communication each time.
The RAM (not shown) in the communication CPU 16 of the relay box 13 is checked for all address areas in the same manner as in step W3 shown in FIG. 15, while the ROM (not shown) is checked for a communication error. .

If the determination in step W8 is YES, the flow proceeds to step W14 to make a failure determination, while if the determination is NO, the flow proceeds to step W9, and this time the communication CPU 16 of the relay box 13 and the evaluation board of the electronic control unit 1 2, a fault diagnosis is performed in a range including the parallel communication cables 12, 12,.
In step W10, it is determined whether or not there is a failure. Specifically, this is performed in the same manner as in step W7, and the DPRA
The diagnosis of M7 is performed in the same manner as in step W3. The diagnosis at this time is the communication CPU 16 of the relay box 13,
The diagnostic data in the RAM 7 is held by the communication CPU 16.

When the determination in step W10 is YES, the process proceeds to step W14, but when the determination is NO, the process proceeds to step W11, where the DPRAM in the electronic control unit 1
A failure diagnosis is made between the control CPU 7 and the control CPU 3, and it is determined in step W12 whether or not there is a failure. This determination is performed in the same manner as in step W7, and the diagnosis of the DPRAM 7 is performed in the same manner as in step W3. The diagnosis at this time is performed by the control CPU 3 on the evaluation board 2, and the control data of the DPRAM 7 is held by the control CPU 3.

Further, the diagnosis in steps W11 and W12 allows not only the connection between the control CPU 3 and the DPRAM 7 but also the
A fault diagnosis between the control CPU 3 and the emulation RAM 5 is performed. Further, by switching the memory switching unit 6 by the control CPU 3, a failure check of the memory switching unit 6 can be performed.

When the determination in step W12 is YES, the process proceeds to step W14, and when the determination is NO, the process proceeds to step W13, and thereafter ends.

Next, the processing operation of the above embodiment will be described. ROM emulation for rewriting the control data of the program ROM 4 of the electronic control unit 1 by the personal computer 30 of the controller 22 or data of RAM built in the control CPU 3 The basic operation when performing the RAM monitoring monitored at 30 is as follows.

First, various commands are displayed on the screen of the display 33 of the personal computer 30, and after rewriting these data, the analysis (monitoring) C of the personal computer 30 is performed.
An interrupt signal is generated by the PU, and a predetermined command is transmitted from the analysis CPU to the electronic control unit 1. That is, the analysis CPU sets the D in the I / F box 23
When the PRAM 27 is accessed from one port and a command code is written in a predetermined command area, and finally, when predetermined data is input to the interrupt code of the DPRAM 27, an interrupt signal is generated from the DPRAM 27 and the interrupt signal is used for the interrupt. I / F box 23 and relay box 1 via cable 35
3 is transmitted to the communication CPUs 26 and 16. Upon receiving the interrupt signal, the communication CPUs 26 and 16 communicate with the I / O
The DPRAM 27 of the F-box 23 is accessed from the other port to read out the command code area, and the data is directly used as the evaluation board 2 of the electronic control unit 1.
Is written in the command area of the DPRAM 7 at the time of. In the same manner as described above, finally, predetermined data is entered in the interrupt code of the DPRAM 7, and this
7 generates an interrupt signal and issues an interrupt command to the control CPU 3. Upon receiving the interrupt signal, the control CPU 3 accesses the DPRAM 7 at a predetermined time, reads the written command code, recognizes the type of the command, and when the original control is not performed, Execute the recognized command.

On the other hand, after execution of the above command, the control C
The PU 3 accesses the DPRAM 7 again, writes the command code, and generates an interrupt signal from the DPRAM 7 by writing data to the interrupt code. This interrupt signal is transmitted to the communication CPUs 16 and 26 via the interrupt cable 35,
The I / F box 23 is controlled by the communication CPUs 16 and 26.
In the area of the DPRAM 27. Thereafter, when the analysis CPU of the personal computer 30 accesses the DPRAM 27, the execution result of the command is transmitted to the personal computer 30 through a route reverse to the above, whereby the electronic control unit 1 receives the command from the personal computer 30. Is identified by

In this embodiment, the following effects can be obtained. When data is exchanged between the electronic control unit 1 and the DPRAMs 7 and 27 of the I / F box 23, the data in the DPRAMs 7 and 27 are converted from parallel signals to serial signals by the communication CPUs 16 and 26. That is, for example, when the electronic control unit 1 is accessed from the personal computer 30 for ROM emulation of the electronic control unit 1, a signal from the personal computer 30 is transmitted to the communication CPU 2 of the I / F box 23.
After being converted into a serial signal by the serial communication cable 6, the communication CPU 16 of the relay box 13
After the communication CPU 16 returns the signal to the original parallel signal, the parallel communication cables 12, 12,
Are accessed to the DPRAM 7 of the electronic control unit 1. On the other hand, on the other hand, the DPRAM of the electronic control unit 1
7 are accessed by the communication CPU 16 of the relay box 13 via the parallel communication cables 12, 12,..., And are converted into serial signals by the communication CPU 16;
The signal is transmitted to the communication CPU 26 of the I / F box 23 through 0, where it is restored to the original parallel signal, and then the personal computer 30 is accessed.

At this time, the serial communication section including the serial communication cable 20 connects between the relay box 13 and the I / F box 23 of the controller 22, and connects between the relay box 13 and the evaluation board 2 of the electronic control unit 1. Are connected by a parallel communication unit including the parallel communication cables 12, 12,..., The portion connected by the serial communication unit is more susceptible to noise due to the influence between the lines and external noise than the connection unit by the parallel communication unit. Noise is less likely to ride, and the noise resistance of the device can be improved as a whole.

Further, since the length of the serial communication cable 20 of the serial communication unit is longer than the length of each parallel communication cable 12 of the parallel communication unit, the portion where external noise is difficult to ride becomes longer, while the portion where noise is easy to mount. And the noise resistance of the tool can be further improved.

Also, the control CPU of the electronic control unit 1
In the third embodiment, it is not necessary to provide a program for ROM emulation in order to increase the speed of the electronic control unit, and only the programs of the relay box 13 and the controller 22 need to be changed separately.
Speed can be increased while reducing the load on the control CPU 3.

Further, the DPRA is installed in the electronic control unit 1.
M7 is provided, and communication between the control CPU 3 of the electronic control unit 1 and the communication CPU 16 of the relay box 13 is performed via the DPRAM 7, so that the communication CPU 16 of the relay box 13 1 is not directly accessed, the communication CPU 16 accesses the DPRAM 7, and the control CPU 3 accesses the DPRAM 7 as necessary when the original control is not performed. The emulation and the RAM monitor may be performed, and the control load of the control CPU 3 is reduced by that amount to reduce the electronic control unit 1.
Controllability can be improved, and the speeding-up can be favorably achieved.

Conversely, the relay box 13 and the controller 22 may be connected by a parallel communication unit, and the relay box 13 and the electronic control unit 1 may be connected by a serial communication unit. It is possible to achieve the same effect. However, the communication CPU
16 are required for the electronic control unit 1, and the cost of the electronic control unit 1 itself increases. In this embodiment, as described above, the relay box 13 and the I / F box 2
3 and the relay box 1
By connecting each of the electronic control unit 3 and the electronic control unit 1 by a parallel communication unit, the above effects can be obtained without increasing the cost.

Further, the data analysis CP of the personal computer 30 is used.
Between the U and the control CPU 3 of the electronic control unit 1
A pair of DPRAMs 7 and 27 and communication CPUs 16 and 26
Are connected, as described in the processing operation of the failure diagnosis of the tool, the connected DPRAM 7,
27, it is only necessary to monitor the exchange of data among the communication CPUs 16 and 26, the control CPU 3 and the data analysis CPU, and it is possible to clearly identify a faulty part by looking at a portion where data transfer is defective. In other words, it is possible to clarify the failure location of the device and improve the maintainability and work efficiency while improving the noise resistance of the tool and the speeding up of the electronic control unit 1.

Since the electronic control unit 1 is provided with the emulation RAM 5 accessible to the control CPU 3, the control CPU 3
ROM emulation for accessing the emulation RAM 5 and rewriting the control data when the original control is unnecessary is sufficient, and the access time can be shortened. Even if the speed of the control CPU 3 is increased, the problem of the access time to the emulation RAM 5 is reduced. It will disappear and you will be able to access it properly. For this reason, on the tool side, even if the speed of the control CPU 3 is increased, the ROM emulation can be performed as it is, and the tool can be used for a long time in terms of control data. Control CPU
3, the control load can be further reduced, and the speed can be further increased.

Further, the emulation RAM 5 controls C
Since the emulation RAM 5 is provided in the electronic control unit 1 integrally with the PU, the emulation RAM 5 corresponds to the control speed of the control CPU 3.
The original control is not hindered, and the speeding up of the control CPU 3 can be easily achieved.

Further, since the unit-side DPRAM 7 is provided in the electronic control unit 1, it is hardly affected by external noise at the time of ROM emulation, and the noise resistance can be improved.

When the control data of the emulation RAM 5 is changed at the time of ROM emulation, the memory switching section 6 temporarily controls the control CPU 3 during the ROM emulation.
Are connected from the emulation RAM 5 to the program ROM 4, and the control of the control target of the control CPU 3 is performed based on the control data of the program ROM 4. Therefore, the control target is the emulation RAM 5
Thus, the control is not performed based on the uncertain control data being changed, and appropriate control can be performed even in the ROM emulation state.

During the ROM emulation, a predetermined code is written in the option areas of the DPRAMs 7 and 27 prior to the change command for changing the control data of the program ROM 4. Is read and the control data is rewritten based on the code,
The writing of data from the personal computer 30 to the DPRAMs 7 and 27 and the reading of data from the DPRAMs 7 and 27 by the control CPU 3 can be performed in a concentrated manner, which facilitates writing and reading, and speeds up rewriting of control data. Can be done.

On the other hand, at the time of ROM emulation or RAM
During monitoring, the control CPU 3 transfers the data to DPRA.
After writing to the data area of M7, 27, DPRA
The check data of M7, 27 is updated, and then D
An interrupt code is written in the PRAMs 7 and 27,
Analysis CPU from the PCRAM 30 to the DPRAM 7, 27
When the interrupt signal is sent to the CPU, the update data of the command check data and the monitor check data of the DPRAMs 7 and 27 are read by the analysis CPU which has received the interrupt signal, and any processing of the command system or the monitor system is performed. It is determined whether to perform. Thereafter, the processing data in the DPRAMs 7 and 27 is read by the analysis CPU. Specifically, the control CPU 3
A command counter or a monitor check counter is incremented as each check data of the DPRAMs 7 and 27, while an analysis C receiving an interrupt signal is used.
The PU determines whether to perform command-based processing or monitor-based processing based on the check counters in the DPRAMs 7 and 27.

The DPRA by such a control CPU 3
The update between the M7 and M27 check data and the analysis CPU reads the update data of the same check data to determine the processing accompanying the interrupt in a software manner, thereby providing an interrupt between the DPRAMs 7 and 27 and each CPU. Circuit is required for one channel, and the circuit configuration can be simplified and the cost can be reduced accordingly. In addition, by determining which process should be performed based on the increase in the values of both check counters, both processes can be easily identified on a program.

A DPRAM based on an interrupt signal
When it is determined that the check data 7 and 27 perform both the command system and the monitor system, the monitor system process is performed with priority. As a result, there is no time-series dropout of monitor data as in the case where command-based processing is prioritized, and it is possible to monitor the ever-changing RAM data without omission and obtain data with no deviation in analysis. Can be.

As for the DPRAMs 7 and 27, since the DPRAMs 7 and 27 are divided into at least a command block, a monitor block, and a status block, blocks for writing and reading codes are determined in advance. Can be easily performed.

The command block is divided into a command area, an option area, a data area and a status area, the monitor block is divided into a monitor setting area, a monitor address area and a monitor data area, and the status block is further divided into a status area and an interrupt area. Therefore, similarly to the above, code writing and reading processing can be easily performed.

Further, the emulation information corresponding to the address of each data in the ROM or RAM of the electronic control unit 1 is stored in advance in the storage unit in the personal computer 30.
When a label name is input to the personal computer 30 from the external input device 32 during AM monitoring, data of an address corresponding to the input label name is displayed on the display 33 of the personal computer 30 based on the emulation information in the storage unit. . That is, when a label name is input to the personal computer 30, the personal computer 30 converts the data of the address corresponding to the input label name from hexadecimal to decimal,
And it is converted into a physical quantity from the conversion formula of the physical quantity conversion file. Thereafter, as shown in FIGS. 7 to 9, the number of effective vertical and horizontal grids displayed on the display 33 is adjusted in accordance with the input label name. Then, at the time of ROM emulation, the data in the emulation RAM 5 may be rewritten and changed based on the data displayed on the display 33. Therefore, by giving such emulation information to the personal computer 30, it is possible to easily perform data address search, address movement, and the like.

Also, since the number of vertical and horizontal effective grids displayed on the display 33 is adjusted in accordance with the input label name, a display form corresponding to, for example, the format of the specification is obtained on the display 33. The screen display that matches the level makes it easier to see, and the work efficiency can be further improved.

Further, the data of the address corresponding to the input label name input to the personal computer 30 is converted from hexadecimal to decimal and converted into a physical quantity from the conversion formula of the physical quantity conversion file, and then displayed on the display 33. Therefore, a meaningful actual physical quantity is displayed on the display 33, which is more advantageous in improving work efficiency.

[0147]

As described above, according to the first aspect of the present invention, the RA of the electronic control unit for controlling a control target such as an electronically controlled fuel injection engine or a transmission.
When M data is externally monitored by a controller, a DPRAM that is accessible from both the controller monitoring CPU and the electronic control unit control CPU is provided between the controller and the electronic control unit.
A monitor condition is set for this DPRAM from the controller side, and the monitor condition is read by the control CPU. The monitor address of the DPRAM is read by the control CPU in a monitor service routine.
After you write the data to the data area of the DPRAM, D
Monitor check data of PRAM monitor check
Updated by incrementing the counter and DPRA
Write the interrupt code to M and copy it from DPRAM.
Sends an interrupt signal to the monitoring CPU on the controller side.
To the monitor CPU based on this interrupt signal.
Update data of DPRAM monitor check data
When the interrupt signal is received, the above DP
Electronic control based on the RAM monitor check counter
Related to commands issued by the controller to the
Command system or RAM data in the control CPU
It is determined which process of the monitor system is to be performed, and this determination is made.
According to the result, the monitor CPU sets the control C in the DPRAM.
By reading the RAM data of PU ,
The control CPU can freely access the DPRAM to read and write data at a timing when the original control is not performed.
Tomo When it is possible to facilitate the monitoring of the AM data
In addition, the processing for updating the monitor check data of the DPRAM and the processing associated with the interrupt are determined by software, and the DP
An interrupt circuit between the RAM and each CPU can be made up of one channel, and cost can be reduced by simplifying the circuit configuration and the like. Further, the monitor check counter is incremented as the monitor check data of the DPRAM, and the monitor CPU determines whether to execute a command system or a monitor system based on the monitor check counter of the DPRAM, It is possible to easily identify the processing of the command system or the monitor system.

[0148]

[0149]

According to the second aspect of the present invention, when it is determined that the monitor check data of the DPRAM performs both the command system and the monitor system, the monitor system data is given priority to perform the RAM system data. By monitoring without leakage in time series, it is possible to reliably obtain good data with no deviation in analysis.

[0151]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an electronic control unit according to an embodiment of the present invention and a tool for performing ROM emulation and RAM monitoring thereof.

FIG. 2 is an explanatory diagram showing each block and its area in a DPRAM.

FIG. 3 is a flowchart illustrating a command service routine.

FIG. 4 is an explanatory diagram showing the order of processing operations on a DPRAM during ROM emulation.

FIG. 5 is a flowchart illustrating a processing operation of ROM emulation.

FIG. 6 is a characteristic diagram showing a relationship between a load on a control CPU during ROM emulation and the number of data that can be changed in an emulation RAM.

FIG. 7 is a diagram exemplifying an emulation setting area screen relating to constants;

FIG. 8 is a diagram exemplifying an emulation setting area screen regarding a table.

FIG. 9 is a diagram exemplifying an emulation setting area screen relating to a map.

FIG. 10 is a flowchart illustrating a monitor service routine.

FIG. 11 is a flowchart illustrating an activation routine of a monitor service routine.

FIG. 12 is a diagram corresponding to FIG. 11, showing another example of a startup routine of the monitor service routine.

FIG. 13 is an explanatory diagram showing the order of processing operations on the DPRAM during RAM monitoring.

FIG. 14 is a time chart of an interrupt processing operation on the personal computer side.

FIG. 15 is a flowchart showing an overall processing operation for failure determination.

FIG. 16 is a flowchart showing a failure determination operation between the DPRAM of the control box and the communication CPU.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 electronic control unit 2 evaluation board 3 control CPU 4 program ROM (ROM) 5 emulation RAM 6 memory switching unit 7 unit side DPRAM 12 parallel communication cable 13 relay box 16 communication CPU 20 serial communication cable 22 controller 23 I / F box 26 Communication CPU 27 DPRAM 30 Personal computer 31 Personal computer main body 32 External input device 33 Display 35 Interrupt cable

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Teruaki Tanioka 3-1 Shinchi, Fuchu-cho, Aki-gun, Hiroshima Prefecture Inside Mazda Co., Ltd. (72) Toshihiro Ishihara 3-1 Shinchi, Fuchu-cho, Aki-gun, Hiroshima Mazda (56) References JP-A-2-196347 (JP, A) JP-A-6-290075 (JP, A) JP-A-1-172150 (JP, U) (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 11/22-11/34

Claims (2)

(57) [Claims] An electronic control unit for controlling a predetermined control target by a control CPU, wherein the control data stored in a RAM in the control CPU is monitored by a controller having a monitor CPU. Wherein the DPRA is accessible from both the monitoring CPU of the controller and the control CPU of the electronic control unit.
M, and a CPU for monitoring the controller with respect to the DPRAM.
Sets a monitor condition including at least a monitor cycle, a monitor address, and a monitor command. The control CPU reads the monitor condition of the DPRAM and starts a monitor service routine. The control CPU executes the DP by the monitor service routine.
Reads the monitor address of RAM, after you write the RAM data of the control CPU based on the monitoring address in the data area of the DPRAM, the control CPU is the monitor check data of the DPRAM
Updated by incrementing the monitor check counter
And, then, control for the CPU interrupt code to DPRAM
Write the code and monitor from DPRAM to the controller side
An interrupt signal is sent to the CPU for monitoring, and the monitoring CPU on the controller side sends the interrupt signal.
Update of the DPRAM monitor check data based on the
When new data is read and an interrupt signal is received
Based on the DPRAM monitor check counter
Command issued by the controller to the electronic control unit.
Performs command-related processing related to commands or controls
Whether to perform monitor processing related to RAM data in the CPU
Determines, based controller side of the monitoring CPU is in the determination result
And reading the RAM data of the control CPU in the DPRAM . 2. A predetermined control target is controlled by a control CPU.
In the control CPU in the electronic control unit that controls
The control data stored in the RAM is
Of the electronic control unit monitored by the
And have you to monitor process, monitoring CPU and the electronic control Uni the controller
DPRA accessible from both control CPUs
M, and a CPU for monitoring the controller with respect to the DPRAM.
Are at least the monitor cycle, monitor address,
And the control CPU reads the monitor conditions of the DPRAM.
To start the monitor service routine, and the control CPU
Reads the monitor address of the RAM and reads the monitor address.
RAM data of the control CPU based on the
After writing to the data area, the control CPU transfers the DPRAM monitor check data.
Update, and then the control CPU
Write the code and monitor from DPRAM to the controller side
An interrupt signal is sent to the CPU for monitoring, and the monitoring CPU on the controller side sends the interrupt signal.
Update of the DPRAM monitor check data based on the
Read the new data and control the electronic control unit.
Performs command-related processing for the command issued by the roller.
Or monitor for RAM data in the control CPU.
It is determined whether or not to perform data processing, and the monitoring CPU on the controller side is based on the above determination result.
DPRAM read based on the interrupt signal
The monitor check data of the above command and monitor
When it is determined that both processes of the
Control within the DPRAM so that system processing is performed with priority
A method of monitoring an electronic control unit, comprising reading RAM data of a CPU for use .