JP3348328B2 - Viterbi decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding device for decoding a convolutional code, and more particularly, to a configuration of a path memory.

[0002]

2. Description of the Related Art For example, in satellite communication, a convolutional code is used, and Viterbi decoding is used for decoding.
Viterbi decoding estimates the code of the maximum likelihood sequence using a trellis diagram representing a state transition, and has a very large ability to correct random errors. In satellite communication, a convolutional code having a constraint length of about 7 is used, but for simplicity of description, a code with a constraint length of 3 will be described here.

FIG. 14 shows an example of an encoder that generates a convolutional code having a constraint length of 3. This encoder includes registers 102A and 102B constituting a two-stage shift register, and adders 103 to 105. That is,
The data from the input terminal 101 is supplied to the cascade connection of the registers 102A and 102B and the adder 103
And 104. Registers 102A and 102
The output between the B stages is supplied to the adder 103. The output of the register 102B is supplied to adders 104 and 105. The output of adders 104 and 105 is output terminal 106A.
And 106B.

The generator polynomial of this encoder is given by G ₁₁ = 1 + D ² G ₁₂ = 1 + D + D ² . These shift registers 102A and 102B
Is represented by a state transition diagram as shown in FIG. In this figure, the symbol 1/11 means that when the input is 1, it outputs 11 and transitions like this branch. There are four states that can be set by the cyst registers 102A and 102B: (00), (01), (10), and (00).

[0005] From the above state transition diagram, a trellis diagram as shown in FIG. 16 can be drawn. In this figure, solid-line branches indicate transitions due to input 0, and dashed-line branches indicate transitions due to input 1. The numbers written along the branch are the output when the transition of that branch occurs. For example, state (00)
Then, the next state is either (00) or (01),
If the input code is "0", it is (00), and if it is "1", it is (01). If the state is (01), the next state is (1)
0) or (11). If the input code is "0", it is (10), and if the input code is "1", it is (11). As described above, there are always two types of paths that transit to each state.

[0006] Viterbi decoding estimates the code of the maximum likelihood sequence using such a trellis diagram. That is, there are two routes to each state. In Viterbi decoding, a path with a high likelihood is selected from these two paths as a surviving path. By selecting a path with a high likelihood as a surviving path in this way, data is decoded.

Normally, a Viterbi decoder is composed of a branch metric operation circuit, an ACS circuit, a path memory, and a decision circuit. The branch metric calculation circuit is for calculating the distance between the reception data and the reception data candidate. The ACS circuit adds the past state metric and the branch metric of the two paths to obtain the current 2
Adder for calculating the metric of one path and 2 for the metric
It comprises a comparator for comparing the metrics of two paths, and a selector for selecting a path with a high likelihood from the output of this comparator. The path memory stores the surviving path in each state. The determination circuit performs the maximum likelihood determination of the output of the path memory in each state.

[0008]

In the above example, a code with a constraint length of 3 has been described for the sake of simplicity. However, in satellite communication, a convolutional code with a constraint length of about 7 is used. When the constraint length is 3, the number of states is 4, and when the constraint length is 7, the number of states is 64. In satellite communication, a high-speed operation of 50 to 60 MHz is required. Furthermore, when the coding rate is set to 7/8 using punctured codes, about 100 stages of path memories for storing surviving paths are required. For this reason, the conventional Viterbi decoder has a problem that the power consumption of the path memory increases.

FIG. 17 shows the structure of a conventional path memory cell. In FIG. 17, 111 is a two-input selector, and 112 is a D flip-flop.
Data is supplied from an input terminal 121 to an A input terminal of the selector 111. Data is supplied from an input terminal 122 to the B input terminal of the selector 111. Selector 111
Is connected to the input terminal 123 from the input terminal 123.
A select signal from the S circuit is supplied. Selector 1
The output of 11 is supplied to the D flip-flop 112.
A system clock is supplied from an input terminal 124 to a clock input terminal of the D flip-flop 112. The output of the D flip-flop 112 is taken out from the output terminal 125.

In the case of a code having a constraint length of 7 and the number of states is 64, these cells are arranged as shown in FIG. In this case, the number of flip-flops in the entire path memory is 700
As many as zero. Since all of them operate in synchronization with the system clock, the power consumption is enormous.
For this reason, even at a low voltage operation of 3.3 V, the power consumption becomes close to 2 W, which causes problems such as reliability of the element, package cost, and cooling in a mounted set.

As a countermeasure, an SST system and a four-pass memory system have been proposed. In the SST method, received data is simply decoded without error correction, convolutionally coded again, and a difference from the received data is obtained and input to a path memory. In this method, since data changes occur only in places where there is no difference, latch inversion in the path memory is reduced, and power consumption is reduced. However, the ratio of latch inversion to the total power consumption is about 20%, and the improvement effect by this method is small as a whole.

[0012] The four-pass alternative memory system is usually
When calculating a branch metric for a set of PSK-modulated I / Q reception data, two consecutive sets of I / Q are used.
The branch metric calculation is performed on the Q reception data. As a result, the likelihood calculation of the surviving path in the ACS is performed once every two system clocks, and accordingly, the path memory unit is also operated at twice the cycle of the system clock, thereby achieving low power consumption. is there. Although depending on the circuit configuration, the path memory occupies 60% or more of the power consumption, such as a transmission gate of a flip-flop, which operates in synchronization with the system clock, and thus this method is effective for reducing the power consumption. .

However, by reducing the likelihood calculation to twice every two times, the conventional calculation of four branch metric calculations for one received data is different from the calculation of 16 branch metrics for two received data. It becomes necessary to calculate a branch metric value. Further, in the ACS circuit, a conventional operation of obtaining two sets of the sum of the branch metric value and the state metric value, comparing the sums, and selecting one of them is performed. Four sets of metric values are obtained, and the minimum value is obtained. That is, the number of wirings and the circuit scale are doubled or more.

Further, in the conventional path memory, as described above, a memory cell is formed for each state. The connection of each memory cell becomes very complicated. Therefore, how the path memory cells are connected has a great influence on the chip size. As the chip size increases, the wiring capacity increases, leading to an increase in power consumption. Further, since a large number of flip-flops operate at the same time, it is necessary to sufficiently strengthen the power supply system.

Therefore, an object of the present invention is to provide a Viterbi decoding device capable of reducing power consumption by lowering the operating frequency of a path memory.

Another object of the present invention is to provide a Viterbi decoding device capable of performing optimum wiring, reducing the chip size, and reducing power consumption.

[0017]

According to the present invention, there is provided a branch metric operation circuit for obtaining a distance between received data and a candidate for received data, an adder for adding a branch metric and a state metric, and a comparator for comparing the metrics. consists and ACS circuit comprising a selector for selecting the survivor path from the metric, the path memory for storing the survivor path, and the number indicating the number of processing stages the N, M
Is the number indicating the number of states, and the constraint length is K, the Nth stage
State (M + 2 ^(k-2) ) and the (N +
1) The state (2M) and the state (2M + 1) at the stage
This is a Viterbi decoding device in which a path memory is configured from a path memory cell as a memory cell .

According to the present invention, the path memory cells have two half-period phases different from each other and operate with a clock having a half frequency of the system clock, and outputs of the two flip-flops are alternately distributed according to the system clock. Configure two elements consisting of selectors
So that that.

[0019]

The shift circuit in the path memory cell is replaced by two flip-flops operating at clocks having a half frequency of the system clock and different in half-period phase, and a selector for distributing the output of the flip-flop. , The operating frequency of the flip-flop of the path memory is set to 1
/ 2.

When a code with a constraint length of K is used, the state M and the state (M + 2 ^(K−2) ) of the N-th stage and the state (N + 1)
The state (2M) and the state (2M + 1) in the stage form a path memory cell. Further, the connection based on the trellis diagram between the path memories is performed by the first wiring layer, the selection signal of each path is performed by the second wiring layer, and in the region where the path memory cell circuit is formed. , The first and second wirings are substantially orthogonal. Thereby, the wiring of the path memory can be optimally performed.

[0021]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a Viterbi decoder to which the present invention can be applied. In FIG. 1, 1A
And 1B are input terminals. Input terminals 1A and 1B
Is supplied with received data.

The received signal is, for example, a demodulated output of data transmitted after being subjected to 1 / 4π shift QPSK modulation. The demodulated output of the I axis is supplied to the input terminal 1A, and the demodulated output of the Q axis is supplied to the input terminal 1B. The received data is encoded using, for example, a convolutional code having a constraint length of 7. As an encoder having the constraint length 7, for example, as shown in FIG. 2, a shift register 11, adders 12 and 13
The following is used.

In the case of a convolutional encoder having a constraint length of 7 as shown in FIG. 2, the number of states is (2 ⁶ = 64). And
The path that transits to each state is one of two types. That is, the next state of the shift register 11 is shifted to the left by one bit, and becomes a state in which the input data is given to the LSB. Therefore, as shown in FIG. (001000) ", the previous state is" 4 (000100) "or" 36 (1
00100) ”. A trellis diagram is created from such state transitions. In the Vitaz decoding apparatus to which the present invention is applied, a trellis diagram is created based on such a state transition, a surviving path is selected from the trellis diagram, and a convolutional code is decoded.

The data received from the input terminals 1A and 1B is supplied to the branch metric calculation circuit 2. The branch metric calculation circuit 2 calculates the distance between the reception data and the reception data candidate. That is, as candidates for the received data (I, Q), (0, 0), (0, 1),
(1,0) and (1,1). The branch metric calculation circuit 2 receives the received data (I, Q) and the candidates (0, 0), (0, 1), (1, 0),
The distance to (1,1) is obtained, and this is output as branch metrics BM00, BM01, BM10, and BM11.

The branch metric calculation circuit 2 uses a technique called soft decision. This is because if the demodulator determines whether the received data is 0 or 1, the data becomes an intermediate value between 0 and 1 due to noise or distortion in the transmission path, and the data may be erroneously determined. The distance is calculated by expressing the distance in about three bits. That is, in this case, candidates for the reception data (I, Q) are:
(00000,000), (000,111), (111,
000) and (111,111). The distance between the candidate expressed in this way and the received data is obtained.

The output of the branch metric calculation circuit 2 is A
It is supplied to the CS circuit 3. The ACS circuit 3 adds an adder that adds a state metric and a branch metric of two paths that reach the state, a comparator that compares the obtained metrics of the two paths, and selects a surviving path from an output of the comparator. Selector.

FIG. 4 shows a specific configuration of the ACS circuit.
In FIG. 4, the input terminal 21 and the input terminal 23
Are supplied. To the input terminal 22,
The state metric at the time (t-1) of the state m is supplied. The input terminal 24 is connected to the state (m + 32) at the time (t−
The state metric of 1) is supplied.

The adder 2 calculates the branch metric from the input terminal 21 and the state metric from the input terminal 22.
5 to be added. The branch metric from the input terminal 23 and the state metric from the input terminal 24 are supplied to the adder 26 and added.

The output of the adder 25 is supplied to a comparator 27 and also to a selector 28. The output of the adder 26 is supplied to a comparator 27 and also to a selector 28.

The comparator 27 compares the output of the adder 25 with the output of the adder 26, and determines the likelihood of the two paths that reach that state. The output of the comparator 27 is the selector 2
8 is supplied. The comparator 27 switches the selector 28 such that the higher likelihood of the two paths is output from the obtained metric. Thereby, the surviving path is selected.

The output of the selector 28 is the flip-flop 2
9. The flip-flop 29 has a terminal 30
Is supplied with a clock. The output of the flip-flop 29 is output from the output terminal 31.

In FIG. 1, the output of the ACS circuit 3 is supplied to a path memory 4. The path memory 4 stores the surviving paths in each state. The output of the path memory 4 is supplied to the determination circuit 5. The maximum likelihood determination of the output of the path memory 4 in each state is performed by the determination circuit 5. This allows
The received data is decoded. The decoded data is output from the output terminal 6.

The path memory 4 will be described in detail. The path memory 4 stores the surviving path in each state as described above. In the path memory 4 to which the present invention is applied, the chip size and the power consumption are reduced.

That is, the conventional path memory cell is the same as that shown in FIG.
As shown in FIG. 7, one state of each stage is configured as a unit. On the other hand, in the path memory cell to which the present invention is applied, one path memory cell is configured from the two states of the N-th stage and the two states of the (N + 1) -th stage that follow. I have. With such a configuration, wiring can be optimally performed.

In other words, when a code having a constraint length of 7 is used, when the coding rate is set to 7/8 by using a punctured code, about 100 stages of path memories are required with one stage number of 64 stages. You. And the connection between each stage becomes very complicated. Therefore, how each stage of the path memory is wired has a great influence on the chip size. In the case of laying out with metal three-layer wiring, it is considered that an optimum wiring is obtained in the following manner.

The path memory in the state m is connected to the path memory cells in the states 2m and (2m + 1). From this, in each stage, a certain state (state m and state (m +
2 ^(K-2) )) and a path memory indicating the next state (states 2m and (2m + 1)) next to that state are arranged adjacent to each other, so that only one connection is required from the preceding stage. . As a result, the number of inter-stage connections can be reduced to a half of 64 lines.

Next, as for the tangent line between the path memories, at least about 32 intersections may occur due to the rules of connection.
Since the width of this intersection is determined by the pitch of the metal wiring,
The shorter the length in the direction perpendicular to the tangential direction, the smaller the area of the intersection. However, its length must be (wiring pitch × 64) or more. Furthermore, if the wiring passes closely over the cell, the contact area of the path memory cell of the wiring must be increased. For this reason, the shape of each stage of the path memory cell is preferably closer to a square as shown in FIG. 5B than to a shape as shown in FIG.

The wiring layers are allocated to the signal lines and the power supply lines on the path memory cell circuit, as shown in FIG. 6, by making the path connection lines in the first wiring layer and by setting the ACS selection lines in the second wiring layer. It is desirable that the wiring be performed in a direction orthogonal to the path connection line in the wiring layer.
It is a matter of course that both are formed in different wiring layers, but the reason why they are made orthogonal is that the intersection of the path connection lines between the stages is performed using the second wiring layer.

In the path memory cell to which the present invention is applied, as shown in FIG. 7B, the path memory cell is composed of the two states of the N-th stage and the following two states of the (N + 1) -th stage. Is done. Then, as shown in FIG. 7A, the cells are arranged in a state close to a substantially square. The path connection line is formed in the first wiring layer, and the ACS selection line is formed in the second wiring layer in a direction orthogonal to the path connection line.

Further, in the path memory cell to which the present invention is applied, two D flip-flops which operate with a clock having a half cycle of a system clock and a half cycle phase shift, instead of being shifted by one clock by a D flip-flop. The output of the selector is fetched by the
The output of the flip-flop is taken out alternately. Thus, the operating frequency of the flip-flop is reduced, and power consumption can be reduced.

FIG. 8 shows an example of a path memory cell in a Viterbi decoder to which the present invention is applied. The path memory cell has the state m and the state (m + 32) of the Nth stage, and the state 2m and the state (2m +
4) are configured as one pass memory cell.

In FIG. 8, two data are supplied to the input terminals 31 and 32 from the stage before going to the state m. The data from the input terminals 31 and 32 is
Are supplied to the A-side input and the B-side input, respectively. A selector 37 is supplied with a select signal from a terminal 37 based on an output from the ACS circuit.

The output of the selector 35 is the flip-flop 4
1 and 42. In the flip-flop 41,
The clock CK1 is supplied. The clock CK2 is supplied to the flip-flop 42. The clocks CK1 and CK2 are clocks having a frequency half of that of the system clock CK, and are shifted in phase by half a period from each other. Outputs of the flip-flops 41 and 42 are supplied to an A-side input and a B-side input of the selector 45, respectively. In the selector 45,
From the terminal 47, a system clock CK is supplied as a select signal. The output of the selector 45 is supplied to the A-side input of the selector 51 and the A-side input of the selector 52.

Data from the input terminals 33 and 34 are supplied to the A-side input and the B-side input of the selector 36, respectively. A selector 36 is supplied with a select signal from a terminal 38 based on the output of the ACS circuit.

The output of the selector 36 is the flip-flop 4
3 and 44. In the flip-flop 43,
The clock CK1 is supplied. The clock CK2 is supplied to the flip-flop 44. Flip-flop 4
The outputs of 3 and 44 are supplied to the A-side input and B-side input of the selector 46, respectively. The selector 46 is supplied with a system clock CK from a terminal 48 as a select signal. The output of the selector 46 is supplied to the B-side input of the selector 51 and the B-side input of the selector 52.

The selector 51 is supplied with a select signal from a terminal 53. The output of selector 51 is output terminal 55
Output from The selector 52 is supplied with a select signal from a terminal 54. The output of the selector 52 is output from the output terminal 56.

FIG. 9 is a timing chart showing the operation of each part of the above-mentioned memory cell. In FIG. 9, as shown in FIG. 9D, data D10, D1
Are supplied to the input terminal 32, and data D20, D21, D22,... Are supplied to the input terminal 32 as shown in FIG. 9E. A select signal is supplied to the select signal input terminal 37 as shown in FIG. 9F. With this select signal, data from the input terminal 31 and data from the input terminal 32 are selected. The output of the selector 35 is supplied to D flip-flops 41 and 42.

A clock CK1 as shown in FIG. 9B is supplied to the D flip-flop 41, and a clock CK2 having a half-period phase different from that of the clock CK1 is supplied to the D flip-flop 42 as shown in FIG. 9C. . The output of the selector 35 is taken into the D flip-flop 41 by the clock CK1. The output of the selector 35 is taken into the D flip-flop 42 by the clock CK2. Therefore, flip-flop 4
1 outputs data as shown in FIG. 9G.
Data is output from the flip-flop 42 as shown in FIG. 9H.

As shown in FIG. 9I, data D30, D31, D32,... Are supplied to the input terminal 33, and data D40, D41,.
D42,... Are supplied. The select signal input terminal 38 is supplied with a select signal as shown in FIG. 9K.
With this select signal, data from the input terminal 33 and data from the input terminal 34 are selected. The output of the selector 36 is supplied to D flip-flops 43 and 44.

A clock CK1 as shown in FIG. 9B is supplied to the D flip-flop 43, and a clock CK2 having a half-period phase different from that of the clock CK1 is supplied to the D flip-flop 44 as shown in FIG. 9C. . The output of the selector 36 is taken into the D flip-flop 43 by the clock CK1. The output of the selector 36 is taken into the D flip-flop 44 by the clock CK2. Therefore, flip-flop 4
3 outputs data as shown in FIG. 9L.
Data is output from the flip-flop 42 as shown in FIG. 9M.

The output of the flip-flop 41 and the output of the flip-flop 42 are supplied to the selector 45. The selector 47 is supplied with the system clock CK shown in FIG. The output of the flip-flop 41 (FIG. 9G) and the output of the flip-flop 42 (FIG. 9H) are distributed by the selector 45 by the system clock CK. As a result, the selector 45 outputs the signal from FIG.
The data is output as shown in FIG.

The output of the flip-flop 43 and the output of the flip-flop 44 are supplied to the selector 46. The selector 46 is supplied with the system clock CK shown in FIG. The output of the flip-flop 43 (FIG. 9L) and the output of the flip-flop 44 (FIG. 9M) are distributed by the selector 46 by the system clock CK. As a result, the selector 46 outputs
The data is output as shown in FIG.

As shown in FIG. 9P, the selector 51
A select signal is supplied. By this select signal,
The output of the selector 45 (FIG. 9N) and the output of the selector 46 (FIG. 9O) are selected. Thereby, the output terminal 55
, Data is output as shown in FIG. 9Q.

As shown in FIG. 9R, the selector 52
A select signal is supplied. By this select signal,
The output of the selector 45 (FIG. 9N) and the output of the selector 46 (FIG. 9O) are selected. Thereby, the output terminal 56
, Data is output as shown in FIG. 9S.

The outputs of the N stages, that is, the outputs of the selectors 45 and 46 are obtained by delaying the output of the N stage in the case of the conventional path memory cell by one clock.
This is the output of the memory cell, ie, the output terminals 55 and 56.
Is made to coincide with the output timing of the conventional memory cell. For this purpose, it is necessary to prepare a (N + 1) -stage select signal that is obtained by delaying the normal select signal by one clock.

In order to confirm that such a path memory cell performs the same operation as the conventional path memory cell,
In the conventional path memory cell, the state m and the state (m +
32), the state 2m and the state (2m +
An example in which the four parts 1) and 1) are configured will be described below.

In FIG. 10, 151A is an n-stage state memory cell in the state m, and 151B is an n-stage state memory (m + 3).
2) Path memory cell. 151C is (n + 1)
The path memory cell 151D in the state 2m of the stage is (n +
1) The path memory cell in the state (2m + 1) of the stage.

Selector 111 of path memory cell 151A
A is supplied with two data from the preceding stage via input terminals 121A and 122A. One of the two data is selected by the selector 111A, and is output via the D flip-flop 112A. Similarly, two data from the preceding stage are supplied to the selector 111B of the path memory cell 151B via the input terminals 121B and 122B. One of the two data is selected by the selector 111B, and this is
Output via B.

The selector 111 of the path memory cell 151C
C is supplied with two data from the path memory cells 151A and 151B via the input terminals 121C and 122C. One of the two data is selected by the selector 111C, and this is output from the output terminal 125C via the D flip-flop 112C. Similarly, the path memory cell 151 is connected to the selector 111D of the path memory cell 151D via the input terminals 121D and 122D.
Two data from 1A and 151B are provided. One of the two data is selected by the selector 111D, and is output from the output terminal 125D via the D flip-flop 112D.

FIG. 11 is a timing chart showing data of each part when a two-stage path memory is configured as described above. In FIG. 11, as shown in FIG. 11B, the data D1 is input to the input terminal 121A of the memory cell 151A.
0, D11, D12,... Are supplied to the input terminal 122A.
As shown in FIG. 11C, data D20, D21, D
, Are supplied. The select signal is supplied to the select signal input terminal 123A of the memory cell 151A, as shown in FIG. 11D. With this select signal, data from the input terminal 121A and data from the input terminal 122B are selected. The selected data is output after being delayed by one clock in the D flip-flop 112A. Therefore, data is output from the output terminal 125A as shown in FIG. 11F.

The input terminal 12 of the memory cell 151B
1B, as shown in FIG. 11F, data D30, D3
, D32,... Are supplied to the input terminal 122B.
As shown in FIG. 1G, data D40, D41, D42,.
Is supplied. The select signal is supplied to the select signal input terminal 123B of the memory cell 151B as shown in FIG. 11H. By this select signal, the input terminal 1
The data from 21B and the data from input terminal 122B are selected. The selected data is output after being delayed by one clock in the D flip-flop 112B. Therefore, data is output from the output terminal 125B as shown in FIG. 11I.

The output (FIG. 11E) of the memory cell 151A is supplied to the input terminal 121C of the memory cell 151C, and the output (FIG. 11I) of the memory cell 151B is supplied to the input terminal 122B. The select signal is supplied to the select signal input terminal 123C of the memory cell 151C as shown in FIG. 11J. By this select signal, the data from the input terminal 121C and the input terminal 122
The data from C is selected. The selected data is
The output is delayed by one clock in the D flip-flop 112C. Therefore, from the output terminal 125C, FIG.
Data is output as shown in 1K.

The output (FIG. 11E) of the memory cell 151A is supplied to the input terminal 121D of the memory cell 151D, and the output (FIG. 11I) of the memory cell 151B is supplied to the input terminal 122D. The select signal is supplied to the select signal input terminal 123D of the memory cell 151D as shown in FIG. 11L. By this select signal, the data from the input terminal 121D and the input terminal 122
The data from D is selected. The selected data is
The output is delayed by one clock by the D flip-flop 112D. Therefore, from the output terminal 125D, FIG.
Data is output as shown in FIG.

FIGS. 9Q and 9S and FIGS. 11K and 11
As can be seen from a comparison with S, the path memory cell to which the present invention is applied can perform the same operation as the conventional one.

FIG. 12 is a circuit size comparison between a conventional Viterbi decoding device using a path memory, a Viterbi decoding device using the four-choice method, and a Viterbi decoding device to which the present invention is applied. FIG. 13 shows a comparison in operation performance. The effects of the present invention are clear from FIGS. That is, in the Viterbi decoding device and the four-choice method to which the present invention is applied, the clock rate of the path memory can be reduced and the power consumption can be reduced as compared with the conventional method. The four-choice method is disadvantageous in terms of circuit scale. In the Viterbi decoding device to which the present invention is applied, power consumption can be reduced, and the circuit scale hardly increases.

[0066]

According to the present invention, a shift circuit in a path memory cell is provided with two flip-flops operating at clocks having a half frequency of a system clock and different half-cycle phases, and an output of the flip-flop. Since the selector is replaced with a selector for distribution, the operating frequency of the flip-flop of the path memory can be reduced to half.
Therefore, the power consumption can be significantly reduced.

Further, according to the present invention, when a code having a constraint length of K is used, the state M and the state (M + 2
^(K-2) ) and the state (2M) and the state (2M + 1) of the (N + 1) -th stage constitute a path memory cell.
Further, the connection based on the trellis diagram between the path memories is performed by the first wiring layer, the selection signal of each path is performed by the second wiring layer, and in the region where the path memory cell circuit is formed. , The first and second wirings are substantially orthogonal. Thereby, the wiring of the path memory can be optimally performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a Viterbi decoding device to which the present invention can be applied.

FIG. 2 is a block diagram used for describing codes in a Viterbi decoding device to which the present invention can be applied.

FIG. 3 is a schematic diagram used for describing a Viterbi decoding device to which the present invention can be applied.

FIG. 4 is a block diagram of an example of an ACS circuit in a Viterbi decoding device to which the present invention can be applied.

FIG. 5 is a schematic diagram used for describing a Viterbi decoding device to which the present invention can be applied.

FIG. 6 is a schematic diagram used for describing a Viterbi decoding device to which the present invention can be applied.

FIG. 7 is a schematic diagram used for describing a Viterbi decoding device to which the present invention can be applied.

FIG. 8 is a block diagram of an example of a path memory in a Viterbi decoding device to which the present invention can be applied.

FIG. 9 is a timing chart used to describe a path memory in a Viterbi decoding device to which the present invention can be applied.

FIG. 10 is a block diagram used for explaining a path memory.

FIG. 11 is a timing chart used for explaining a path memory.

FIG. 12 is a schematic diagram used for describing one embodiment of the present invention.

FIG. 13 is a schematic diagram used for describing one embodiment of the present invention.

FIG. 14 is a block diagram used for describing a convolutional code.

FIG. 15 is a state transition diagram used for describing a convolutional code.

FIG. 16 is a trellis diagram used for describing Viterbi decoding.

FIG. 17 is a block diagram of an example of a conventional path memory cell.

FIG. 18 is a block diagram used for explaining a conventional path memory.

[Explanation of symbols]

 2 Brachymetric operation circuit 3 ACS circuit 4 Path memory 35, 36, 45, 46, 51, 52 Selector 41, 42, 43, 44 Flip-flop

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 H04B 14/00 H04L 25/00

Claims (1)

(57) [Claims] A branch metric calculation circuit for calculating a distance between received data and a candidate for the received data; an adder for adding the branch metric and a state metric; a comparator for comparing metrics;
An ACS circuit comprising a selector for selecting a surviving path from the metric; and a path memory for storing the surviving path .
A memory cell indicating two states of the (N + 1) th stage following the stage
The half-cycle phase differs from each other in units of
Two clocks that operate with a clock of half the frequency of the lock
A flip-flop and the output of the above two flip-flops
And a selector that alternately distributes the
A Viterbi decoding device comprising two sets of elements consisting of