JP3347029B2 - Switching noise reduction device, data filter circuit with built-in noise filter, and car navigation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching noise reduction device for reducing switching noise of a circuit which repeatedly activates and deactivates in response to an activation signal, and a data holding circuit with a built-in noise filter incorporating the switching noise reduction device. And a car navigation device equipped with the data holding circuit with a built-in noise filter.

[0002]

2. Description of the Related Art In recent years, the problem of the electromagnetic environment has been widely taken up. This is because, when EMI (electromagnetic interference) noise occurs, a malfunction or the like of another electronic device occurs, and a serious problem may occur.

There are three main types of EMI noise. (1) Conducted noise from power line,
(2) Leakage noise from a port and (3) radiation noise from an LSI surface.

[0004] The conduction noise from the power line (1) is as follows.
Conduction / radiation depends on the power supply current waveform, using the power supply line as an antenna. In the noise leakage from the port (2), the fluctuation of the power supply potential from the pins of the LSI such as the port is transmitted / radiated using the external wiring as an antenna. Also, the LSI of (3)
Radiation noise from the surface radiates from the LSI surface to space mainly using the current loop as an antenna.

[0005] Among them, there is an urgent need to take measures against the fact that conduction noise from a power supply line has the greatest possibility of adversely affecting other electronic devices.

[0006] The conduction noise from the power supply line changes the power supply current due to a change in the signal input to the circuit, and generates noise. This is generally called switching noise. In order to suppress such switching noise, conventionally, as shown in FIG.
Filter insertion has been performed.

The capacitance C in the figure is called a bypass capacitor, and the resistance R is called a limiter resistance. For example, the bypass capacitor C is formed by a gate capacitance of a transistor, and the limiter resistance R is formed by a poly resistance or an aluminum resistance. Further, the activation signal GN in the figure is a signal based on a clock signal, and the circuit 101 is constituted by, for example, a latch.

FIGS. 14 (a), (b), (c), (d)
7A is a waveform diagram of each node when a simulation of the circuit is performed using SPICE. FIG. 7A is a voltage waveform of an activation signal GN, FIG. 7B is a voltage waveform of an input signal DIN, FIG. 3C shows the voltage waveform of the output signal Q, and FIG. 3D shows the current waveform of the power supply VDD.

When the activation signal GN changes in the circuit 101 connected to the power supply VDD, a power supply current flows. Assuming that activation signal GN is repeated in a similar manner every certain period, the power supply current also has a certain period, as is apparent from FIG. The electromagnetic wave radiated by the power supply current can be obtained by using Maxwell's equation. However, noise analysis is usually performed using Fourier analysis of power supply current and a spectrum expressed as a transmission amount (dB) with respect to a reference value for each frequency.

FIG. 15 shows a spectrum with respect to the power supply current of FIG.

The reference value is 1A. Hereinafter, similarly, the reference value is 1A in the spectrum. It is estimated that the smaller the transmission amount [dB], the lower the noise level. The radiated power can be similarly expressed using a spectrum, but is omitted here.

When the activation signal GN changes and the circuit 101 operates, a current is supplied from the electric charge stored in the bypass capacitor C together with the current from the power supply VDD. At this time, since the current flowing to the power supply VDD is limited by the limiter resistance R, a rapid change in the power supply current is reduced. Therefore, the noise level is reduced as compared with the case where there is no RC filter.

[0013]

As described above, in the prior art, a noise filter including a limiter resistor R and a bypass capacitor C as shown in FIG. 13 has been used to reduce switching noise. However, in particular, a large number of latches used in an integrated circuit operate simultaneously in synchronization with a clock, so that a rapid power supply current flows and switching noise occurs. At this time, when the capacitance of the bypass capacitor C is small and the load current is large, the switching noise may exceed an allowable value.

That is, in the conventional configuration of FIG. 13, the load current consumed by the circuit 101 is directly supplied from the power supply VDD, so that a rapid power supply current flows. In order to sufficiently suppress the switching noise generated at this time, it is necessary to provide a bypass capacitor C having a large capacity.

However, conventionally, when inserting an RC filter into an LSI chip, it has been difficult to insert a large-capacity bypass capacitor from the viewpoint of chip area limitation and cost. Therefore, if a bypass capacitor with a small capacity is used in consideration of the chip area and cost, it is extremely difficult to sufficiently reduce the switching noise generated by a sudden change in the power supply current. At present, it is not possible to cope with the generation of switching noise exceeding.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a switching device capable of sufficiently reducing switching noise even when a bypass capacitor having a small capacitance is used. It is to provide a noise reduction device. Another object of the present invention is to provide a data holding circuit with a built-in noise filter which incorporates the switching noise reduction device according to the above object. Still another object is to provide a car navigation device equipped with the data holding circuit with a built-in noise filter according to the above object and reducing electromagnetic interference noise of the entire system.

[0017]

In order to achieve the above object, a switching noise reduction apparatus according to the present invention is characterized in that it is connected in series between a power supply and a circuit and controls activation / deactivation of the circuit. It is composed of two transistors that are turned on / off based on an activation signal, and a capacitor connected between a first node between the two transistors and the ground. When the circuit is activated, When the first transistor connected to the power supply side of the two transistors is in a non-conductive state, the second transistor connected to the circuit side is in a conductive state, and the circuit is not activated, The first transistor is turned on and the second transistor is turned off, and the on-resistance value of the first transistor is set to the second transistor. Lies in the set to be larger than the on-resistance of the register.

[0018]

[0019]

[0020]

Another feature of the switching noise reduction device according to the present invention is that the switching noise reduction device is connected in series between a power supply and a circuit, and is turned on / off based on an activation signal for controlling activation / deactivation of the circuit. One transistor and a capacitor connected between a first node between the two transistors and the ground, and when the circuit is activated, it is connected to the power supply side of the two transistors. When the first transistor is turned off and the second transistor connected to the circuit side is turned on and the circuit is not activated, the first transistor is turned on and the second transistor is turned off. A transistor is configured to be in a non-conductive state, and a first resistor is connected in series between the first transistor and the first node.

[0022]

[0023]

[0024]

[0025]

[0026]

A switching noise reduction device according to another aspect of the invention is characterized in that the switching noise reduction device is connected in series between a power supply and a latch which is activated / inactivated by an activation signal generated based on a clock signal. Two transistors that are turned on / off based on a clock signal, a capacitor connected between a first node between the two transistors and a ground, the first transistor and the first transistor,
A first resistor connected in series with the node; and a second resistor for supplying a current from the power supply to the latch when the latch is in an inactive state, and when the latch is activated. When the first transistor connected to the power supply side of the two transistors is turned off, the second transistor connected to the latch side is turned on, and the latch is not activated. Is that the first transistor is turned on and the second transistor is turned off.

[0028]

The data holding circuit with a built-in noise filter according to another invention is characterized by a main control section for controlling the operation of the entire apparatus and a GP for receiving radio waves from GPS satellites.
An S receiver unit, a storage medium control unit that controls a storage medium storing map information, and a display that displays various information including map information are provided in the vehicle, and the current position is determined based on radio waves from GPS satellites. In a car navigation device for displaying on a display, all latch circuits provided in the main control unit are activated / activated by an activation signal generated based on a clock signal.
A latch main body in an inactive state, two transistors connected in series between the latch main body and a power supply, and controlled to be turned on / off based on the clock signal; A capacitor connected between a first node and ground, a first resistor connected in series between the first transistor and the first node, and a power supply when the latch body is inactive. A second resistor for supplying current to the latch body, wherein when the latch body is activated, a first transistor connected to a power supply side of the two transistors is non-conductive. In this state, the second transistor connected to the latch main body side is turned on, and when the latch main body is not activated, the first transistor is turned on. In that the second transistor is configured to be non-conductive.

[0030]

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a switching noise reduction device according to a first embodiment of the present invention.

The switching noise reduction device (noise filter) of this embodiment includes two transistors 11 and 12 connected in series between a power supply VDD and a circuit 1, a node N between the two transistors, and a ground. GND
And a bypass capacitor C connected therebetween. The circuit 1 is activated when the activation signal GN is, for example, at “H” level, and is inactivated when it is at “L” level. That is, the activation signal GN repeats “H” level and “L” level at a predetermined cycle t as shown in FIG.
In response to this, circuit 1 is activated / deactivated.

In the present embodiment, the two transistors 11 and 12 are composed of P-channel MOS transistors, and are turned on / off by an activation signal GN and its inverted signal GNI, respectively. Further, the transistor 11
Is set to be higher than that of the transistor 12.

The electric charge stored in the bypass capacitor C is preferably equal to the electric charge consumed in the circuit 1, and the capacitance value of the bypass capacitor C is obtained by dividing this value by the voltage.

Next, the operation of the noise filter of this embodiment will be described.

When the activation signal GN goes to "H" level,
When the circuit 1 is in the activated state, the transistor 12 is turned on, and a current is supplied to the circuit 1 from the bypass capacitor C. At this time, the transistor 11 is off, and no current flows through the power supply VDD line.

When the activation signal GN is at "L" level, the transistor 11 is turned on and the transistor 12 is turned off, so that electric charge is supplied from the power supply VDD to the bypass capacitor C. At this time, since the on-resistance value of the transistor 11 is increased, the current flowing to the power supply VDD is suppressed to a small value, and noise can be sufficiently reduced.

As described above, in the present embodiment, since the load current consumed in the circuit 1 is not directly supplied from the power supply VDD, no abrupt power supply current flows. Therefore, it is not necessary to increase the capacitance value of the bypass capacitor C more than necessary. With the minimum capacitance value required for the operation of the circuit 1, the switching noise can be sufficiently reduced.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram of a switching noise reduction device according to a second embodiment of the present invention. Elements common to FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

The noise filter according to the present embodiment is obtained by inserting a limiter resistor R in series between the transistor 11 and the node N in the configuration shown in FIG. As a result, in the first embodiment, it is necessary to increase the gate length in order to increase the on-resistance value of the transistor 11, so that the circuit formation area is increased. In the present embodiment, since the limiter resistor R is provided, the on-resistance value of the transistor 11 can be reduced accordingly, and the circuit formation area can be made smaller than in the first embodiment.

The operation of this embodiment is the same as that of the first embodiment. The value of the limiter resistance R can be expressed by the following equation.

R = T / (α · C) where T is a time constant C is a capacitance value of a bypass capacitor α is a value from 2 to 4. Next, a third embodiment of the present invention will be described.

FIGS. 4A, 4B and 4C are diagrams for explaining a switching noise reduction device according to a third embodiment of the present invention, and FIG. 4A is a circuit diagram of the device. FIG. 2B is a configuration diagram of a generation unit of the activation signal GN, and FIG. 2C is a waveform diagram of the clock signal CLK.

In the noise filter according to the present embodiment, the circuit 1 is configured by a latch in the configuration of FIG.
A resistor 21 is connected between the DD and the latch 1 in parallel with the transistor 11, the limiter resistor R and the transistor 12.

This resistor 21 is provided to supplement the current in consideration of a leak current ILEAK generated when the state of the latch 1 is held. The resistance value R21 of the resistor 21 is substantially equal to a value obtained by dividing the power supply voltage VDD by the leak current ILEAK (R21 = VDD / ILEAK), and is very large. Therefore, the power supply current flowing through the resistor 21 becomes very small, and the occurrence of noise at this time can be ignored.

A clock signal CLK for controlling on / off of the transistor 11 is an activation signal G of the latch 1.
A signal CLKI that is in phase with N and that controls on / off of the transistor 12 is a signal that is in phase opposite to the activation signal GN of the latch 1.

Further, the signal CLKI and the activation signal GN
Is generated by two-stage inverters 31 and 32 which receive the clock signal CLK as shown in FIG. The clock signal CLK is, as shown in FIG.
This signal periodically repeats the “H” level and the “L” level.

FIG. 5 is an internal circuit diagram of the latch 1.

This latch circuit 1 has a CMOS inverter 51 to which an input signal DIN is applied, and has a tri-state inverter 52 and a CMOS inverter 5 on its output side.
3, and the CMOS inverter 54 are sequentially connected, and the output signal Q is output from the CMOS inverter 54 at the last stage.

On the other hand, two-stage CMOS inverters 55 and 56 which receive the activation signal GN as inputs are provided, and generate signals to be supplied to the control nodes N1 and N2 of the tristate inverter 52.

According to latch 1, when activation signal GN is at "H" level, tristate inverter 52
Are in a through state, and the input signal DIN is output as it is as the output signal Q (activation of the latch 1). Conversely, when activation signal GN is at "L" level, tristate inverter 52 is in a data holding state, and the output of tristate inverter 52 and the next-stage CMOS inverter 5
Then, an output signal Q corresponding to the node level held between the input and the third input is output (the latch 1 is inactivated).

FIGS. 6A and 6B show other internal circuit diagrams of the latch 1. FIG.

Next, the operation of the noise filter of this embodiment added to the latch 1 will be described.

When clock signal CLK is at "L" level, transistor 11 is turned on and transistor 12 is turned off.
Are turned off, and electric charge is supplied from the power supply VDD to the bypass capacitor C. At this time, a current for maintaining the state of the latch 1 is supplied from the power supply VDD to the latch 1 via the resistor 21. That is, when the latch 1 does not operate,
Power is supplied to the bypass capacitor C, and power supply to the latch 1 supplies the minimum power required for data retention.

When the clock signal CLK goes high and the latch 1 is activated, the transistor 1
2 becomes conductive, and current is supplied from the bypass capacitor C. At this time, the transistor 11 is off, and no current flows through the power supply VDD line. That is, the latch 1 and the bypass capacitor C are connected before the operation state of the latch 1, and the power supply VDD and the bypass capacitor C are connected.
Disconnect.

As described above, in the present embodiment, the power is supplied from the bypass capacitor C to the latch 1 during the active period of the clock signal CLK, and the bypass capacitor C is charged during the negative period of the clock signal CLK.
As a result, the load current consumed by the latch 1 is not directly supplied from the power supply VDD, so that an abrupt power supply current does not flow. Therefore, it is not necessary to increase the capacitance value of the bypass capacitor C more than necessary. With the minimum capacitance value required for the operation of the latch 1, the switching noise can be sufficiently reduced.

FIGS. 7A to 7F are waveform diagrams of each node when the circuit of this embodiment is simulated using SPICE. FIG. 7A shows the clock signal CL.
K, the voltage waveform of the signal CLKI, FIG.
2C shows the voltage waveform of the activation signal GN, FIG. 2D shows the voltage waveform of the input signal DIN, FIG. 2E shows the voltage waveform of the output signal Q, and FIG. 2F shows the current of the power supply VDD. It is a waveform.

FIG. 8 shows a spectrum with respect to the power supply current of FIG. In the measurement of this spectrum, FIG.
The circuits other than the middle noise filter are the same as the conventional circuit of FIG. 13, and the size of the transistor and the capacitance value of the bypass capacitor C are also the same. As shown in FIG.
In this embodiment, it can be seen that the dB value representing the noise level is significantly reduced as compared with the conventional example shown in FIG.

In the first to third embodiments, the example in which the activation signal GN is activated at the “H” level has been described as the circuit 1, but the circuit 1 is activated at the “L” level. Needless to say, it is applicable.

Hereinafter, an example in which the switching noise reduction device of the present invention is mounted on a car navigation device will be described.

The car navigation device is used in a car, receives radio waves from three or more GSP satellites orbiting 2100 km above the sky, and can determine the current position from the time difference between the radio waves.

FIG. 9 is a block diagram showing a configuration of a car navigation device showing an application example of the switching noise reduction device (noise filter) of the present invention.

In the figure, reference numeral 80 denotes a main control section for controlling the operation of the entire apparatus, which is composed of the components shown in FIGS. The main control unit 80 is composed of, for example, a 32-bit general-purpose RISC microprocessor.

As shown in FIG. 10, the microprocessor 80 includes a processor core 81 serving as a core of the operation of the processor, a write buffer / bus controller 82,
The debug support unit 83, the memory protection unit 84, and the clock generator 85
It is mounted and configured in a chip.

Further, as shown in FIG. 11, the processor core 81 includes the product-sum operation unit 8 for realizing the DSP function.
CPU core 8 including memory 1a and memory management 81b
1c, instruction cache 81d, and data cache 8
1e, and a bus interface unit 81f for externally interfacing each of these elements.

Here, as shown in FIG. 12, all the latch circuits incorporated in the respective components of the main control section 80 have, for example, a noise filter with a built-in noise filter described in the third embodiment. It is constituted by a latch circuit 90. Note that the bypass capacitor C
Is formed, for example, by the gate capacitance of a transistor, and the limiter resistance R is formed by a poly resistance or an aluminum resistance.

Reference numeral 91 in FIG. 9 denotes a GPS receiver unit, which receives a radio wave of 1575.42 MHz from a GPS satellite and obtains a required radio wave of 20 MHz through an RF down converter, a filter, an IF down converter, and the like. 92
Is a DRAM used as a frame buffer and a system memory, and 93 is a mask ROM (MROM) used as a program memory and a character generator. Further, S 94 used as a work area
A RAM 95 is a CD-ROM interface. A CD-ROM control section 96 is connected to the CD-ROM interface 95. CD-R
The OM control unit 96 stores the map software and the like.
It has a function of controlling the drive of the D-ROM 97 and decoding stored data.

DRAM 92, mask ROM 93, SRA
The M94 and the CD-ROM interface 95 are connected to the main control unit 80 via a system bus. The display 98 displays map information and the like.

Normally, a car navigation apparatus is often used in such a manner that map information is extracted from a CD-ROM 97 on a display 98 provided in a vehicle and a shortest course from its current position to a destination is selected. During the operation, in the conventional car navigation device, strong electromagnetic interference noise is generated, and the noise may enter into, for example, an FM radio disposed near the device.

On the other hand, in the above-described car navigation device equipped with the latch circuit 90 with the noise filter of the present invention, the switching noise generated by the latch circuit operating in synchronization with the clock signal in the integrated circuit can be greatly reduced. Therefore, the occurrence of electromagnetic interference noise in the entire system is suppressed, and the above-described problems can be avoided.

[0072]

As described in detail above, according to the switching noise reduction device of the first invention, when the circuit operates, current is supplied only from the capacitor and the power supply and the circuit are cut off. The power supply current does not change much. This eliminates the need to increase the capacitance value of the capacitor more than necessary, and can greatly reduce switching noise even when using a capacitor with a small capacitance (capacity equivalent to or less than the conventional one). become.

According to the switching noise reduction device of the second invention, in the first invention, the on-resistance of the first transistor is set to be larger than the on-resistance of the second transistor. When electric charge is supplied to the capacitor, the current flowing to the power supply is kept small,
The noise level can be further reduced.

According to the switching noise reduction device of the third aspect, in the first aspect, the first resistor is connected in series between the first transistor and the first node. The on-resistance value of the transistor can be kept small, and the circuit formation area can be made smaller than in the second invention.

According to the switching noise reduction device of the fourth invention, in the third invention, the first resistor R is represented by R = T / (α · C) (where T:
Time constant, C: capacitance value of the bypass capacitor, α: value from 2 to 4), and the first resistor and the capacitor function to
The current flowing through the power supply can be reduced, and the switching noise can be accurately reduced.

According to the switching noise reduction device of the fifth invention, in the third invention, the second resistor for supplying a current from the power supply to the circuit when the circuit is inactive is connected. Of the circuit is performed, and the state of the circuit when inactive can be reliably maintained.

According to the switching noise reduction device of the sixth aspect, in the first to fifth aspects, the activation signal is a signal that periodically repeats a high level and a low level. Switching noise of a circuit that repeatedly activates and deactivates periodically can be accurately reduced.

According to the switching noise reduction device of the seventh aspect, it is possible to greatly reduce the switching noise generated by the latch operating in synchronization with the clock signal.

According to the data holding circuit with a built-in noise filter according to the eighth invention, the switching noise generated by the latch operating in synchronization with the clock signal in the integrated circuit can be greatly reduced.

According to the car navigation device of the ninth aspect, the data holding circuit with a built-in noise filter of the eighth aspect is incorporated, so that the same effect as that of the eighth aspect can be obtained, and the system as a whole can be realized. It is possible to suppress the occurrence of electromagnetic interference noise.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a switching noise reduction device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of an activation signal GN.

FIG. 3 is a circuit diagram of a switching noise reduction device according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining a switching noise reduction device according to a third embodiment of the present invention.

FIG. 5 is an internal circuit diagram of the latch 1;

FIG. 6 is another internal circuit diagram of the latch 1;

FIG. 7 is a waveform diagram of each node when the circuit shown in FIG. 4 is simulated using SPICE.

8 is a graph showing a spectrum with respect to a power supply current shown in FIG.

FIG. 9 is a configuration block diagram of a car navigation device showing an application example of the switching noise reduction device of the present invention.

FIG. 10 is a block diagram showing an internal configuration of a microprocessor 80.

FIG. 11 is a block diagram showing an internal configuration of a processor core 81.

FIG. 12 is a block diagram showing an internal configuration of a latch circuit with a noise filter 90;

FIG. 13 is a diagram showing a configuration of a conventional noise filter.

14 is a waveform diagram of each node when a simulation is performed on the conventional circuit shown in FIG. 13 using SPICE.

FIG. 15 is a graph showing a spectrum with respect to the power supply current shown in FIG.

[Explanation of symbols]

 Reference Signs List 1 circuit, latch, latch body 11, 12 transistor C bypass capacitor GN activation signal GNI inversion signal of activation signal VDD power supply GND ground

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takashi Ishioka 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation Semiconductor System Technology Center (56) References JP-A-54-1857 (JP, A) JP-A-6-217465 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02J 1/00-1/16 H02J 7/00-7/12 H02J 7/34-7 / 36

Claims (6)

(57) [Claims] 1. A transistor connected in series between a power supply and a circuit, the transistor being on / off controlled based on an activation signal for controlling activation / inactivation of the circuit, and an intermediate between the two transistors. When the circuit is activated, the first transistor connected to the power supply side of the two transistors is turned off and the circuit is turned off. When the second transistor connected to the side becomes conductive and the circuit is not activated,
The first transistor is turned on and the second transistor is turned off, and the on-resistance of the first transistor is set to be larger than the on-resistance of the second transistor. A switching noise reduction device, characterized in that: 2. A transistor which is connected in series between a power supply and a circuit and which is turned on / off based on an activation signal for controlling activation / deactivation of the circuit, and an intermediate between the two transistors. And a capacitor connected between the first node and the ground. When the circuit is activated, the first transistor connected to the power supply side of the two transistors is turned off, and the circuit is turned off. When the second transistor connected to the side becomes conductive and the circuit is not activated,
The first transistor is turned on and the second transistor is turned off, and a first resistor is connected in series between the first transistor and the first node. A switching noise reduction device characterized by the above-mentioned. 3. The resistance value R of the first resistor is defined as: R = T / (α · C), where T: time constant C: capacitance value of a bypass capacitor α: a value from 2 to 4. The switching noise reduction device according to claim 2, wherein: 4. The switching noise reduction device according to claim 2, wherein a second resistor for supplying a current from a power supply to the circuit is connected when the circuit is in an inactive state. 5. A power supply is connected in series between a latch that is activated / deactivated by an activation signal generated based on a clock signal and a power supply, and is turned on / off based on the clock signal. Two transistors, a capacitor connected between a first node between the two transistors and ground, a first resistor connected in series between the first transistor and the first node, A second resistor for supplying a current from the power supply to the latch when the latch is in an inactive state; and a second resistor connected to a power supply side of the two transistors when the latch is activated. When the first transistor is turned off and the second transistor connected to the latch side is turned on and the latch is not activated, the first transistor is turned off. The passing state, the switching noise reducing apparatus, wherein the second transistor is configured to be non-conductive. 6. A main control section for controlling the operation of the entire apparatus, a GPS receiver section for receiving radio waves from GPS satellites, a storage medium control section for controlling a storage medium storing map information, and various kinds of information including map information. A car navigation device that includes a display for displaying information in a vehicle, determines a current position based on a radio wave from a GPS satellite, and displays the current position on the display; a latch circuit provided in the main control unit, based on a clock signal, A latch main body that is activated / deactivated by the generated activation signal, and two latches that are connected in series between the latch main body and a power supply and that are on / off controlled based on the clock signal A transistor, a capacitor connected between a first node intermediate the two transistors and ground, A first resistor connected in series between a first transistor and the first node, and a second resistor for supplying a current from the power supply to the latch body when the latch body is inactive. When the latch main body is activated, a first transistor connected to a power supply side of the two transistors is turned off and a first transistor connected to the latch main body side is turned off. When the second transistor is turned on and the latch body is not activated, the first transistor is turned on and the second transistor is turned off. A car navigation device having a holding circuit.