JP3346682B2 - PN code synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention CDMA synchronization method for synchronizing the station unit spreading code to the input spread code of a receiver in (Code Division Multiple Access), and other general input pseudo-random code sequence (input PN code sequence) The present invention also relates to a synchronization method for synchronizing a local pseudo random code sequence (local PN code sequence).

[0002]

2. Description of the Related Art FIG. 3 shows a conventional synchronization method. Local PN
A code sequence is generated (S ₁ ), multiplied with the input PN code sequence, and summed for one cycle. That is, the cross-correlation for one PN cycle is calculated (S ₂ ), it is checked whether the correlation value exceeds a threshold value (S ₃ ), and if not, the phase of the local PN code sequence is shifted by one chip (S 2). ₄ ). Determine was performed shifting the phase in each chip of one period of the PN code (S _5), if not end the search for one cycle returns to step S _2. If the correlation value in step S ₃ is has exceeded the threshold value, the local PN code sequence is determined and synchronized with the input PN code sequence (S _6). If you search for all chips in step S _5, it determines that it has not been possible to synchronize (S _7).

[0003]

PN sequence [SUMMARY OF THE INVENTION] is very long, for example, also 32768 chips, P at Step S ₂
It takes time to take the sum of products for one cycle of N code sequences,
If the product-sum for one cycle is not synchronized, the phase of the local PN code sequence is shifted by one chip, and the cycle of obtaining the product-sum for one cycle is repeated, so that it takes a relatively long time to acquire synchronization. Was.

[0004]

According to the present invention, an input PN code sequence is divided for each same chip length to produce a plurality of input partial sequences (first step). A plurality of local subsequences are created by dividing by chip length (second step), and the head of these input subsequences and the head of the local subsequence are taken out (third step). A correlation calculation with the local partial sequence is performed (fourth step), and it is checked whether the result of the correlation calculation has exceeded the first threshold value (fifth step). If it is determined that the value exceeds the first threshold value, it is checked whether or not the correlation calculation has been performed for all of the input subsequences (sixth step). The next ones of the partial sequence and the local partial sequence are respectively extracted, and the process proceeds to the fourth step (seventh step). If it is determined in the fifth step that the value does not exceed the first threshold value, the phase of the local PN code sequence is set to 1
Shift the chip to the second step (eighth step),
If it is determined in the sixth step that the calculations for all have been completed, it is determined that synchronization has been established (ninth step).

According to the second aspect of the present invention, based on the above-mentioned invention, the sixth step includes a tenth step of accumulatively adding the calculation result of the fourth step to the correlation calculation value up to that time. It is checked whether or not the result of the cumulative addition has exceeded the second threshold (step 11). If the result has exceeded the second threshold, it is determined that synchronization has been established, and if the result has not exceeded the second threshold. Includes resetting the cumulative addition result of the tenth step to the eighth step, and in the eighth step.

[0006]

FIG. 1 shows an embodiment of the present invention. First, a local PN code sequence is generated at an appropriate phase (S ₁ ), and the input PN code sequence is divided for each M (M is an integer of 2 or more) chip lengths to produce a plurality of input partial sequences (S ₂ ). Next, the local PN code sequence is divided into M chip lengths to form a plurality of local subsequences (S ₃ ), and the leading portion of these input partial sequences and the leading portion of the local partial sequence are extracted (S ₄ ).
Calculating the correlation between these retrieved input part sequence and the local partial sequence (S _5). It is checked whether the correlation value exceeds the first threshold value (S ₆ ). If the correlation value exceeds the first threshold value, it is checked whether the correlation calculation has been performed for all of the input subsequences (S ₇ ). each next input partial series and the local partial sequence proceeds to step S ₅ is taken out, respectively (S _8).

[0007] correlation value in step S ₆ is determined not to exceed the threshold value, shifted by one chip phase of the local PN code sequence (S _9), 1 period of the PN code to be shifted the one chip investigate whether carried out (S _10). That this shifting process returns to step S ₃ If you have not done one cycle, divides the local PN code sequence shifted its phase by M chip length again, repeating the described above. It determines that the synchronization when it is determined for all the input partial sequence at step S ₇ that performs a correlation calculation is established (S _11). Step S ₁₀
In determining that shifting one chip, if it is determined that went one period, and can not synchronize acquisition (S _12).

[0008] While performing this correlation calculation of step S ₅ the input partial series and the local partial series (product sum calculation), that part sequence length is, for example, 36 chips, of the PN code 1
Because it is significantly shorter than the period length, for example 32768,
It is possible to know in a short time whether or not it is likely to be synchronized, and if not, it is possible to know the determination in a much shorter time than in the conventional method.

[0009] If it is determined that there is a possibility that the synchronization in step S _6, made the correlation calculation for the next partial series, this partial sequence is also briefly determines whether likely to be synchronized it can be known, when it is determined that no synchronized, since immediately shift the phase of the local PN code sequence, whereas if not synchronized in the conventional, its possible for each cycle are detected, the invention will be detected for each partial sequence it is, can be carried out quickly that much shifted local PN code phase synchronization establishment is increased. If it is determined that the likely synchronized continuously for all the input partial sequences, it is higher becomes soluble possibly synchronized to the actual is acquired.

In order to further increase the accuracy of this synchronization establishment,
The processing can be performed as shown in FIG. That is, FIG.
Although corresponding processes as FIG. 1 are given the same step symbols in, in this embodiment, when the correlation value in step S ₆ is determined to exceed the threshold value (first threshold value), the correlation value the by adding accumulated correlation value until then (S _13), the flow proceeds to step S _7. When the calculation of all of the input part sequence is determined to have ended in step S _7, step S
Cumulative addition value obtained in ₁₃ it is checked whether or exceeds the second threshold value (S _14), together with the past unless it proceeds to step S ₉ to a similar in phase in step S ₉ 1 1 chip shifted, in this example resets the accumulated value of the step S ₁₃ to zero. Correlation value obtained by accumulating in step S ₁₄ second
If it is determined that exceeds the threshold value, it is determined that synchronization is established (S _11).

For example, a PN system having one cycle of 32768 chips
A sequence is a local PN code sequence, a sequence including a 5% bit error in the local PN code sequence is an input PN code sequence, and each length of the input partial sequence and the local partial sequence is 32 chips.
Two consecutive input subsequences, that is, 64 chips are taken out, and the correlation with the local PN code sequence is obtained.
The first threshold value used in step ₆ is set to 0.4375, and step S
The second threshold value used in ₁₄ was 0.5357. This second
As the cumulative addition value of the correlation value to be compared with the threshold value, a value normalized by the number of the cumulatively added partial sequences is used. As a result of a simulation using a workstation under such conditions, the maximum time required for synchronization acquisition is 0.22 seconds, and in the case of the conventional method that is not divided into subsequences, it is 0.50 seconds. In the worst case, synchronization can be established in a half of the conventional time. In the above description, the length of the subsequence is set to 32 chips, but this is because the bit length of the arithmetic unit used for the correlation calculation is 32 bits (that is, the arithmetic processing is performed as 32-digit data in binary notation ). For the sake of convenience, the number of chips was set to 32 chips. In this example, 64 consecutive chips in the input PN code sequence are taken out, and the correlation between the chip and the local PN code sequence is obtained. That is, the length of the input PN code sequence is set to 64 chips, and the input PN code sequence is divided into two parts. In the case where the one cycle is a 32768-chip PN code, it is necessary that the value when the correlation value is synchronized is larger than the value when the correlation value is not synchronized in any part of the input code. Is obtained. In this case, the input marks
The signal length is required to be 56 chips or more , and 64 chips are used in order to make the partial sequence 32 chips. In other words,
Input P only for the minimum number of chips that satisfy this condition out of several times
What is necessary is just to take in N code sequences.

[0012]

As described above, according to the present invention, the input PN code sequence and the local PN code sequence are each divided into sub-sequences, and the cross-correlation of the sub-sequences is used to determine whether or not synchronization is likely. And when not synchronized, the local P
In order to shift the phase of the N code sequence, when the synchronization is not performed, it is detected much faster, that is, the state is detected with a significantly smaller amount of calculation. The phase of the local PN code sequence can be shifted, and synchronization can be established in a shorter time than in the past.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of the present invention.

FIG. 2 is a flowchart showing another embodiment of the present invention.

FIG. 3 is a flowchart showing a conventional synchronization method.

Claims (2)

(57) [Claims] 1. A synchronization method for synchronizing a local pseudo-random code sequence (local PN code sequence) with an input pseudo-random code sequence (input PN code sequence), comprising: A second step of dividing the local PN code sequence for each of the same chip lengths to generate a plurality of local subsequences; a head of the input subsequence; A third step of extracting the head of the input subsequence, a fourth step of calculating a correlation between the extracted input subsequence and the local subsequence, and a fifth step of examining whether the result of the correlation calculation has exceeded a first threshold value. A step of determining whether the correlation calculation has been performed for all of the input subsequences if it is determined in step 5 that the first threshold has been exceeded; If it is determined in the sixth step that the calculations for all have not been completed, the next steps of the input subsequence and the local subsequence are respectively taken out, and the seventh step of moving to the fourth step; If it is determined in step 5 that the value does not exceed the first threshold value, an eighth step in which the phase of the local PN code sequence is shifted by one chip to proceed to the second step; A ninth step of determining that synchronization has been established when it is determined that the PN code has been completed. 2. The sixth step includes a tenth step of accumulatively adding the calculation result of the fourth step to the correlation calculation value up to that time, and the ninth step includes calculating the second result of the accumulative addition. includes a eleventh step of Ru determine exceeds the threshold, at the eleventh step, when exceeding the second threshold value, it determines that the synchronization is established, if not exceed the second threshold value The PN code synchronization method according to claim 1, wherein the operation proceeds to the eighth step, wherein the eighth step includes resetting the cumulative addition result of the tenth step.