JP3302007B2 - Spread code synchronization acquisition method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for a direct spread spectrum communication system or the like, which acquires synchronization of a spread code for synchronizing a received signal spread by a spread code with a spread code generated on the receiving side. A method and a synchronization acquisition device.

[0002]

2. Description of the Related Art Direct spread spectrum communication systems (D
In the (S-SS) receiver, it is necessary to synchronize (receive synchronization) the received signal spread with the spread code and the spread code generated on the receiving side. For synchronous acquisition, a method using a sliding correlator and a matched filter (M
The method using F) is generally used.

FIG. 23 is a block diagram of a conventional sliding correlator. In the following description, a binary PN (Pseudo Noise) code is used as an example of a spreading code. In the figure, 101 is a multiplier, 102 is an integrator, 103 is a PN generator, and 104 is a control unit. For the received spread spectrum signal that has been spread by the PN code, the same PN code as the spread code on the transmission side is applied to the PN generator 1.
The multiplier 101 multiplies the received spread spectrum signal by the PN code. Then, the multiplication signal output from the multiplier 101 is integrated in the integrator 102. The above process is called despreading.

In this despreading, if the phase of the PN code spectrum-spread on the transmitting side is synchronized with the phase of the PN code generated by the PN generator 103 on the receiving side, a multiplied signal output from the multiplier 101 is output. Is integrated by the integrator 102 for a certain time (for example, one cycle of the PN code), and the output exceeds a predetermined threshold. When the control unit 104 detects that the predetermined threshold value has been exceeded, the control unit 10
No. 4 determines that the received spread spectrum signal and the PN code generated by the PN generator 103 have been synchronized. Conversely, if the output from the integrator 102 does not exceed the predetermined threshold, the control unit 104 determines that synchronization has not been achieved, and shifts the phase of the PN code output from the PN generator 103. Then, despreading is performed again. FIG.
FIG. 24 is a conceptual diagram showing an output of the sliding correlator shown in FIG. 23. In the figure, the points where the peaks 111 and 112 stand are the synchronization points.

FIG. 25 is a block diagram of a conventional matched filter. In the figure, 121 _{1 to} 121 _N-1 are the first
To the (N-1) th one-chip multi-level delay element, 122 ₁ to 1
22 _N are the first to N-th amplifiers, 123
Is an adder. The received spread spectrum signal is input to a one-chip multi-level delay element 121 _N-1 and an amplifier 122 _N having the last chip of the PN code as a coefficient a _N. However, each of the amplifiers 122 _{1 to} 122 _N has a coefficient a ₁
~ A _N takes a value of {+1, -1}. Multi-level delay element 1
The output of 21 _N-1 is the next multi-level delay element 121 _{N -2} and P
The signal is input to the amplifier 122 _N-1 having the chip one before the last chip of the N code as the coefficient a _N-1 . The above processing is repeated in the same manner to configure the amplifier 122 _{1 having} the coefficient a ₁ of the first chip of the PN code, and add the values obtained by adding all the amplifier outputs by the adder 123 to the matched filter (M
F). At this time, the amplifiers 122 _{N to} 122 ₁
Is called the number of taps. In a matched filter, the above process is despreading.

In other words, the matched filter is substantially equivalent to continuously (per chip) performing the sliding correlator shown in FIG. Adding all the outputs of the respective amplifiers 122 _{N to} 122 ₁ is equivalent to the integrator 10 in the sliding correlator shown in FIG.
It is equivalent to 2. The detection of the synchronization point is the same as that of the sliding correlator.

A threshold value at the time of detecting a synchronization point using a sliding correlator or a matched filter is a predetermined constant value (for example, 3/3 of the output of the sliding correlator or the matched filter when synchronization is achieved). 4) and a method of dynamically determining the threshold value during operation. However, as a method for detecting a peak most reliably, there is a maximum likelihood detection method in which a maximum output value is selected without setting a threshold value.

FIG. 26 is a block diagram showing a configuration for performing maximum likelihood detection using a conventional sliding correlator. In the figure, the same parts as those in FIG. 23 are denoted by the same reference numerals, but since they have an N-stage parallel configuration, the number of stages is given as a subscript. 1
31 is a maximum likelihood detection unit. An output from the PN generator 103 is input to the binary delay elements 132 _{1 to} 132 _N−1 in series,
The PN code is shifted. Multipliers 101 _{1 to} 101 _N perform sliding correlation for a predetermined time length with respect to each shifted timing, integrate their outputs with integrators 102 _{1 to} 102 _N , respectively, and perform maximum likelihood detection. In the section 131, the timing at which the maximum integrated output is obtained indicates the synchronization point.

Each shift amount of the binary delay elements 132 _{1 to} 132 _N−1 is set to one chip period Δ. In this case, sliding correlators (multipliers,
An integrator). When oversampling is performed, if the p-times oversampling is performed, the shift amount of the binary delay element is Δ / p, and the number of necessary sliding correlators is N × p. When a matched filter is used instead of the sliding correlator, each sliding correlator is replaced with an individual matched filter as a first realization circuit. As a second realizing circuit, one matched filter of N taps and a register or memory of N chips for sequentially accumulating the output are prepared. If the method of comparing the outputs of the N chips is used, the circuit scale can be reduced although the immediacy is inferior. The above-described maximum likelihood detection method is superior in the anti-fading characteristics as compared with the method in which the determination threshold is fixed.

In any of the above-described methods, any method may be used as long as the spreading code has a short period of up to about 1024. However, a problem arises when a long-period code such as 32768 (= 2 ¹⁵ ) is used. For example, when acquiring synchronization in a fading environment in a sliding correlator, a method of keeping the threshold constant is out of the question, and a method of dynamically determining the threshold during operation is:
Not applicable for long periods. Therefore, in order to apply the above-described maximum likelihood detection method, it is necessary to prepare at least N sliding correlators corresponding to the period length of the PN code.
The integration time (dwell time) is 1
This is usually too time-consuming to do over a cycle,
It is usual to terminate the integration at an appropriate time. As a result, the false alarm probability (false synchronization probability) is worse than in one cycle.

Next, in the case where a matched filter is employed, when considering synchronization in a fading environment, the method of keeping the threshold constant is out of the question.
In addition, a method of dynamically determining during operation requires preparing a matched filter in which the number of taps is one cycle, so that it is not realistic in a long cycle in terms of circuit scale. Even if the above-described second realization circuit of the maximum likelihood detection method is employed, it is not realistic to prepare a matched filter having the number of taps for a long period. Since the output observation period (correlation detection period) is long, the fading condition changes at the beginning and end of the observation time, and the detection is no longer the maximum likelihood detection.

Therefore, there is a method of selecting a maximum output point by parallelizing a plurality of matched filters in order to speed up synchronization acquisition. When the spread code length exceeds the product of the length and the number of matched filters, the observation period of the matched filter output needs to be longer than the length of the matched filter.

FIG. 27 is a block diagram of a conventional spread code synchronizing apparatus using a parallel matched filter. In the figure, 210 _{1 to} 210 _J-1 are matched filters,
211 is a maximum value selection and threshold value comparison unit. FIG.
FIG. 28 is an explanatory diagram of a method of creating a code used in the synchronization capturing apparatus shown in FIG. Although a PN (Pseudo Noise) code is used as the spreading code, another spreading code may be used. FIG. 29 is a diagram for explaining the operation of a specific example of the synchronization acquisition apparatus shown in FIG.

First, with reference to FIG. 28, a description will be given of a method of creating a code used as a matched filter coefficient. Let the length of the spreading code be N chips and the number of matched filters be J. Divide the spreading code into J frames. next,
Each frame is divided into matched filter length K blocks. Here, M blocks are formed in one frame. Let the code of the last block of each frame be the coefficient of each matched filter 210 _{1 to} 210 _{J −1} . This will be described using equations. When the spreading code of code length N used in the spread spectrum communication system is C, and this is represented by a vector, the following expression is obtained. C = (c ₀ , c ₁ , ..., c _N-1 ) First, this is equally divided into J frames, and the blocks obtained by dividing the blocks into M blocks are represented by vectors. It becomes an expression. Where the subscript j is the j-th frame,
The subscript m means the m-th block. Here, j = 0,
1, ..., J-1, m = 0, 1, ..., M-1. G _{j, m} = (c _{jMK + mK} , c _{jMK + mK + 1} , ..., c _{jMK + mK + K-1} )

From the above, the following blocks are respectively used as matched filters 210 ₀ and 21 shown in FIG.
0 ₁ ,..., 210 are selected as coefficients of _J-1 . G _{0, M−1} , G _{1, M−1} ,..., G _{J−1, M−1 The} specific example shown in FIG. 29 is an example when J = 4, M = 4. Matched filters 210 ₀ , 210 ₁ , 21
The following blocks in the spread code are selected as the coefficients of O ₂ and 210 ₃ . G _0,3 , G _1,3 , G _2,3 , G _3,3 Returning to FIG. Synchronous acquisition is performed in two stages, an acquisition mode and a confirmation mode. In capture mode,
The received spread spectrum signal r (t), which is spread spectrum by the PN code on the transmission side, is input in parallel to _J matched filters 210 ₀ ,..., 210 _J-1 .
From each matched filter 210 ₀ ,..., 210 _J−1 , 1
A partial despread result by the matched filter coefficient is output for each chip time.

The maximum value selection and the threshold comparator 211, the matched filter 210 _0, ..., 210 of the _J-1 of the output power, matched filter output and the maximum value, the maximum value,
Further, the timing at which the maximum value is output is specified, and the information is held. When a certain matched filter output is larger than the held maximum value, the held maximum value, matched filter, and timing information are updated. This is repeatedly performed in the observation period (1 frame M chip time), and the timing at which the maximum value is output is a candidate for the code synchronization point.

In the above-mentioned M chip time, the maximum value is detected and, at the same time, the maximum value is compared with a threshold value. If the maximum value is not compared with the threshold value, the maximum value will not always be the correct synchronization point due to the effects of fading and noise. It will move to. The average value of the output power of the matched filters of all the matched filters 210 ₀ ,..., 210 _J-1 at all the timings is taken, and multiplied by a certain coefficient γ ₀ to obtain a threshold γ ₁ . If the maximum value described above exceeds the threshold value gamma _1, the timing of taking the maximum value as a synchronization point in the acquisition mode, transitions to the confirmation mode. On the other hand, if the threshold value is not exceeded, the capture mode is restarted.

Here, the reason why the threshold value γ ₁ is not made constant is to follow a fading environment or the like. The received signal level fluctuates due to fading, and also varies depending on the distance from the transmitter. Therefore, as described above, definitive time to time, and determines the threshold value gamma ₁ with reference to the whole of the matched filter output. However, the coefficient γ ₀ is
The optimum value must be determined in advance by analysis using simulation or the like and fixed. However, if the coefficient γ ₀ is too high, the maximum value may not exceed the threshold. Since the upper limit is set for the number of times of re-synchronization, when the limit is reached, the maximum value at that time is used as the synchronization point. However, the timing to take the maximum value at this time is
It is not always the synchronization point. On the other hand, if the coefficient γ ₀ is too low, the threshold will always be exceeded,
There is no point in setting a threshold. Therefore, the coefficient γ ₀ is
The optimum value changes depending on the signal-to-noise ratio (SNR) at that time.

In the confirmation mode, a correlation output is obtained by multiplying and integrating the received spread spectrum signal and the spread code on the receiver side by the synchronization timing determined in the acquisition mode by the sliding correlator. The integration time is set to, for example, one to several cycles when the spreading code is a short code, and to a predetermined fraction of one cycle when the spreading code is a long code. This correlation detection is repeated A ₀ times. Correlation output value, the number of times exceeding a certain threshold value gamma ₂ is not less than _one A, the synchronization point was correct, the process proceeds to the normal receive mode of operation (operation mode). If not, start over from capture mode.

The threshold value in the above-described confirmation mode is also made variable according to the power level of the received signal. For example, another matched filter that multiplies with a spreading code whose synchronization timing has been removed is used, and a threshold value that is a multiple of a value obtained by taking the time average of the integrated output is used. In the confirmation mode, any _one of the parallel matched filters 210 ₀ ,..., 210 _J-1 can be used as a substitute for the sliding correlator.

As described above, in order to improve the performance of the synchronization acquisition mode, it is better to change the coefficient γ ₀ according to the signal-to-noise ratio at each time. However, this is not possible because the synchronization must be captured first in order to estimate the signal-to-noise ratio. Therefore, the coefficient γ ₀
Must select a signal having a relatively good characteristic over the entire expected signal-to-noise ratio. Therefore, when the signal-to-noise ratio is deteriorated, the number of erroneous acquisitions in the synchronous acquisition mode increases, and the number of operations of once entering the confirmation mode and returning to the acquisition mode increases. Confirmation mode, in order to increase the reliability, because the relatively large design integration time and or number of repetitions A ₀ described above, takes a relatively long processing time. Therefore, there is a problem that the synchronization acquisition time increases as a result of switching between the confirmation mode and the acquisition mode.

[0022]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a small circuit scale, and enables high-speed and high-accuracy synchronization acquisition of a spread code. It is intended to provide a device. It has excellent anti-fading characteristics, and is particularly suitable for a direct spread spectrum spread communication system using a long-period signed sequence.

[0023]

According to the first aspect of the present invention, there is provided a method for acquiring synchronization of a spread code which establishes synchronization between a received signal which has been spread spectrum by a spread code and the spread code on a receiving side. The spread code is divided into J frames, and a plurality of block-divided spread codes generated by dividing the code into M blocks are added to the codes corresponding to the positions in the block for each of the frames. Number of multi-level block division spreading codes are generated, and by performing correlation detection between the J number of multi-level block division spreading codes and the received signal in parallel, the multi-level block providing the maximum correlation value is obtained. Specifying a coded block division spreading code and a first intra-block phase, and specifying the block of M blocks in the frame in which the specified multi-valued block division spreading code is generated. The divided spread code, as it is, or after advancing the phase to the subsequent block divided spread code, is further subdivided into J frames, and the block divided spread code in a plurality of divided subdivided spread codes is By performing correlation detection with the received signal in parallel, the block division spreading code that gives the maximum correlation value and the second intra-block phase are specified, and the first and second intra-block phases match. Sometimes, it detects that there is a synchronization point in the phase in the second block of the specified block division spreading code. Therefore, by performing correlation detection in parallel, it has excellent anti-fading characteristics,
Enables good synchronization acquisition. Since the block division spreading code is multi-valued, synchronization acquisition can be speeded up with a small circuit scale.

According to a second aspect of the present invention, in the method for acquiring synchronization of a spread code which establishes synchronization between a received signal spread spectrum by a spread code and the spread code on the receiving side, the spread code is set to a J frame. , And by adding a plurality of block division spread codes generated by dividing into M blocks to each of the codes corresponding to the positions in the block for each frame, J first multiplications are performed. A plurality of the block division spreading codes corresponding to the block positions corresponding to the block positions in each of the frames, in which the coded block division spreading codes are generated, are assigned to the block positions corresponding to the respective block positions. Are added to generate M second multi-level block division spreading codes, and the J first multi-level block division spreading codes and the reception code And the first multi-level block-divided spreading code that gives the maximum correlation value and the phase within the first block are specified, and the M second multi-levels are detected. The correlation detection between the generalized block division spreading code and the received signal is performed in parallel, the second multi-valued block division spreading code that gives the maximum correlation value and the second intra-block phase are specified, 1, when the phases in the second block match, in the frame that generated the specified first multi-level block division spreading code, the specified second multi-level block division spreading in the frame. It is to detect that there is a synchronization point in the phase in the second block of the block division spreading code at the block position where the code is generated. Therefore, by performing the correlation detection in parallel, the anti-fading characteristic is excellent, and good synchronization acquisition is enabled. Since the block division spreading code is multi-valued, synchronization acquisition can be speeded up with a small circuit scale. Since the block division spreading code converted into a multivalued matrix is used, high-speed processing can be realized in two stages.

According to a third aspect of the present invention, in the synchronization acquisition method according to the first or second aspect, a plurality of block divisions generated by dividing the spread code into J frames and further dividing the spread codes into M blocks. In place of the spreading code, a partial spreading code forming a part of each of the block division spreading codes is used. Therefore, since the code length for performing the correlation detection is reduced, the number of taps of the matched filter used for the correlation detection can be reduced, and the processing load and the circuit scale are reduced.

According to the fourth aspect of the present invention, a J signal for receiving a spread spectrum signal by a spread code is input.
Spread detector comprising: a plurality of correlation detectors; a maximum likelihood detector for comparing correlation values of the J correlation detectors over a predetermined time; a count storage unit for storing coefficients of the J correlation detectors; In the code synchronization acquisition apparatus, the coefficient storage unit divides the spread code into J frames, further divides the spread code into M blocks, and generates a plurality of block-divided spread codes for each frame. J first codes generated by adding codes having corresponding positions
And stores the multi-valued block division spreading code of
In the first step, the control unit sets the J number of first multilevel block-divided spreading codes stored in the coefficient storage unit to the J number of correlation detectors, and The detectors respectively perform correlation detection of the received signal and the first multi-level block division spreading code in parallel, and the maximum likelihood detector outputs the maximum correlation value with the correlation detector. And the control unit specifies the first multilevel block-divided spreading code that gives the maximum correlation value and the first intra-block phase based on the output of the maximum likelihood detector. And predicting that there is a synchronization point in the phase in the first block in one of the block division spreading codes in the frame in which the specified first multi-valued block division spreading code is generated. . Therefore, by performing correlation detection in parallel,
It has excellent anti-fading characteristics and enables good synchronization acquisition. Since the block division spreading code is multi-valued, synchronization acquisition can be speeded up with a small circuit scale. Correlation detection can be easily performed in parallel.

According to a fifth aspect of the present invention, in the spread code synchronization acquisition apparatus according to the fourth aspect, the coefficient storage section stores the specified first multi-level block division in the first stage. The block division spreading code of the M block in the frame in which the spreading code is generated, as it is, or after advancing the phase to the subsequent block division spreading code, is further divided into J frames, and the divided And selecting and storing one block division spreading code from each frame. In a second stage, the control unit determines the J number of the block division spreading codes stored in the coefficient storage unit. The spreading codes are
The J correlation detectors are set, and each of the correlation detectors is:
In each case, the correlation detection between the received signal and the selected block division spreading code is performed in parallel, and the maximum likelihood detector outputs the correlation detector and the timing that output the maximum correlation value, The control unit specifies the selected block division spreading code that gives the maximum correlation value and a second intra-block phase based on the output of the maximum likelihood detector, and controls the first and second blocks. When the inner phases match, it is to detect that there is a synchronization point in the specified second intra-block phase of the selected block division spreading code. Therefore, the second step can be easily performed using the block division spreading code.

According to a sixth aspect of the present invention, in the apparatus for acquiring a spread code according to the fourth aspect, the coefficient storage unit stores the specified first multi-level block division in the first stage. The block division spreading code of the M block in the frame that generated the spreading code, as it is, or after advancing the phase to the subsequent block division spreading code, re-divided into J frames, and the re-divided A block for storing J second multi-level block-divided spreading codes generated by adding the codes corresponding to the positions in the block to each other for each re-divided frame. And in the second stage,
The control unit sets the J second multi-valued block division spreading codes stored in the coefficient storage unit to the J correlation detectors, respectively, and the correlation detectors respectively Performing correlation detection between the received signal and the second multi-level block division spreading code in parallel, and the maximum likelihood detector outputs the correlation detector that has output the maximum correlation value and the timing. , The control unit is configured to generate, based on an output of the maximum likelihood detector, the second multi-level block division spreading code that gives the maximum correlation value,
It specifies that there is a synchronization point in the second block phase in the two block division spreading codes, and when the first and second blocks have the same phase, shifts to the next step of synchronization point detection. is there. Therefore, the correlation detection processing can be speeded up by using the multi-valued block division spreading code many times.

[0029] According to the present invention, a plurality of correlation detectors for inputting a received signal spectrum-spread by a spreading code, and a maximum likelihood detector for comparing correlation values of the plurality of correlation detectors over a predetermined time period A synchronization storage device for a spread code, comprising: a count storage unit for storing coefficients of the plurality of correlation detectors; and a control unit, wherein the coefficient storage unit divides the spread code into J frames, J first multilevel binarization generated by adding a plurality of block division spread codes generated by dividing into blocks to codes corresponding to positions in the block for each frame. A block division spreading code and a block division spreading code corresponding to a block position in each frame correspond to a code corresponding to a position in the block for each block position. And M second multi-valued block division spreading codes generated by adding the numbers, and wherein the control unit stores the J first multi-valued block division spreading codes stored in the coefficient storage unit. Are set to the J number of correlation detectors, respectively, and each of the correlation detectors calculates a correlation between the received signal and the first multi-level block division spreading code. Performing the detection in parallel, the maximum likelihood detector outputs the correlation detector that has output the maximum correlation value, and the timing, and the control unit is configured to control the M number of Mth stored in the coefficient storage unit. 2 are respectively set to the M number of the correlation detectors, and each of the correlation detectors is configured to transmit the received signal and the M number of the second multi-level block division spreading codes respectively. Perform correlation detection with the code in parallel, the maximum likelihood detector The outputs correlation detector and timing of outputting the maximum correlation value,
The control unit specifies the first multi-level block-divided spreading code that gives a maximum correlation value and a first intra-block phase based on an output of the maximum likelihood detector, and The second multi-level block division spreading code for giving a value and a second intra-block phase are specified,
When the phase in the second block matches, the specified second multi-level block division spreading code in the frame that generated the specified first multi-level block division spreading code. At the block position that generated
It is to detect that there is a synchronization point in the phase in the second block of the block division spreading code. Therefore, high-speed processing can be realized in two stages because the block-divided spreading code converted into a multi-value matrix is used.

In the invention according to claim 8, in the spread code synchronizing acquisition apparatus according to any one of claims 4 to 7, the coefficient storage unit includes: The coefficient for performing correlation detection over a period is also stored, and the control unit is configured to store the coefficient stored in the coefficient storage unit when performing correlation detection over one period of the correlation detection. The correlation value is newly set in the correlation detector, and the correlation value is synchronously added to the maximum likelihood detector. Therefore, since the maximum value obtained by synchronous addition over a plurality of synchronization detection periods is obtained, detection accuracy is improved.

According to a ninth aspect of the present invention, in the synchronization acquisition apparatus according to any one of the fourth to eighth aspects, the spread code is divided into J frames and further divided into M blocks. In place of the plurality of block division spread codes, a partial spread code forming a part of each of the block division spread codes is used. Therefore, the code length for performing the correlation detection is reduced, so that the processing load and the circuit scale are reduced.

In a tenth aspect of the present invention, in the method for acquiring a spread code synchronously, a plurality of partial spread codes different from each other are extracted from a plurality of partial spread codes respectively extracted from a plurality of portions of the spread code. A group of a plurality of multilevel partial spreading codes is generated by combining and adding, and further, by performing the generation for a plurality of different combinations, a plurality of groups of the multilevel partial spreading codes are generated. The received signal subjected to spectrum spreading by the spreading code, and the correlation detection between each of the multi-valued partial spreading codes of each group, the maximum correlation value for each group, the multi-valued partial spreading code, An offset timing is detected, and when the offset timings match for the plurality of groups, it is determined that there is a synchronization point. Therefore, since the partial spreading code is multi-valued, the speed of synchronization acquisition can be increased with a small circuit scale. Since each partial spreading code is multi-valued in a plurality of ways, a plurality of offset timings are compared by detecting a plurality of types of correlations in different groups, thereby confirming that the determined synchronization point is correct. Since the probability of returning to the acquisition mode from the confirmation mode or the like is reduced, the synchronization acquisition time is shortened as a result. When the correlation detection is performed in parallel, the anti-fading characteristic is excellent, and good synchronization acquisition is enabled.

According to the eleventh aspect of the present invention, in the method of acquiring a spread code according to the tenth aspect, the plurality of portions of the spread code are portions separated from each other.
Therefore, the proportion of the partial spreading code in the spreading code decreases due to the separated portion, and the total number of codes for performing the correlation detection decreases, thereby reducing the circuit scale. It is even better if they are evenly spaced because the time until the partial spreading code is correlated is uniform.

According to a twelfth aspect of the present invention, in the method for acquiring synchronization of a spread code, the spread code is divided into J _r frames, each frame is divided into J _c blocks, and each block is divided into J _c blocks. Divided into multiple sub-blocks,
By using the predetermined sub-block in each divided block as a partial spreading code and adding the partial spreading codes in each of the blocks in the frame for each frame, J _r row multiplications are performed. A value-added partial spreading code is generated, and for each of the blocks, J _c column multi-valued partial spreading codes are generated by adding the partial spreading codes of the block in each of the frames. And performing a correlation detection between the received signal spectrum-spread by the spreading code and the row multi-level partial spreading code to give a maximum correlation value.
The offset timing is specified, and the correlation between the received signal and the column multi-level partial spreading code is detected, and the maximum correlation value is given. The column multi-level partial spreading code and the second offset timing Is specified, and the first,
When the second offset timings match, it is determined that there is a synchronization point. Therefore, since the partial spreading code is multi-valued, the speed of synchronization acquisition can be increased with a small circuit scale. Since the combination for multi-value processing is systematically performed, the processing is simplified. By comparing the two offset timings, it is confirmed that the determined synchronization point is correct. Since the probability of returning to the acquisition mode from the confirmation mode or the like is reduced, the synchronization acquisition time is shortened as a result. When the correlation detection is performed in parallel, the anti-fading characteristic is excellent, and good synchronization acquisition is enabled.

According to a thirteenth aspect of the present invention, in the synchronization acquisition method according to the twelfth aspect, the correlation detection between the row multi-level partial spreading code and the column multi-level partial spreading code is performed for a plurality of block times. For the detection of the correlation at each block time when performing over, the row multi-valued partial spreading code and the column multi-value The row multi-level partial spreading code and the first offset timing that provide the maximum correlation value, and the column multi-level partial spreading code that provides the maximum correlation value And the second offset timing are determined by synchronous addition in units of one block. Therefore, when the coincidence of the offset timings is checked, the S / N ratio is improved by using the synchronous addition together, so that the determination accuracy can be improved. Further, it is easy to set the column multi-level partial spreading code and the row multi-level partial spreading code at the time of synchronous addition.

According to a fourteenth aspect of the present invention, in the synchronization acquisition method according to the twelfth or thirteenth aspect, correlation detection with the row multi-level partial spreading code and the column multi-level partial spreading code, and The determination of the first and second offset timings is performed at an integral multiple of the chip timing of the spreading code, and the first and second offset timings are coincident when they are within a predetermined range. It is to judge. Therefore, the coincidence of the offset timing can be determined strictly. If it is too strict, the criterion can be easily changed.

According to a fifteenth aspect of the present invention, in the spread code synchronization acquisition apparatus, a plurality of groups of correlation detectors for inputting the received signals spectrum-spread by the spread codes, and the coefficients of the plurality of groups of correlation detectors are inputted. A coefficient storage unit for storing, and a synchronization acquisition device for a spread code having a determiner that receives an output of the plurality of groups of correlation detectors as inputs, wherein the coefficient storage unit is configured to perform a plurality of operations from a plurality of portions of the spread code. A group of a plurality of multi-valued partial spreading codes generated by combining the extracted plurality of partial spreading codes with the plurality of different partial spreading codes and adding the vectors are generated for a plurality of different combinations. The plurality of groups of the multi-level partial spreading codes are stored, and the correlation detectors of the respective groups are set with the multi-level partial spreading codes of the respective groups, and The correlation detection between the received signal subjected to spectrum spreading and the multi-level partial spreading code of each group is performed, and the determiner gives, for each of the groups, the maximum correlation value. A spread code and an offset timing are detected, and when the offset timings match for a plurality of groups, it is determined that there is a synchronization point. Therefore, since the partial spreading code is multi-valued,
Synchronous acquisition can be speeded up with a small circuit scale.
By comparing a plurality of offset timings, it is confirmed that the determined synchronization point is correct. Since the probability of returning to the capture mode from the confirmation mode etc. decreases,
As a result, the synchronization acquisition time is shortened. In addition, when the correlation detection is performed in parallel, the anti-fading property is excellent,
Enables good synchronization acquisition.

According to a sixteenth aspect of the present invention, in the spread code synchronization acquiring apparatus according to the fifteenth aspect, the plurality of portions of the spread code are portions that are separated from each other.
Therefore, the proportion of the partial spread code in the spread code decreases, and the total number of codes for performing the correlation detection decreases, thereby reducing the circuit scale. If they are evenly spaced, the time until the partial spreading code is detected as a correlation becomes uniform.

According to the seventeenth aspect of the present invention, in the synchronization acquisition device, J _r row correlation detectors and J _c for inputting the received signal spectrum-spread by the spreading code.
Column correlation detectors, a coefficient storage unit that stores coefficients of the row correlation detector and the column correlation detector, and a determiner that receives outputs of the row correlation detector and the column correlation detector as inputs. In the spread code synchronization acquisition apparatus, the coefficient storage unit divides the spread code into J _r frames, divides each frame into J _c blocks, and divides each block into a plurality of sub-blocks. , And the predetermined sub-block in each divided block is used as a partial spreading code, and for each frame, generated by adding the partial spreading codes in each of the blocks in the frame. J and _r rows multilevel portion spreading code for each said block, said portion J _c number column multilevel moiety generated by adding a spread code to each other of the block within each frame And the row correlation detector, respectively, wherein the row multi-level partial spreading code is set, and performs correlation detection between the received signal and the row multi-level partial spreading code. Correlation detector, respectively, the column multi-level partial spreading code is set, performs a correlation detection between the received signal and the column multi-level partial spreading code, the determiner, the row correlation detector of each row The correlation values are compared, the maximum correlation value is output, the row correlation detector and the first offset timing are specified, and the correlation values of the column correlation detectors are compared to determine the maximum correlation value. The output, the column correlation detector and the column-side offset timing are specified, and when the first and second offset timings match,
It is determined that there is a synchronization point. Therefore, since the partial spreading code is multi-valued, it is possible to speed up the acquisition of the synchronization with a small circuit scale. Processing is simplified because it is organized. By comparing the two offset timings, it is confirmed that the determined synchronization point is correct. Since the probability of returning to the acquisition mode from the confirmation mode or the like is reduced, the synchronization acquisition time is shortened as a result. When the correlation detection is performed in parallel, the anti-fading characteristic is excellent, and good synchronization acquisition is enabled.

In the eighteenth aspect of the present invention, in the spread code synchronizing apparatus according to the seventeenth aspect, the coefficient storage section includes a plurality of row detection units and a plurality of column correlation detection units. When performing at the block time, for detecting the correlation at each block time, the row multi-valued partial spreading code and the row multi-valued partial spreading code generated for each of the spreading codes advanced one block at a time exceeding one block time The column multi-level partial spreading code is stored, and every time the one block time is exceeded, the row correlation detector sets the row multi-level partial spreading code for correlation detection at each block time. The column correlation detector is configured to set the column multilevel partial spreading code for correlation detection at each block time, and the determinator performs the row correlation detection. And an output of said column correlation detector is for synchronously adding one block as a unit. Therefore, determination accuracy can be improved by synchronous addition. Further, it is easy to set the column multi-level partial spreading code and the row multi-level partial spreading code at the time of synchronous addition.

According to a nineteenth aspect of the present invention, in the synchronization acquisition device according to the seventeenth or eighteenth aspect, the row correlation detector and the column correlation detector perform correlation at an integral multiple of a chip timing of the spread code. Performing the detection, the determiner compares the correlation output at an integer multiple of the chip timing of the spreading code, and determines when the first and second offset timings are within a predetermined range. It is determined that there is. Therefore, the coincidence of the offset timing can be determined strictly.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a synchronization acquisition apparatus according to the first to third embodiments of the present invention. The correlation detector is realized by a matched filter. In the figure, 1 ₁ to 1 _J is a memory for storing the spreading code of the multilevel or binary. 2 _{1 to} 2 _J are matched filters (MF: Matched Filt) that take a correlation with a received spread spectrum signal using a multi-level or binary block division spreading code as a coefficient.
er). Reference numeral 3 denotes a maximum likelihood detector that specifies a matched filter that obtains a maximum output at any timing during an observation period of a predetermined correlation detection, and a phase at which the maximum output is obtained (block division when the maximum value is obtained). The position of the chip in the spread code) is detected and recorded. As a result, it is found that there is a synchronization point in the phase at which the maximum output of the block division spreading code used for the coefficient of the matched filter that has obtained the maximum output. A control unit 4 controls each block.

It is assumed that the received signal is directly spread by a spreading code whose code length N is an integer power of 2. However, this condition is a condition for simplifying the configuration and operation of the synchronization acquisition device, and is not limited in principle to an integer power of 2. The received spread spectrum signal is usually converted into a baseband band, and a digitally modulated signal that has passed through a bandpass filter is input as an I or Q component output based on the carrier phase. This synchronization acquisition device
The spread code P is divided into blocks, taking the configuration for detecting the maximum likelihood using the J matched filters 2 ₁ to 2 _J, and performs synchronization acquisition by performing a two-step or more processes.

As a coefficient for the first stage, a spreading code P
Is divided into J frames, which are further divided into M blocks. A J × M block-divided spread code (1 block K chip) generated for each frame is assigned a code ( by adding chips) with each other to generate the J multilevel block division spread code, stored in the memory 1 ₁ to 1 _J. As a first step, J-number of multi-level block division spreading code matched filter 2 ₁ to 2 _J
The received spread-spectrum signal is input as a coefficient, and correlation detection is performed in parallel, and one frame is specified by maximum likelihood detection. In this way, the candidates for the synchronization points are narrowed down to the intra-block phases in the M block division spreading codes constituting the specified frame.

In the second stage, one synchronization point is specified from a plurality of candidates. The second stage differs depending on the first to third embodiments. In any of the first and second stages of any of the above-described embodiments, a feature is that a phase in a block serving as a synchronization point in one block division spreading code is predicted. Therefore, when the phase in the block at the synchronization point predicted in the first stage does not match the phase in the block at the synchronization point predicted in the second or higher stage, it is determined that the synchronization point cannot be detected.
The synchronization acquisition operation is performed again from the first stage.

FIG. 2 shows a first stage of each embodiment of the present invention.
Concept of Generating Multi-level Block Dividing Spread Codes Used in FPGA
FIG. This multilevel block division spreading code is shown in FIG.
J matched filters 2 shown ₁~ 2_JUsed as the coefficient of
Used. First, in direct spread spectrum spread communication,
The spreading code of the code length N to be used is represented by a vector,
Let P be the following equation. P = ｛c₁, C_Two, ………, c_N｝ Where the vector element c₁, C_Two, ………, c_NIs
This is a code that constitutes a scattered code.
Take.

The spreading code P is first matched with the matched filter 2
_{It is} equally divided into J frames corresponding to the number of _{1 to} 2 _J. Further, each frame is equally divided into M blocks. Each partial spreading code sequence that has been equally divided is hereinafter referred to as a block-spreading code.
_{j and m} . G _{j, m} = ｛c _{(j-1) JK + (m-1) K + 1} ,..., C
_{(j-1) JK + (m-1) K + K}添 The subscript j indicates the j-th frame, and the subscript m indicates the m-th block. If the number of codes constituting each block is K, then K = N / (J × M).

The J spreading codes used as the coefficients of the matched filters 2 ₁ to 2 _J in the first stage are hereinafter referred to as multi-value block division spreading codes. This multi-valued block division spreading code is represented by a vector notation, and F _j (j = 1,...,
J). The multi-level division spreading code F _j is calculated for each frame j
Each time, it is generated by vector-adding all the block division spreading codes G _{j, m} described above. _{F j = G j, 1 +} G j, 2 + ......... + G j, M i.e., each block divided spreading codes G _j belonging to each frame _{j, 1, G j, 2} , ........., G j, M The value of each element of F _j is obtained by arithmetically adding the same vector elements to each other. In other words, F _{j is} obtained by arithmetically adding codes corresponding to positions in the same block.
Are obtained. The code that constitutes F _j is
It becomes a multivalued number. Multi-level block division spreading code F _j (j =
A specific example of the case 1) is as follows.

G _1,1 = {c ₁ , c ₂ , c ₃ ,..., C _K } G _1,2 = {c _{K + 1} , c _{K + 2} , c _{K + 3} ,. c _2K Ｇ G _1,3 = ｛c _{2K + 1} , c _{2K + 2} , c _{2K + 3} ,..., c _3K ｝ G _{1, M} = ｛c _{( M-1) K + 1,} c (M-1) K + 2, c (M-1) K + 3, ........., c MK} F 1 = {c 1 + c K + 1 + c 2K + 1 + ……… + c _{(M-1) K + 1} , c ₂ + c _{K + 2} + c _{2K + 2} + ……… + c _{(M-1) K + 2} , c ₃ + c _{K + 3} + c _{2K + 3} + …… … + C _{(M-1) K + 3} , c _K + c _2K + c _3K + ……… + c _MK ｝

FIG. 3 is a conceptual diagram of a method of generating a spread code used in the second stage in the first embodiment of the present invention. The spreading codes are also used as the coefficient of the J matched filters 2 ₁ to 2 _J shown in FIG. In the first stage, the maximum output is obtained in the v-th matched filter 2 _v. As a result, as will be described later, the synchronization point can be predicted to be in any one of the block spreading codes G _{v, 1} , G _{v, 2} ,..., G _{v, M} constituting the frame v. Therefore, in the second stage, in order to find a synchronization point from among them, M block division spreading codes G _{v, 1} , G _{v, 2} ,..., G _{v, M} in frame v are J-divided. Then, for example, the last block division spreading code of each division group is used as a coefficient in the second stage. When the M block division spreading codes are J-divided, each frame becomes S
(= M / J) block division spreading codes. Therefore, the last block division spreading code used is S
This is the first block division spreading code.

However, when the process proceeds from the first stage to the second stage, after the correlation detection time (standby time) corresponding to one block length in the first stage is completed, the reception spectrum is performed in the second stage. You will be waiting for a spread signal. In consideration of this, according to the elapsed time corresponding to one block length required for standby in the first stage, the first passed block division spreading code G _{v, 1} is discarded, and the block division spreading code The sequence is obtained by advancing the phase by one block.
From the block sequences G _{v, 2} , G _{v, 3} ,..., G _{v, M} , G _{v + 1,1} shown in FIG.
Newly set to the coefficients of the J matched filters 2 ₁ to 2 _J. More specifically, in the figure, each of the block-divided spreading codes G _{v, S + 1} , G _{v, S + 2} ,..., G _{v, (J−1) S + 1} , G _v the _Tasu1,1 as a coefficient in the second stage, respectively, set for each matched filter 2 ₁ to 2 _J. In the illustrated example, 1
Although the block is shifted, it can be shifted by 2 blocks or 3 or more blocks.

FIG. 4 is a flowchart for explaining the operation of the first embodiment of the present invention. FIG. 5 is an explanatory diagram showing a specific example of the operation in the first stage in the first to third embodiments of the present invention. FIG. 6 is an explanatory diagram showing a specific example of the operation of the second stage in the first embodiment of the present invention. In a specific example, the code length of the original spread code is N = 2 ¹² = 4096, the number of frames J = 4, the number of blocks M = 16, the number of codes in a block K = 64, the number of blocks S in the second stage = 4 This is an example.

In step S11, the first stage is started, and the control unit 4 shown in FIG. 1 reads out the multi-valued block division spreading code from the memories ₁₁ to 1 _J , and each of the J matched filters 2 _1. It is set as the coefficient of ~2 _J. S12
In, J-number of matched filters 2 ₁ to 2 _J has on the received spread spectrum signal, one block (K PN code
And correlation detection for chip) time, during which the maximum likelihood detector 3 compares the correlation value of the J matched filters 2 ₁ to 2 _J. In S13, the maximum likelihood detector 3 specifies the frame v of the matched filter having the maximum correlation value within one block time and the phase at which the maximum value is obtained (for example, the correlation v during one block time). The value indicates the number of chips delayed for the maximum value). The above is the first stage, and assuming that the maximum output is obtained in the v-th matched filter 2 _v , the synchronization point is determined in the v-th frame in which the multi-valued block division code F _v was generated. Block division spreading code G
_{v, 1} , _{Gv, 2} ,..., _{Gv, M.} However, since the original block division spreading code is vector-added and the correlation detection is performed using the multilevel block division spreading code, it is affected by mutual interference.

Here, the first example using the specific example shown in FIG.
The steps will be described. The upper row shows the code sequence of the received spread spectrum signals arranged so that the time progresses to the right. 4 blocks the lower represents the matched filter 21 _{to 24} schematically, F ₁ to F ₄ is multi-valued block division spread code used in the first stage as the coefficients of the respective matched filters 21 _{to 24} It is. Below that, the block division spreading code from which each multi-valued block division spreading code is generated is displayed. This figure, in accordance with the progress of the waiting time, while the matched filter ₂₁ to ₂₄ is moved rightward, the manner in which the correlation detection operation captures code sequence of the received spread spectrum signal immediately above is schematically shown I have. To simplify the explanation, the transmission information data is +
It is assumed to be 1.

[0055] During the course of one block (K chips) time, a multi-level block division spread code F ₁ to F ₄ as the coefficients of the matched filter 21 _{to 24,} the block boundary of the received spread spectrum signal is coincident There is a timing to do it. In the illustrated example, a matching from the initial phase phi ₁ chip period elapsed block phase. At this time, the received spread spectrum signal spread by block division spread code G _{2, 2} is received, is input in parallel to each matched filter ₂₁ to _24. Therefore, in this phase, if there is a matched filter using the block division spreading code G _2,2 as a coefficient, the correlation value becomes maximum. In this case, the block division spreading code G
There is no coefficient with _2,2 . However, there is a multi-valued block division spread code F ₂ generated the block division spread code G _{2, 2} are vector addition. Second correlation value of the matched filter 2 ₂ to the multi-valued block division spread code F ₂ and coefficients 1 during the course block K chip time, one of the matched filters 21 _{to 24} takes a correlation value It is the maximum value. Thus, in the illustrated example, the first second matched filters 2 _2, and the block in the phase phi ₁ is specified.

Referring back to FIG. 4, the second stage will be described.
In S14, the control unit 4 of Figure 1, from the memory 1 ₁ to 1 _J, reads the J blocks divided spreading codes corresponding to the frame number v that is specified by the first stage, the J matched filters 2 ₁ It is set as the coefficient of ~2 _J. As described above with reference to FIG. 3, the block division spreading code to be used is J selected for each S from a code string obtained by advancing the block division spreading code belonging to the specified frame v by one block. , G _{v, S + 1} , G _{v, 2S + 1} ,..., G _{v, (J−1) S + 1} , G _{v + 1,1} .

In S15, the J matched filters 2 ₁ to 2 _J wait in this state, and detect the correlation of the received spread spectrum signal over the S block (K × S chip) time, during which the maximum likelihood detector 3 compares the correlation value of the J matched filters 2 ₁ to 2 _J. In S16,
The maximum likelihood detector 3 specifies the block division spreading code based on the matched filter having the maximum correlation value within the S block time, and specifies the intra-block phase φ ₂ having the maximum value. Remember.

In S17, the phase φ ₁ in the block specified in the first stage is compared with the phase φ ₂ in the block specified in the second stage. If the phases match, the process proceeds to S18. In S18, synchronization acquisition is completed. That is, it can be seen that the intra-block phase φ1 of the specified block division spreading code is the synchronization point, and that the receiving side spread code and the received spread spectrum signal are synchronized. On the other hand, when the phases do not match, the process returns to S11 and starts over from the first stage because the reliability is unreliable. This is called a retry. Thereby, the same operation as a plurality of dwells in a sliding correlator is realized. Although omitted in this flowchart, a limit is set on the number of times of retry, and if the limit is exceeded, it is considered that synchronization establishment has failed.

The second stage will be described with reference to the specific example shown in FIG. As in FIG. 5, the upper row is an arrangement of code strings of the received spread spectrum signals such that the time progresses to the right. 4 blocks the lower represents the matched filter ₂₁ to ₂₄ schematically, a block division spread code _{G 2,5, G 2,9, G 2} , 13, G 3,1 is a coefficient of each matched filter is there. G _2,5 , G _2,9 , G _2,13 , G _3,1
Is selected according to the frame number 2 of the matched filter that outputs the maximum value in the first stage shown in FIG.
From among G _2,2 , G _2,3 ,..., G _2,16 and G _3,1 , S =
4 is a block division spreading code selected every four. Although the correlation detection period is S = 4 blocks, this figure shows up to three blocks of a part of the correlation detection section.

[0060] During the course S = 4 blocks (K × S chip) time, there is a phase in which the divided spreading code as the coefficient of each matched filter ₂₁ to _24, the block boundary of the received spread spectrum signal matches . In the example shown in the drawing, the phase coincides with the phase φ ₂ in the block after a lapse of 2K + φ ₂ chips from the initial phase. Therefore, in S = 4 block time, the correlation value of the second matched filter takes the maximum value. As a result, the correlation value becomes maximum in the intra-block phase φ ₂ of the block spreading code G _2,5 . As a result, the received spread-spectrum signal P includes a block spreading code G _{2, 5} belonging to the frame number 2, two blocks (128 chips) from the initial phase + phi ₂ phase after the chip has elapsed is the point synchronization. It can be seen that the phase of the received spread spectrum signal and the phase of the spread code of the synchronization acquisition device are synchronized.

In the above description, the matched filter 2 ₁
~ 2 _J waited for the received spread spectrum signal,
When the present invention is applied to a so-called "block demodulator" that employs a method of searching for a synchronization point for a received spread spectrum signal once stored in a memory, it is not necessary to shift blocks of a block division spreading code. Simply, block division spread code _{G v, 1, G v,} 2, ........., G v, from among _M, a block of each S, by setting the coefficient of the J matched filters 2 ₁ to 2 _J I just need. FIG. 7 is a conceptual diagram of a method of generating a binary spreading code used in the second stage in the second embodiment of the present invention. In the first stage, the synchronization timing is
The block spreading codes G _{v, 1} , G _{v, 2} ,.
.., G _{v, M} could be predicted to exist somewhere, so in the second stage, the spreading code sequence G _{v, 2} , G _{v, 3} ,. The synchronization timing is searched for from G _{v, M} and G _{v + 1,1} . In the second embodiment, the above-described spread code string is equally divided into J frames in exactly the same manner as in the first stage, and each frame is further divided into S frames. In FIG. 7, each of the equally divided block division codes is rewritten as G'j, _m, and the number of blocks constituting each frame is set to M '. M ′ = S. Subscript j is the j-th frame,
The subscript m means the m-th block.

The multi-valued block division spreading codes used as the coefficients of the _J matched filters 2 ₁ to 2 _J used in the second stage are expressed in vector notation F ′ _j (j = 1,..., J )
And The multi-value division spreading code F ' _j is generated by performing vector addition on the block division spreading codes G' _1,1 , G ' _1,2 , ..., G' _{J, M.} F ′ _j = G ′ _{j, 1} + G ′ _{j, 2} +... + G ′ _{j, M} This multi-level division spreading code F ′ _j is used in the same way as in the first stage, as shown in FIG. the coefficients of the matched filter 2 ₁ to 2 _J. In this state, the apparatus waits again, and over a period of one block (K chips), J matched filters 2 _1.
The synchronization point is included in the timing at which the maximum value of the matched filter that takes the maximum value by comparing the correlation values of ２2 _J is obtained.

Assuming that the maximum output is obtained from the matched filter 2 _w, among the block division spreading codes G _{w, 1} , G _{w, 2} ,..., G _{w, M} constituting the frame w in the second stage It can be predicted that there is a synchronization point somewhere in. Using these blocks divided spreading codes, the third stage, again generates a multilevel block division spread code, to set the coefficient of the J matched filters 2 ₁ to 2 _J. Such a process is repeated until the J-divided block division spreading code cannot be multi-valued, that is, until one frame becomes one block division spreading code. If one block division code is obtained, a synchronization point is obtained in the same manner as in the second stage of the first embodiment. During this time, if the phase in the block that takes the maximum value does not match in the middle, a plurality of dwells are realized by retrying from the first stage. The number of steps taken by this method differs depending on the number of times until the coefficient becomes one block division spreading code.

FIG. 8 is a flowchart for explaining the operation of the second embodiment of the present invention. FIG. 9 is an explanatory diagram showing a specific example of the operation at the second stage in the second embodiment of the present invention. The first stage is the same as in the first embodiment. That is, S21 to S23 are the same as S11 to S13 described with reference to FIG. The second stage is started in S24. The control unit 4 in FIG. 1 stores J multi-valued block division spreading codes F′j corresponding to the frame number v specified in the first stage from the memories 11 ₁ to 1 _J into J matched matching codes. Filter 2
It is set as the coefficient of ₁ to 2 _J. In S25, J-number of matched filters 2 ₁ to 2 _J correlates detected over the received spread spectrum signal one block (K chip) time. The maximum likelihood detector 3 includes J matched filters 2 ₁ to 2 _J
Are compared.

In step S26, the maximum likelihood detector 3 specifies the frame w based on the matched filter having the maximum correlation value within one block time, and the intra-block phase φ ₂ having the maximum value. To identify. The above is the second stage, and assuming that the maximum output is obtained in the matched filter w, the synchronization point is the block division spread code G ′ _{w, 1} , G ′ _{w, 2} ,. …
.., G ′ _{w, M ′} .

In S27, the phase φ ₁ specified in the first stage is compared with the phase φ ₂ specified in the second stage. If the two phases match, the process proceeds to S28. If the two phases do not match, the process returns to S21 and starts over from the first stage. S2
In 8, it is determined whether or not the specified frame w can be further J-divided to generate a multilevel block-divided spread code. If it can be generated, the process returns to S24 and the second
The process of the next step similar to the step is repeated, and if it cannot be generated, the process proceeds to S29. It should be noted that a limit is set on the number of redoes, and if the limit is exceeded, it is considered that synchronization establishment has failed. In S29 to S33, the same processes as those in S14 to S18 in the second stage of the first embodiment shown in FIG. The time for correlation detection is the second
It is a frame time in each stage after the stage. When proceeding to S29 at the end of the second stage, in S33, the first stage of frame v, block phase phi ₁ block divided spreading codes in a frame w of the second stage is the synchronization point.

The second stage will be described once again using the specific example shown in FIG. As in FIG. 5, the upper row is an arrangement of code strings of the received spread spectrum signals such that the time progresses to the right. 4 blocks the lower represents the matched filter 21 _{to 24} schematically, F _'1
To F _'4 is a multilevel block division spread code used in the second stage as a coefficient of each matched filter ₂₁ to _24. Below that, the block division spreading code from which each multi-valued block division spreading code is generated is displayed. M
= 16 blocks are divided into J = 4 frames, so that the number M ′ (= S) of block division spreading codes from which each of the multi-valued block division spreading codes F ′ _{1 to} F ′ ₄ is generated is 4
Becomes

[0068] During the course one block time, the multi-valued block division spread code F _'1 to F' ₄ as the coefficients of the matched filter 21 _{to 24,} the block boundary of the received spread-spectrum code, the initial phase And the phase φ ₂ in the block after φ ₂ chip time has passed. At this time, the block division spreading code G _2,3 is received, and each matched filter 2 ₁ is received.
It is inputted in parallel to the 21 to _24. Therefore, the phase φ ₂
In the first method, a divided spreading code F ′ ₁ generated by adding vectors of the block divided spreading codes G _2,3 is used as a coefficient.
Correlation value of the matched filter 2 ₁ becomes the maximum value in either of the matched filter ₂₁ to ₂₄ takes a correlation value over the course of one block time. Therefore, in the illustrated example,
The frame 1 in the second stage and the phase φ ₂ in the block are specified. As a result, in the second stage, the synchronization point is narrowed down to any of the intra-block phases φ ₂ among the block division spreading codes G _2,2 , G _2,3 , G _2,4 , G _2,5 . In the third stage, the block division spreading codes G _2,2 , G _2,3 , G _2,4 , G
Assuming that _2,5 are the coefficients of the matched filter, it is finally found that there is a synchronization point in any block division spreading code,
Synchronous acquisition is completed.

FIG. 10 shows a multi-level block division spreading code F _j used in the first stage and a multi-level block division spreading code used in the second stage in the third embodiment of the present invention. it is a conceptual diagram of a method of generating H _m. In this embodiment, a received signal is temporarily stored in a memory, and is then sent to a block demodulator that searches for a synchronization point in order to avoid processing delay when switching from the first stage to the second stage. An example will be described in which the present invention is applied. For multi-valued block division spread code F _j used in the first stage, is identical to the multilevel block division spread code F _j shown in FIG. Second
Also at the stage, the block division spreading code G _{j, m} G _{j, m} = ｛c _{(j−1) JK + (m−1) K + 1} ,.
_(j-1) Generate a multi-level block division spreading code based on _{JK + (m-1) K + KK} .

However, in the next second stage, FIG.
A matched filter shown in reference M pieces, the matched filter 2 ₁ to 2 _M. If J = M, the configuration may be the same, but if J ≠ M, the number of matched filters to be used is increased or reduced.

[0071] In notation M pieces of multivalued block division spread code _{vector, H m (m = 1,} ........., M) and, set in the coefficient of M matched filters 2 ₁ to 2 _M. Multilevel block division spread code H _m of the second stage, block division spread code G _{1, 1} described above, G _{1, 2,} ........., G _J, from the bit stream of the _M, the vector addition of the following formula Generate. _{H m = G 1, m +} G 2, m + G 3, m + ......... + G J, m i.e., multi-level block division spread code H _m is 10
, A plurality of block division codes G1 _{, m} , G2 _{, m} ,..., Corresponding to the block positions in each frame.
G _{J, M} is obtained by adding the codes corresponding to the positions in the block for each block position, and each vector element of H _m is a multi-valued number.

A concrete example of the case of H _m (m = 1) is as follows. G _1,1 = ｛c ₁ , c ₂ , c ₃ ,..., C _K ｝ G _2,1 = ｛c _{MK + 1} , c _{MK + 2} , c _{MK + 3} , ..., c _{MK + K} ｝ G _3,1 = ｛c _{2MK + 1} , c _{2MK + 2} , c _{2MK + 3} ,..., C _{2MK + K}・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ G _{J, 1} = ｛c _{(J-1) MK + 1} , c _{(J-1) MK + 2} , c _{(J-1) MK + 3} ,..., C _{(J-1) MK + K} ｝ H ₁ = ｛c ₁ + c _{MK + 1 + c 2MK + 1} + ......... + c (J-1) MK + 1, c 2 + c MK + 2 + c 2MK + 2 + ......... + c (J-1) MK + 2, c 3 + c MK + ₃ + c _{2MK + 3} +... + C _{(J-1) MK + 3} , c _K + c _{MK + K} + c _{2MK + K} +... + C _{(J-1) MK + K} ｝ FIG. FIG. 14 is an explanatory diagram of a principle of predicting a synchronization point in the third embodiment. It is assumed that the matched filter having the maximum value is the matched filter 2 _q in the first stage using the multi-level block division spreading code F _j as a coefficient. That is, it is predicted that there is a synchronization point in a plurality of block division spreading codes constituting frame q.
Then, in a second stage using a multi-level block division spread code H _m in the coefficient, the matched filter having the maximum value is assumed to be matched filter 2 _r. That is, the second
It is predicted that there is a synchronization point in a plurality of block division spreading codes constituting the block r of the stage. As a result, the synchronization timing can be captured in a matrix, and it can be seen that the received spread spectrum signal and the spread code P on the receiving side are synchronized in the phase within the block division code _{Gq, r} . However, when the phase in the first stage and the phase in the second stage do not match, the phase is not reliable, so the process is restarted from the first stage. In the case where the synchronization acquisition operation is performed directly while receiving the received signal without using the block demodulator, the processing delay must be considered when moving to the second stage. Generation of the divided spreading code is slightly complicated.

FIG. 12 is a flowchart for explaining the operation of the third embodiment of the present invention. FIG.
FIG. 14 is an explanatory diagram showing, in a specific example, the operation of the second stage in the third embodiment of the present invention. The first stage, S4
1 to S43 correspond to S11 of the first embodiment shown in FIG.
Although the description is omitted because it is similar to S13, it is assumed that the block division spreading code in the frame q has a synchronization point. In S44, the second stage is started. Control unit 4 of FIG. 1 sets a multi-valued block division spread code of the second stage as a coefficient memory 1 ₁ to 1 _M of M matched filters 2 ₁ to 2 _M. In S45, 2 ₁ ~2 _{M M} number of matched filters, on the received spread spectrum signal,
And correlation detection over one block of time, during which the maximum likelihood detector 3 compares the correlation values of M matched filters 2 ₁ to 2 _M. In S46, the maximum likelihood detector 3 specifies the frame number r from the multi-valued matched filter 2 _r having the maximum correlation value within the time of one block, and the phase φ _{2 in} the block having the maximum value. To identify. The above is the second stage. If the maximum output is obtained in the r-th matched filter 2 _r , the synchronization timing is the block division spreading code G _{1, r} , G from which H _r is generated. _It can be predicted that it is somewhere in _{2, r} , ..., G _{J, r} . In step S47, if the first and second in-block phases φ ₁ and φ ₂ match, the process proceeds to step S48 to complete synchronization acquisition. If not, the process is restarted from the first step in step S41.

The second stage will be described with reference to the specific example shown in FIG. The upper row arranges the code string of the received spread spectrum signal such that the time progresses to the right. As described above, in this embodiment, the received spread spectrum signal is stored in a memory not shown in FIG. Lower block, schematic representation of the M = 16 pieces of matched filters _{2 1 ~2 16, H 1 ~H} 16 is
It is a multi-valued block division spread code to be used as coefficients of the matched filter 2 ₁ to 2 ₁₆ in the second stage. Below that,
The block division spreading code from which each multi-level block division spreading code is generated is displayed. Matched filter 2
₂₁ to _16, in the received spread spectrum signal stored in the memory, from the initial phase point that initiated the operation of detecting the synchronization point in the first stage, again inputs the received spread-spectrum signal. The initial phase point to start detecting the synchronization point is
By making them coincide with those in the first stage, it is possible to determine whether the in-frame phases of the synchronization points coincide with each other in the first and second stages.

[0075] From the initial phase point during the lapse of one block (K chips) time, and the multi-level block division spread code as the coefficient of each matched filter 2 ₁ to 2 _16, the block boundary of the received spread-spectrum code, It coincides with the phase φ ₂ within the frame after φ ₂ chip time has elapsed from the initial phase point.
At this time, it is parallelly input is received block division spread code G _{2, 2} to each matched filter 2 ₁ to 2 _16. Thus, the correlation value of the block division spread code G _{2, 2} vectors summed second matched filter 2 _2, generated multilevel block division spread code H ₂ the coefficient is, during the lapse of one block time , one of the matched filters ₂₁ to ₂₄ is the maximum value among the correlation values output. Therefore, in the illustrated example, in the block division spreading code G _2,2 that intersects the frame q = 2 in FIG. 11 predicted in the first stage and the block r = 2 in FIG. 11 predicted in the second stage. The phase φ ₁ (= φ ₂ ) in the block becomes a synchronization point.

In the third embodiment described above, the second stage is executed after the completion of the first stage. Alternatively, the first step and the second step can be performed simultaneously in parallel. The configuration shown in FIG.
Prepared for the stage, the first stage device predicts the frame q described above, and the second stage device predicts the block r =
Predict 2

In the above description of the first to third embodiments, when the synchronization point is predicted in the first stage, the process immediately proceeds to the second stage, and when the synchronization point is detected in the second stage, the synchronization is immediately established. Completed. Instead, the maximum likelihood detection is performed by performing “synchronous addition (ensemble averaging)” over a plurality of correlation detection periods, and, depending on the result, transition from the first stage to the second stage or from the second stage to the synchronization The establishment may be completed.

FIG. 14 is an explanatory diagram of a specific example in the case where synchronous addition is performed in the first stage in the first to third embodiments of the present invention. The upper row shows the code sequence of the received spread spectrum signals arranged so that the time progresses to the right. 4 blocks the lower represents the matched filter 21 _{to 24} schematically, F ₁ to F ₄ is multi-valued block division spread code used in the first stage as the coefficients of the respective matched filters 21 _{to 24} It is. Below that, the block division spreading code from which each multi-valued block division spreading code is generated is displayed.

[0079] In the initial phase point within a block synchronization detection period time length, the maximum value is detected in the matched filter 2 _2. In synchronous detection period, a new multi-level block division spread code from the memory 1 ₁ to 1 _J is supplied to the matched filter 2 ₁ to 2 _J. The new multi-valued block division spreading code is generated by adding a vector obtained by advancing the original block division spreading code by one block to a vector. Therefore, in the synchronization detection period, the multi-level block division spreading code is generated as follows. F ₁ = ｛G _1,2 , G _1,3 ,..., G _2,1 Ｆ F ₂ = ｛G _2,2 , G _2,3 ,..., G _3,1 Ｆ F ₃ = ｛ G _3,2 , G _3,3 ,..., G _4,1 ｝ F ₄ = {G _4,2 , G _{4,3 ,.} If provided, the multi-level block division spreading code is generated as follows. F ₁ = ｛G _1,3 , G _1,4 ,..., G _2,2 Ｆ F ₂ = ｛G _2,3 , G _2,4 ,..., G _3,2 Ｆ F ₃ = ｛ G _3,3 , G _3,4 ,..., G _4,2 Ｆ F ₄ = {G _4,3 , G _4,4 ,..., G _{5,2 よ う} As described above, one block at a time. by the generated multi-valued block division spread code by vector addition by advancing the block division spread code, a synchronous detection period, for example, the maximum value in the second matched filter 2 ₂ and is output, synchronization detection period, even, because so that the maximum value is output at the same second matched filter 2 _2, the same matched filter 2 _2, will be a maximum value which is synchronously added over several synchronization detection period is obtained , The detection accuracy is improved. The above-described synchronous addition can be applied to the first and second stages in the second and third embodiments. In the second stage of the first embodiment, the maximum likelihood detection of a normal binary spreading code is performed. Therefore, the maximum likelihood detection is performed over a plurality of synchronization detection periods without shifting the binary block division spreading code. Likelihood detection may be performed.

FIG. 15 is a diagram showing the synchronization acquisition characteristics of the first embodiment of the present invention evaluated by computer simulation. The horizontal axis is SNR (signal to noise ratio) [d
B], and the vertical axis indicates the synchronization point detection error rate [%]. The PN code has a code length N of 32768, the spreading is performed by BPSK,
The number of matched filters J is fixed at 8, and the synchronous point detection error rate with respect to the SNR (signal-to-noise ratio) under Gaussian noise is acquired for each of the matched filter tap lengths K of 64, 128, 256 and 512. . The number of retries performed when the timing phases do not match in the first stage and the second stage is limited to a maximum of 100 times. According to this diagram, when the tap length K of the matched filter is small, the influence of the mutual interference generated due to the multi-valued spreading code causes S
Synchronous acquisition is almost impossible even in a place where NR is good. However, it can be seen that the characteristics improve as K increases, and that good detection characteristics can be obtained even at a low SNR. When K = 256 and SNR = 0 [dB], the synchronization point detection error rate is less than 1%. At this time, the average number of retries was 2.6, and the average time until the synchronization point was detected was 3,733 chips.

In the above description, the case where the spreading code length is a code length of an integer power of 2 has been described. However, if the block division spreading code can be generated, it is not necessary to satisfy this condition. The code length may be such that it cannot be divided when dividing the frame or dividing the frame into blocks.
For example, in the first embodiment, when N = 4095 and the number of frames J = 4, N is not an integer power of 2. At this time, assuming that the number of blocks M = 15 and the number of codes in the block K = 64, in the first stage, a multi-level block division code is generated without using codes for 15 chips,
Synchronization detection is performed without using these 15 chips. In the second stage, the 15 chips are added, for example, to the head of the first block. In the second stage, a block division spreading code corresponding to the frame number selected in the first stage is synchronously detected as a coefficient. At this time, when a frame including a block division spreading code to which 15 chips are added is selected, if the synchronization detection period is extended by this 15 frames and synchronization is detected, synchronization detection including the 15 chips is performed. can do.

In the above description, the number of taps of the matched filter is changed to the block length of the multi-value block division spread code (one block Number), but does not have to be. In addition to being an integral multiple of the block length, it may be longer or shorter than the number of blocks. In the second stage of the first embodiment in which the binary spreading code is used for the coefficient, the number of stages of the matched filter is the same as that of the matched filter in the above-described description, as in the case of the K chip length of the first stage. It is not necessary to adjust the number of stages to the correlation detection period. Hereinafter, the case where the number of stages (the number of taps) of the matched filter is shorter than the block length of the multi-value block division spreading code will be described as fourth and fifth embodiments.

FIG. 16 is a block diagram showing a fourth embodiment of the synchronization acquisition apparatus according to the present invention. In the figure, 51 is a row correlation detection unit, 52 is a column correlation detection unit,
Reference numeral 53 denotes a determiner, which performs a maximum value selection and an offset timing comparison with respect to a row correlation detection unit 51 and a column correlation detection unit 52 under a control unit 54 to detect a synchronization point. . In the row (row) correlation detector 51, 55 ₀ ~55 _Jr-1 rows matched filter coefficients for the memory, which is 56 ₀ ~56 _Jr-1 rows matched filter. In the column correlation detecting section 52, 57 _{0 to} 5
7 _Jc-1 memory for the string matched filter coefficients, 58 ₀ ~
58 _Jc-1 is a column matched filter. Line matched filter 56 ₀ ~56 _Jr-1 number of stages (number of taps) equal to the column matched filter 58 ₀ ~58 _Jc-1 number of stages (number of taps), and K.

In this embodiment, based on the above-described third embodiment, the above-described block is further divided into sub-blocks. The length (the number of chips) of the sub-block is made to correspond to the number of stages (the number of taps) of the matched filter. According to this embodiment, the number of stages of the matched filter is reduced, and the circuit scale can be reduced. However, the observation period of the correlation detection is a period of one block length as in the third embodiment.

FIG. 17 is used in the fourth embodiment of FIG.
Schematically shows how to generate matched filter coefficients to be used
It is a 1st explanatory view. Row matched filter 56₀Coefficient
F₀, Column matched filter 58₀H which is the coefficient of₀
, A specific generation method is described. FIG.
Are all maps used in the first embodiment shown in FIG.
The second theory that schematically shows a method of generating a pseudo filter coefficient
FIG. All row matched filters 56₀~ 56
_Jr-1, Column matched filter 58₀~ 58 _Jc-1The coefficient of
And how the vectors are added.

First, referring to FIG.
Explains how to generate multi-level spreading codes used as
You. Let the spreading code of code length N be C = (c₀, c₁, ..., c_N-1)age
And this is converted to the row matched filter 56₀~ 56_Jr-1Pieces
The number J_rEqually divided into frames 0 to J_r-1
Is generated. Each frame is converted to a column matched filter 57.₀~
57_Jc-1J is the number of _cEqually divided into blocks,
Block J_c-1Is generated. Each block is further divided into B
Split into sub-blocks with length K equal to the length of the filter
I do. Because one sub-block is part of a block
It is called a partial spreading code. Sub in the frame
If the number of blocks is M, M = J_c× B.

The sub-block is represented by G _{jr, m} (where the subscript j _r is j
_{If the r-} th frame and the subscript m mean the m-th sub-block), the vector can be expressed as in the following equation. G _{jr, m} = (c _{jrMK + mK} , c _{jrMK + mK + 1} ,..., C _{jrMK + mK + K−1} ) The codes to be generated are roughly classified into two types: a row side and a column side. Each is J _r pieces and J _c pieces. The row multi-valued partial spreading code has a position in each block corresponding to each frame. For example, the last sub-block is a partial spreading code, and the partial spreading code is vector-added for each block. It is. That is, assuming that the j _r- th row multi-valued partial spreading code is represented by a vector and represented by F _jr , F _jr = G _{jr, B-1} + G _{jr, 2B-1} + G _{jr, 3B-1} +. + G
_{jr, (Jc-1) B} -1 where _{j r = 0, 1, 2} , ..., a J _r-1. The row multilevel partial spreading code is used as a row matched filter coefficient.

Next, the column multilevel partial spreading code is obtained by vector-adding, for each frame, the last sub-block described above whose position in each block corresponds to each frame. . That is, _assuming that the j _c- th column multi-level partial spreading code is expressed in vector as H _jc , H _jc = G _{0, jcB-1} + G _{1, jcB-1} + G _{2, jcB-1} +. + G
_{Jr-1, jcB-1} except _{j c = 0, 1, 2} , ..., a J _c-1. The column multilevel partial spreading code is used as a column matched filter coefficient.

FIG. 18 schematically shows a manner in which a row multi-level partial spreading code and a column multi-level partial spreading code are generated by vector addition. Spreading code frame 0
To _Jr-1 are arranged in the vertical row direction. Viewed in this way, the row multi-valued partial spreading codes F ₀ , F ₁ ,..., F _Jr-1 look like addition of row side sub-blocks in a matrix. The column multilevel partial spreading codes H ₀ , H ₁ ,..., H _Jc-1 appear to be additions of sub-blocks on the column side in a matrix.

Returning to FIG. 16, the synchronization acquisition operation will be described. The row correlation detection unit 51 determines, for each chip timing, the observation time for one block (B sub-block).
The correlation between the spread spectrum received signal and the above-described row multi-level partial spreading code is detected. At the same time, the column correlation detection unit 52 also detects the correlation between the received spread spectrum signal and the above-described column multi-level partial spreading code for each chip timing in the same observation time of one block.

More specifically, the row correlation detecting section 51
From the memory 55 ₀ ~55 _Jr-1 of the inner row multilevel portion spreading codes described above is as row matched filter coefficients are supplied to the corresponding row matched filter 56 ₀ ~56 _Jr-1. The row matched filters 56 _{0 to} 56 _Jr-1 add in parallel the correlation output of the spread spectrum received signal and the above-mentioned multi-level partial spreading code for each block and chip timing for one block. 53. Also, from the memory 57 ₀ ~57 _Jc-1 in the column correlation detector 52 supplies a column multilevel portion spreading code described above column matched filter coefficients, the corresponding column matched filter 58 ₀ ~58 _Jc-1 Have been. Column matched filter 58 ₀ ~58 _Jc-1
Outputs, in parallel, the correlation output between the spread spectrum received signal and the above-described row multi-level partial spreading code for one block time and chip timing, and outputs the result to the decision unit 53. Determiner 53, for each chip timing, as well as observing all of the output lines matched filter 56 ₀ ~ 56 _Jr-1, and past a maximum value during the observation period of one block, matched filter outputs the maximum value The offset timing (in this example, the phase within one block) when this maximum value is output is stored. At each chip timing, it is determined whether there is a correlation output exceeding the past maximum value. If there is no value exceeding the past maximum value, the process waits for the next chip timing. If the maximum value is exceeded, the storage of the row matched filter information and offset timing information that output the maximum value is updated, and the row matched filter information that newly outputs the maximum value and the offset timing information when the maximum value is output are updated. Remember. As a result, at the end of the observation period of one block, the stored row matched filter and offset timing information are:
This corresponds to the row matched filter that outputs the maximum value during the observation period of one block, and the offset timing when this maximum value is output.

The same processing is performed on the column side. That is, the determination unit 53, for each chip timing, as well as observing all of the output of the column matched filter 58 ₀ to 58 _Jc-1, and past a maximum value during the observation period of one block, and outputs this maximum value The information of the column matched filter and the information of the offset timing (phase in one block) when this maximum value is output are stored. At each chip timing, it is determined whether there is a correlation output exceeding the past maximum value. If there is no value exceeding the past maximum value, the process waits for the next chip timing. When the maximum value is exceeded, the storage of the column matched filter that output the maximum value and the offset timing are updated, and the column matched filter that newly outputs the maximum value and the offset timing when the maximum value is output are stored. At the end of the observation period of one block, the stored column matched filter and offset timing correspond to the column matched filter that output the maximum value during the observation period of one block and the offset timing when the maximum value is output. I do.

As a result, at the end of the observation period of one block, the decision unit 53 selects one row matched filter and one column matched filter that output the maximum value. Here, both offset timings are compared.
If the row-matched filter and the column-matched filter have the same offset timing from the capture mode start time (initial phase), the position of one row-matched filter and one column-matched filter that output this maximum value is synchronized. Points can be specified.

FIG. 19 is a first operation explanatory diagram showing, by a specific example, the principle by which a synchronization point can be specified. In this specific example,
The number of frames J _r = 2, the number of blocks J _c = 2, and the number of sub-blocks in a block M = 4. In the drawing, the upper row shows the code sequence of the received spread spectrum signals arranged such that the time progresses to the right. For the sake of simplicity, it is assumed that the transmission information data is +1 and the code of the spread code appears as it is in the code sequence of the received spread spectrum signal. Lower 4
The sub-blocks are, in order from the top, a row matched filter 56
₀ , row matched filter 56 ₁ , column matched filter 58
₀ , a column matched filter 58 ₁ is schematically shown.

[0095] F _0, as already described, is a row multilevel portion spreading code which is a coefficient line matched filter 56 _0. Below that, G _0,3 , G _0,7 , which are the partial spreading codes from which this row code was generated, are displayed. Similarly,
F ₁ is a line multilevel portion spreading code which is a coefficient line matched filter 56 _1. Below this, G _1,3 and G _1,7 which are partial spreading codes from which this row code was generated are displayed. H ₀ is a sequence multilevel portion spreading code as the coefficient of the column matched filter 58 _0. Below that is the partial spreading code from which this column multi-level partial spreading code was generated,
G _0,3 and G _1,3 are displayed. H ₁ is a column multi-level partial spreading code which is a coefficient of the column matched filter 58 ₁ . Below that, the partial spread codes G _0,7 and G _{1,7 from} which the column multi-level partial spread code is generated are displayed.

This figure shows that as the observation time progresses,
While the row matched filters 56 ₀ , 56 ₁ and the column matched filters 58 ₀ , 58 ₁ move rightward, they take in the code sequence of the immediately above received spread spectrum signal and perform a correlation detection operation. Is shown. During the lapse of one block (K × B chip) time, multi-value portion spreading code F ₀ is the coefficient of the line matched filter 56 _0, 56 _1,
And F _1, there is a timing at which the block boundaries of the received spread spectrum signal matches. In the illustrated example, a matching offset timing has elapsed phi ₁ chip period from acquisition mode starting point (initial phase).

At this time, the received spread spectrum signal spread by the partial spreading codes G _0,3 is received and input to the row matched filters 56 ₀ , 56 ₁ in parallel. Therefore, at this timing, if there is one that uses the partial spreading code G _0,3 as a matched filter coefficient, the correlation value becomes maximum. In this case, none of the partial spreading codes G _0,3 is used as a matched filter coefficient. Instead, there is a multi-level partial spreading code F ₀ generated by adding the partial spreading codes G _0,3 to the vector. Correlation line matched filter 56 ₀ to the multi-level portion spreading code F ₀ and the matched filter coefficients, during one block of the observation time, any row matched filter 56 _0, 56 ₁ of the correlation values take This is the maximum value. Therefore, in the illustrated example, the row matched filter 5
6 _0, and the offset timing phi ₁ is specified.

Similarly, on the column matched filter side, the multi-valued partial spreading codes H ₀ , H ₁ , which are the coefficients of the column matched filters 58 ₀ , 58 ₁ , are passed during one block (K × B chip) time. There is a timing at which the block boundaries of the received spread spectrum signal coincide. In the illustrated example, a matching offset timing has elapsed phi ₂ chip period from acquisition mode starting point (initial phase). At this time, the received spread spectrum signal spread by the partial spreading codes G _0,3 is received and input to the row matched filters 58 ₀ , 58 ₁ in parallel. Therefore, at this timing, there is a multi-valued partial spreading code H ₀ generated by adding the partial spreading codes G _0,3 by vector. Thus, the correlation value of the column matched filter 58 ₀ to the multi-level portion spreading code H ₀ and the matched filter coefficients, 1 between the block of the observation time, one of the columns matched filter 58 _0, 58 ₁ takes correlation This is the maximum value. Thus, in the illustrated example, the column matched filter 58 _0, and the offset timing phi ₂ are identified.

In the above description, it has been described that the offset timings φ ₁ and φ ₂ have different values. However, the line matched filter 56 ₀ ~56 _Jr-1, column matched filter 58 ₀ ~58 _Jc-1 both because the combined initial phase, the offset timing phi ₁ when matching the block boundaries of the received spread spectrum signal φ ₂ should also match. If they do not match, the received spread spectrum signal is affected by fading distortion or noise. When the offset timing phi ₁ and phi ₂ are identical, with the multi-level portion spreading code F ₀ is the coefficient of the line matched filter 56 ₀ specified, multi-valued coefficients of a column matched filter 58 ₀ identified The partial spreading code G _{0,3 from} which both partial spreading codes H ₀ are generated is specified.

As a result, the received spread spectrum signal is
At the timing of the offset timing φ ₁ (= φ ₂ ) from the initial phase of the specified partial spreading code G _0,3 , it is detected that the partial spreading code G _0,3 is synchronized with the spreading code on the receiving side.

FIG. 20 is a second operation explanatory diagram showing, by a specific example, the principle by which a synchronization point can be specified. As in FIG.
This is a specific example in which the number of frames J _r = 2, the number of blocks J _c = 2, and the number of sub-blocks in a block M = 4. 1 output value is selected as the maximum value in a block time, with respect to the output line matched filter 56 _0, 56 _1, line matched filter 5
6 ₀ is the output of the offset timing phi _1, with respect to the output of the column matched filter 58 _0, 58 _1, which is the output of the offset timing phi ₂ columns matched filter 58 _0.

As described above, the synchronization point with the received spread spectrum signal is detected by the combination of the row matched filter and the column matched filter that give the maximum value on the row side and the column side during one observation time and the offset timing thereof. Is done. The synchronization point is located at the offset timing of the partial spreading code from which the multivalued partial spreading code, which is a coefficient of each matched filter, is generated.

When the offset timings φ ₁ and φ ₂ from the start of the capture mode (initial phase) coincide with each other, the mode shifts to the confirmation mode described in the prior art.
Move to operation mode. However, when the offset timings φ ₁ and φ _{2 of} the row matched filter and the column matched filter do not match, an observation time of one block time is provided again, and the synchronization acquisition operation is restarted from the beginning. The number of redoes is determined in advance as a predetermined allowable number.

According to the configuration described above, the number of matched filters can be reduced and the observation time can be shortened by using multi-valued spreading codes. However, the correlation output includes intersymbol interference due to multi-level coding. At this point, the accuracy of the detected synchronization point is confirmed by judging the coincidence of the offset timing having the maximum value by two independent correlation detection processes on the row side and the column side. The method of detecting timing coincidence by two systems of processing is less susceptible to fading fluctuations, reception level fluctuations and the like than the case where power level threshold comparison as described in the related art is also used. Therefore, S
It can be applied in a wide range of N ratio. If the timings match as a result of the offset timing comparison, there is a low probability of erroneous synchronization acquisition, so that it is possible to reliably shift to the next confirmation mode. If the offset timings do not match, the overall time required for synchronization can be reduced by repeating the synchronization acquisition mode again without shifting to the next confirmation mode. Note that, since errors in synchronization acquisition are reduced, it is possible to immediately shift to the operation mode without shifting to the confirmation mode.

Next, a description will be given of a modification of the fourth embodiment of the above-described synchronization acquisition apparatus according to the present invention, in which synchronous addition is used together. When the synchronous addition is performed, the SN ratio is improved with respect to the received power, the peak of the maximum value becomes steep, and the resistance to noise can be improved. The matched filter is
A correlation value is output using a plurality of block periods as observation periods. When the matched filter coefficient exceeds one block time, the filter coefficient is shifted so that correlation can be detected at the same phase.

During the observation period, the row-side and column-side maximum values are selected for the value obtained by cumulatively adding the correlation outputs, that is, the value obtained by synchronous addition, for each chip timing during the block time. The offset timing having the maximum value on the row side and the column side, and the row matched filter and the column matched filter having the maximum value are specified. When the offset timings on the row side and the column side match, it is determined that there is a synchronization point in the offset timing of the partial spreading code, which is the basis for generating the coefficients of the specified row matched filter and column matched filter. Therefore, a memory for storing a value obtained by cumulatively adding the correlation output is provided for each matched filter output for each chip timing during the block time. In addition, the matched filter is updated in accordance with the time progress of the received spread spectrum signal so that the matched filter can continue to be detected with the same phase relationship even when one block is exceeded. There is a need.

FIG. 21 is an explanatory diagram schematically showing a method of generating a matched filter coefficient used in the fourth embodiment of the present invention. The synchronous addition when all rows matched filter 56 ₀ ~56 _Jr-1, column matched filter 58 _0-58
This shows how vector addition is performed for the coefficient of _Jc-1 . The row multi-level partial spreading code and the column multi-level partial spreading code in this case will be described. A subscript q indicating the sequence number of the synchronous addition is added, and the number of synchronous additions is Q. First, assuming that the row multi-valued partial spreading code is Fj _r , q, the following expression is obtained.

F _{jr, q} = G _{jr, qB-1} + G _{jr, (q + 1) B-1} + G
_{jr, (q + 2) B-1} + ... + G _{jr, (qJc-1) B-1 where} j _r = 0, 1, 2, ..., J _r -1 q = 1, .. ., Q FIG. 21A is an explanatory diagram showing a case where the sequence number q = 1 for synchronous addition. As in the third embodiment, as shown in FIG.
Column multilevel moiety spreading codes are generated, respectively, the matched filter 56 ₀ ~ 56 _Jr-1, column matched filters 58 ₀ ~
It becomes a coefficient of 58 _Jc-1 . Here, the sequence number q of the synchronous addition
Each time is incremented by 1, the added sub-blocks corresponding to the later time sequentially protrude into the frame at the earlier time. Last row multilevel partial spreading code G
_{As an example for jr, (qJc-1) B-1} , when q = 2, G
_{jr, (Jc + 1) B-1} = _{Gjr + 1, B-1} . Here, M = _Jc × B.

FIG. 21 (b) shows the sequence number q =
This is the case of 2. All the codes of the sub-blocks advance in the previous time direction by B sub-blocks. The code in the first sub-block circulates to become the code in the last sub-block. Therefore, the codes of the sub-blocks to be vector-added are all shifted by B sub-blocks in the previous time direction and circulated. FIG. 21 (c)
Is a case where the sequence number q of synchronous addition is 3. The codes of each sub-block further advance in the previous time direction by the amount of all B sub-blocks. Therefore, for the row multi-valued partial spreading code, the matched filter coefficients for the number of times of synchronous addition may be calculated in advance and stored in the row matched filter coefficient memory.

On the other hand, with regard to the column multi-valued partial spreading code,
The column multilevel partial spreading code used for the q-th synchronous addition is H
_{Assuming that jc, q} , the following relationship holds. H _{jc, q + 1} = H _{jc + 1, q} , H _{Jc, q + 1} = H _{0, q It} is clear from FIGS. 21 (a) to 21 (c) that the column multilevel partial spreading code is Synchronous addition can be realized by reusing one set of matched filter coefficients. Also,
Instead of changing the setting of the matched filter coefficient, the register for inputting the correlation output of the maximum likelihood detector on the column side is
Every time the block time ends, the input destination is switched, and even if the correlation output is input from a matched filter having a desired matched filter coefficient and then synchronous addition is performed,
Substantially the same. For example, when q = 1, the register that stores the correlation output of the matched filter 56 ₀ (FIG. 16) using H _0,1 as a coefficient in units of chips becomes:
The H _{1, 1} inputs the correlation output of the matched filter 56 _1, the coefficient (16), when q = 3, or by entering the correlation output of the matched filter 56 _2, coefficient H _2,1.

Next, a specific configuration will be described. In FIG.
All row matched filters 56 shown₀~ 56_Jr-1, Column
Matched filter 58₀~ 58_Jc-1Method that holds the coefficient of
Moly 55₀~ 55_Jr-1, 57₀~ 57_{Jc- 1}Apart from each
Holds synchronous addition data for one block of the filtered filter
(J _r+ J_c) Data memories are prepared. Controller 5
4. First, the row matched filter 56₀~ 56_Jr-1To F
_{jr, 0}(j_r= 0, ..., J_r-1) and H_{jc, 0}(j_c= 0, ..., J_cPerson in charge of -1)
Set the number. Data memory for each chip timing
Holds the output of each matched filter in
After holding for minutes, the matched filter coefficient
Moly 55₀~ 55_Jr-1, 57₀~ 57_Jc-1From the coefficient
F_{jr, 1}(j_r= 0, ..., J_r-1) and H_{jc, 1}(j_c= 0, ..., J_c-1)
Set for each matched filter.

Then, at each chip timing, the output of each matched filter and the previous value of the corresponding matched filter held in the data memory are added, and
The process of storing the data again in the data memory is performed for one block. After repeating the above-mentioned synchronous addition up to Q times, the row side from the data held in the data memory,
Select the maximum value for each column side. Identify the offset timing and matched filter that output the maximum value. Subsequent steps are the same as in the first embodiment,
The offset timings on the row and column sides that output the maximum value are compared. If they match, the mode shifts to the confirmation mode. If they do not match, the synchronization acquisition mode is restarted from the beginning.

FIG. 22 is a diagram showing a computer simulation to evaluate the synchronization acquisition characteristic when the synchronous addition is used in the fourth embodiment of the present invention. The PN code has a code length N of 32768, and the spread spectrum is BPSK.
The number of row matched filters J _r and the number of column matched filters J _c were each set to four, and the tap length K of each of the row matched filter and the column matched filter was set to 64. The number of synchronous additions Q is four.

FIG. 22 (a) shows an image under Gaussian noise.
(B) shows a synchronization point detection error rate (P
robabilility of false acquisition). A model in which the average signal power of each fading path exponentially decreases from the leading path was used. For comparison, the dotted line shows the synchronization acquisition characteristics of the conventional method (γ ₀ = 16). However, the number of times the capture mode is redone is 10
Limited to times. In either environment, the method of the present invention shows superior characteristics to the conventional method.

In the above description, the case where the matched filter is operated at the chip timing of the spread code has been described. On the other hand, a (integer) of chip timing
There is an oversampling operation for operating the matched filter at one-half time intervals. In each of the embodiments of the present invention, an oversampling operation can be performed. In this case, the number of stages of the matched filter is set to a times, and tap outputs are taken out at one-chip intervals to perform correlation detection. Since the correlation output is output at a time interval of 1 / (integer) of the chip timing, the maximum value is also detected at this interval.

For detection of the maximum value, the offset phase is output at a time interval equal to 1 / a (integer) of the chip timing. Therefore, there are two determination methods for comparing the offset timing. The first method is to check for coincidence at a time interval of 1 / a (integer) of the chip timing. The second method is that the offset timing shift is within a predetermined range, for example,
This is a method in which if they are within a predetermined range of less than one chip, it is determined that they match. For example, when a = 4 times, ± 0.25
If the difference is equal to or less than the chip, it is considered that they match.

In the above-described fourth embodiment, the synchronization detection on the row side and the column side is performed simultaneously in parallel to speed up the processing. , In order. It is not always necessary to simultaneously detect the synchronization on the row side and the column side simultaneously. In the above description, the number of frames number J _r and the block number J _c, if two or more are not particularly limited. However, the total number of the matched filter when the frame number J _r = number of blocks J _c is a row-side, with the effect of mutual interference distortion due to multi-value can be the same for correlation detection of the column side, which requires Can be minimized. Also, for one of the matrices, without adding by multi-valued conversion, 2
It is also possible to detect the correlation with the partial spreading code of the value.

Further, one block has one sub-block length (K
The case where it is divisible by the chip) has been described. But,
It is not always necessary that one block be divisible by one sub-block length (K chips). Although the calculation becomes easier when the number is divisible, even if the number is not divisible, one block time is the observation time. Therefore, a synchronization point is detected at the last sub-block in one block. In addition, in the above description, the matched filter coefficient is generated by vector addition of the code of the last sub-block in one block. The use of the last sub-block simplifies the operation, but the matched filter coefficient may be generated by vector-adding the K-block sub-block at an arbitrary position in one block. Also, the partial spreading code does not necessarily have to be fixed length

In the third and fourth embodiments described above, two groups of matched filters on the row side and the column side are used, and the decision unit for selecting the maximum value on the row side and the column side is used. And That is, in the third embodiment, a multi-valued divided spreading code obtained by dividing a spread code into a plurality of divided spread codes, arranging the divided spread codes two-dimensionally in rows and columns, and performing vector addition in the row and column directions. Are used as the matched filter coefficients on the row side and the column side, respectively, to find the synchronization point at which the correlation output in the row and the column becomes maximum two-dimensionally. Also, in the fourth embodiment, a part of the divided spreading code is used as a partial spreading code instead of the divided spreading code, and a synchronization point at which the correlation output in the two-dimensional row and column is maximized is similarly obtained. ing. At this time, the timing of each of the row and the column at which the maximum value is obtained is compared, and a synchronization point is obtained when they are equal, thereby improving the accuracy of determining the synchronization point.

Therefore, by further generalizing, it is possible to detect the maximum likelihood in three or more dimensions. In this case, the codes constituting the above-described sub-blocks may be further divided into second sub-blocks, and the second sub-blocks may be arranged in the height direction. That is, the spreading codes are three-dimensionally arranged. Then, the multi-value division spreading code obtained by vector addition in the height direction is set as a matched filter coefficient for the height direction. Maximum likelihood detection is also performed for this matched filter for the height direction, and it is compared whether or not the synchronization detection phase when the maximum value is obtained in each dimension is matched. It can be seen that there is a synchronization point in the offset timing of the divided spreading code commonly included in the plurality of divided spreading codes that are the source of the multi-valued divided spreading code when taking the maximum value. It is preferable that the number of divisions in each dimension is equal, as in the case of the above-described two-dimension.

In the above-described two-dimensional and three-dimensional maximum likelihood detection, two or more multi-level partial spreading codes are obtained by using independent combinations of divided spreading codes extracted at equal intervals from the spreading codes. Three are generated. By doing so, it is possible to detect the maximum likelihood systematically and orderly. More generally, a group of a plurality of multilevel partial spreading codes is obtained by combining and adding a plurality of different partial spreading codes to a plurality of partial spreading codes respectively extracted from a plurality of portions of the spreading code. Generate Further, by generating a plurality of different combinations, a plurality of groups of the multi-valued partial spreading codes are generated. Perform correlation detection between the received signal that has been spread spectrum by the spreading code and each multi-level partial spreading code of each group,
A multi-level partial spreading code that gives the maximum correlation value for each group and an offset timing are detected, and when the offset timings match for a plurality of groups (exact match or majority decision match), it is determined that there is a synchronization point. I do.

In the fourth embodiment described above, based on the third embodiment, the block is divided into sub-blocks, and the number of chips in this sub-block is used as the number of taps of the matched filter. Similarly, in the first and second embodiments, a block is divided into sub-blocks,
For example, the last sub-block in a block may be a partial spreading code, and the number of chips may correspond to the number of taps of a matched filter, and one block time may be used as an observation time.
Instead of being divided into sub-blocks, a part of a block may simply be used as a partial spreading code, and the number of chips of the partial spreading code may correspond to the number of taps of the matched filter.

In the above description, correlation detection was performed using a matched filter. Examples of the matched filter include an analog type or digital type transversal filter, a matched filter using a surface acoustic wave element (SAW), and a filter having a function equivalent to a matched filter using a SAW convolver. Alternatively, the correlation can be detected using a sliding correlator. However, the synchronization acquisition time becomes significantly longer, and the control of selecting a spreading code to be given to the sliding correlator from the memory becomes complicated.

[0124]

According to the present invention, as is apparent from the above description, the spreading code is divided into a plurality of block-divided spreading codes, and a plurality of correlation detectors are arranged in parallel to operate simultaneously, thereby fading in a fading environment. A strong maximum likelihood detection method can be employed. In addition, the use of multi-level block division codes has the effect that an optimum synchronization point can be acquired quickly and satisfactorily. In particular, it is suitable when a long-period sequence is used as a spreading code. Since it is possible to determine whether the synchronization point is correct by comparing the timings at which the two matched filters output the maximum value, it is possible to transit to the confirmation mode or the operation mode with a higher probability than before. If it is determined in the confirmation mode that the synchronization point is incorrect, it is necessary to start over from the acquisition mode again. In the prior art, the capture time of the present invention is shorter than in the prior art as a result of the increased probability of redoing from the confirmation mode to the capture mode.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronization acquisition device according to first to third embodiments of the present invention.

FIG. 2 is a conceptual diagram of a method for generating a multilevel block division spreading code used in the first stage of each embodiment of the present invention.

FIG. 3 shows a second embodiment of the present invention.
It is a conceptual diagram of the generation method of the spreading code used in a stage.

FIG. 4 is a flowchart for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a specific example of the operation of the first stage in the first to third embodiments of the present invention.

FIG. 6 shows a second embodiment of the present invention.
It is explanatory drawing which shows the operation | movement of a stage by a specific example.

FIG. 7 shows a second embodiment of the present invention.
It is a conceptual diagram of the generation method of the binary spreading code used at a stage.

FIG. 8 is a flowchart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 9 shows a second embodiment of the present invention.
It is explanatory drawing which shows the operation | movement of a stage by a specific example.

FIG. 10 is a block diagram showing a multi-level block division spreading code F _j used in the first stage and a multi-level block division spreading code H _m used in the second stage according to the third embodiment of the present invention. It is a conceptual diagram of a generation method.

FIG. 11 is an explanatory diagram of a principle of predicting a synchronization point in the third embodiment of the present invention.

FIG. 12 is a flowchart for explaining an operation of the third exemplary embodiment of the present invention.

FIG. 13 is an explanatory diagram showing a specific example of the operation of the second stage in the third embodiment of the present invention.

FIG. 14 is a cross-sectional view of the first to third embodiments of the present invention.
FIG. 9 is an explanatory diagram of a specific example in a case where synchronous addition is performed in the first stage.

FIG. 15 is a diagram in which synchronization acquisition characteristics are evaluated by computer simulation in the first embodiment of the present invention.

FIG. 16 is a block diagram of a fourth embodiment of the synchronization acquisition device of the present invention.

FIG. 17 is a first explanatory view schematically showing a method of generating a matched filter coefficient used in the fourth embodiment of FIG.

FIG. 18 is a second diagram schematically showing a method of generating a matched filter coefficient used in the fourth embodiment shown in FIG.
FIG.

FIG. 19 is a first operation explanatory diagram showing, by a specific example, the principle by which a synchronization point can be specified;

FIG. 20 is a second operation explanatory diagram showing, by a specific example, the principle by which a synchronization point can be specified;

FIG. 21 is an explanatory diagram schematically showing a method of generating a matched filter coefficient used in the second embodiment of the present invention.

FIG. 22 is a diagram illustrating, by computer simulation, synchronization acquisition characteristics when synchronous addition is used in conjunction with the fourth embodiment of the present invention.

FIG. 23 is a block diagram of a conventional sliding correlator.

24 is a conceptual diagram showing an output of the sliding correlator shown in FIG.

FIG. 25 is a block diagram of a conventional matched filter.

FIG. 26 is a block diagram showing a configuration for performing maximum likelihood detection using a conventional sliding correlator.

FIG. 27 is a block diagram of a conventional spread code synchronization acquisition device using a parallel matched filter.

FIG. 28 is an explanatory diagram of a method of creating a code used in the synchronization acquisition device shown in FIG. 27;

FIG. 29 is a diagram for explaining the operation of a specific example of the synchronization acquisition device shown in FIG. 27;

[Explanation of symbols]

 1₁~ 1_J Memory, 2₁~ 2_J Matched filter, 3
Maximum likelihood detector, 4 control section, 51 row correlation detection section, 52
Column correlation detector, 53 determiner, 54 controller, 55₀~
55_Jr-1, 57₀~ 57_Jc-1 Memory, 56₀~ 56_Jr-1
 Row matched filter, 58₀~ 58_Jc-1 Column matched
Filter, 101, 101₁~ 101_NMultiplier, 102
Integrator, 103 PN generator, 104 control unit, 121
₁~ 121_N-1 Multi-level delay element, 132₁~ 132_N-1 2
Value delay element, 122₁~ 122 _N 1st to Nth amplification
, 123 adder, 131 maximum likelihood detector, 131 maximum likelihood
Detector, 210₁~ 210_J-1 Matched filter, 21
1 Maximum value selection and threshold comparison unit

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-88526 (JP, A) JP-A-4-77022 (JP, A) JP-A-7-131381 (JP, A) JP-A-11-111 112384 (JP, A) JP-A-2000-41022 (JP, A) JP-A-2000-115148 (JP, A) JP-A-2000-252869 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04B 1/707 H04L 7/00 H04L 27/38

Claims (19)

(57) [Claims] 1. A method for acquiring a spread code for establishing synchronization between a received signal spread spectrum by a spread code and the spread code on a receiving side, wherein the spread code is divided into J frames and further divided into M blocks. J pieces of multi-level block division spreading codes are generated by adding a plurality of block division spreading codes generated by division to codes corresponding to positions in a block for each frame. By performing correlation detection between the J multi-level block division spreading codes and the received signal in parallel, the multi-level block division spreading code that provides the maximum correlation value, the first intra-block phase, And specifying the block division spreading code of M blocks in the frame in which the specified multi-level block division spreading code is generated, as it is or following After advancing the phase to the block division spreading code, it is further subdivided into J frames, and the correlation detection between the block division spreading code and the reception signal in the plurality of subdivided block division spreading codes is performed in parallel. By performing the above, the block division spreading code that gives the maximum correlation value and the second intra-block phase are specified, and when the first and second intra-block phases match, the specified block division spread code Detecting that there is a synchronization point in the phase in the second block. 2. A method for capturing a spread code for establishing synchronization between a received signal spread spectrum by a spread code and the spread code on the receiving side, wherein the spread code is divided into J frames and further divided into M blocks. By adding a plurality of block-divided spreading codes generated by division to codes corresponding to positions in a block for each frame, J first multilevel block-divided spreading codes are generated. And adding the codes corresponding to the positions in the block to each of the plurality of block division spread codes corresponding to the block positions in each frame, for each of the block positions, Number of second multi-level block division spreading codes are generated, and correlation detection between the J first multi-level block division spreading codes and the received signal is performed in parallel. The first multi-level block division spreading code that gives the maximum correlation value and the phase in the first block are specified, and the M second multi-level block division spreading codes and the reception signal are identified. Correlation detection is performed in parallel, the second multi-level block-divided spreading code that gives the maximum correlation value and the second intra-block phase are specified, and the first and second intra-block phases match. When the specified first multi-valued block division spreading code is generated in the frame, the specified second multi-valued block division spreading code is generated at the block position. Detecting the presence of a synchronization point in the second intra-block phase of the block division spreading code. 3. A partial spreading code forming a part of each of the block divided spreading codes is used instead of a plurality of block divided spreading codes generated by dividing the spread code into J frames and further dividing the divided code into M blocks. The synchronization acquisition method according to claim 1, wherein: 4. J correlation detectors for inputting a received signal spectrum-spread by a spreading code, a maximum likelihood detector for comparing the correlation values of the J correlation detectors over a predetermined time period, and the J correlations A count storage unit that stores a coefficient of a detector, and a synchronization acquisition device for a spread code including a control unit, wherein the coefficient storage unit divides the spread code into J frames, and further divides the spread code into M blocks. Stores J first multi-level block-divided spreading codes generated by adding the generated plurality of block-divided spreading codes to codes corresponding to positions in a block for each frame. In the first stage, the control unit sets the J first multi-level block division spreading codes stored in the coefficient storage unit to the J correlation detectors, respectively. And The correlation detectors respectively perform parallel detection of the correlation between the received signal and the first multi-level block-divided spreading code, and the maximum likelihood detector outputs the maximum correlation value. A detector and a timing, wherein the control unit, based on the output of the maximum likelihood detector, calculates the first multi-level block-divided spreading code that gives a maximum correlation value and a first intra-block phase. By identifying, it is predicted that there is a synchronization point in the phase in the first block in one of the block division spreading codes in the frame that generated the identified first multi-level quantization block division spreading code. A synchronization acquisition apparatus for a spreading code, characterized by the following. 5. The coefficient storage unit according to claim 1, wherein the block division spreading code of M blocks in the frame in which the specified first multi-valued block division spreading code in the first stage is generated, or , After advancing the phase to the subsequent block division spreading code, re-dividing into J frames, and selecting and storing one block division spreading code from each of the re-divided frames, In the second step, the control unit sets each of the J selected block division spreading codes stored in the coefficient storage unit to the J correlation detectors, and the correlation detector Perform parallel detection of the correlation between the received signal and the selected block-spreading code, respectively, and the maximum likelihood detector outputs the maximum correlation value and the correlation detector. And the controller specifies the selected block division spreading code that gives the maximum correlation value and the second intra-block phase based on the output of the maximum likelihood detector, When the phases in the first and second blocks match,
The apparatus according to claim 4, wherein it is detected that a synchronization point exists in the specified phase in the second block of the selected block division spreading code. 6. The coefficient storage unit according to claim 1, wherein the block division spreading code of M blocks in the frame in which the specified first multi-valued block division spreading code is generated in the first stage is directly or After advancing the phase to the subsequent block division spreading code, it is subdivided into J frames, and the subdivided block division spreading code has a position in the block corresponding to each subdivision frame. And storing J number of second multilevel block-divided spreading codes generated by adding the codes. In a second stage, the control unit stores the code stored in the coefficient storage unit. J second multi-valued block division spreading codes are respectively set in the J correlation detectors, and the correlation detectors respectively receive the received signal and the second multi-valued block. The correlation detection with the spreading code is performed in parallel, the maximum likelihood detector outputs the correlation detector that outputs the maximum correlation value and the timing, and the control unit outputs the maximum likelihood detector. A synchronization point is present in a phase in a second block in one of the block division spreading codes in the re-divided frame that has generated the second multi-valued block division spreading code that gives the maximum correlation value based on And when the phases in the first and second blocks match,
The apparatus according to claim 4, wherein the apparatus shifts to the next stage of synchronization point detection. 7. A plurality of correlation detectors for inputting a received signal spectrum-spread by a spreading code, a maximum likelihood detector for comparing correlation values of the plurality of correlation detectors over a predetermined time, and a plurality of correlation detectors. A coefficient storage unit for storing coefficients, and a spread code synchronization acquisition device having a control unit, wherein the coefficient storage unit is generated by dividing the spread code into J frames and further dividing into J blocks. J number of first multilevel block division spreading codes generated by adding a plurality of block division spreading codes for codes corresponding to positions in a block for each frame,
The block division spreading code corresponding to the block position in each frame is generated for each of the block positions by adding codes corresponding to the positions in the block to each other. And the controller stores the J first multi-level block division spreading codes stored in the coefficient storage unit as J The correlation detector of the above, each of the correlation detectors, respectively, performs a parallel detection of the correlation between the received signal and the first multi-level block division spreading code, The maximum likelihood detector, The correlation detector that outputs the maximum correlation value and the timing are output, and the control unit outputs the M second multi-level block division spreading codes stored in the coefficient storage unit as M Set to the above correlation detectors And each of the correlation detectors respectively receives the received signal and the M
The second maximum likelihood detector outputs the correlation detector that outputs the maximum correlation value and the timing, and performs the correlation detection with the second second multi-level block division spreading codes in parallel. Specifies, based on an output of the maximum likelihood detector, the first multi-level block-divided spreading code that gives a maximum correlation value and a first intra-block phase, and gives the maximum correlation value. Identifying the second multi-level block division spreading code and a second intra-block phase, and when the first and second intra-block phases match, the identified first multi-level encoding The phase in the second block of the block division spread code at the block position where the specified second multi-valued block division spread code was generated in the frame in which the block division spread code was generated. That there is a sync point Out to the synchronization acquisition apparatus of the spreading code, characterized in that. 8. The coefficient storage unit also stores a coefficient when the correlation detector performs correlation detection over one period of correlation detection, and the control unit stores the coefficient over one period of the correlation detection. And performing correlation detection by resetting the coefficient stored in the coefficient storage unit to the correlation detector, and causing the maximum likelihood detector to synchronously add the correlation value. The spread code synchronization acquisition device according to any one of claims 4 to 7. 9. A partial spreading code forming a part of each of the block divided spreading codes is used instead of a plurality of block divided spreading codes generated by dividing the spread code into J frames and further dividing the divided code into M blocks. The synchronization acquisition device according to any one of claims 4 to 8, wherein: 10. A group of a plurality of multi-level partial spreading codes by combining and adding a plurality of different partial spreading codes to a plurality of partial spreading codes respectively extracted from a plurality of portions of the spreading code. Is generated, and further, by performing the generation for a plurality of different combinations, a plurality of groups of the multi-valued partial spreading codes are generated, and the received signals spectrum-spread by the spreading codes, and the reception signals of the respective groups, The correlation detection with each multi-level partial spreading code is performed, and the multi-level partial spreading code that gives the maximum correlation value for each group is detected. And determining that there is a synchronization point when performing the method. 11. The method according to claim 10, wherein the plurality of portions of the spread code are portions separated from each other. 12. The spread code is divided into J _r frames, each frame is divided into J _c blocks, each block is divided into a plurality of sub-blocks, and a predetermined number in each of the divided blocks is determined. By using the sub-blocks as partial spreading codes, for each frame, adding the partial spreading codes in each block in the frame, J
_{By generating r} row multi-valued partial spreading codes and adding, for each block, the partial spreading codes of the block in each frame, J _c column multi-valued partial spreading codes are obtained. A spreading code has been generated, and a correlation detection between the received signal subjected to spectrum spreading by the spreading code and the row multi-level partial spreading code is performed to give a maximum correlation value. A first offset timing is specified, and a correlation between the received signal and the column multi-level partial spreading code is detected to give a maximum correlation value. A synchronization timing when the first and second offset timings match, determining that there is a synchronization point. 13. When detecting a correlation with the row multi-level partial spreading code and the column multi-level partial spreading code over a plurality of block times, one block time is used for the correlation detection at each block time. The row multi-valued partial spreading code and the column multi-valued partial spreading code are generated for each of the codes obtained by advancing the spreading code one block at a time, and the row giving the maximum correlation value is generated. A multi-level partial spreading code, the first offset timing, and the column multi-level partial spreading code and the second offset timing that give the maximum correlation value are determined by synchronous addition in units of one block. The method according to claim 12, wherein: 14. The method of detecting a correlation between the row multi-level partial spreading code and the column multi-level partial spreading code and determining the first and second offset timings is an integer of chip timing of the spreading code. 14. The method according to claim 12, wherein it is determined that the first and second offset timings match when the first and second offset timings are within a predetermined range. 15. A plurality of groups of correlation detectors for inputting a received signal spectrum-spread by a spreading code, a coefficient storage unit for storing coefficients of the plurality of groups of correlation detectors, and a plurality of groups of correlation detectors. An apparatus for acquiring a spread code having a determiner having an output as an input, wherein the coefficient storage unit includes a plurality of partial spread codes extracted from a plurality of parts of the spread code, and a plurality of different spread codes. A group of a plurality of multi-valued partial spreading codes generated by combining and adding the partial spreading codes, and storing a plurality of groups of the multi-valued partial spreading codes generated for a plurality of different combinations, The correlation detectors of the respective groups are provided with the multi-valued partial spreading codes of the respective groups, and a received signal spectrum-spread by the spreading codes and the multi-level conversion of the respective groups. Performs correlation detection between the divided spreading code, the determining unit, the per group, gives the maximum correlation value,
A synchronization acquisition apparatus for a spread code, comprising: detecting the multi-level partial spreading code and an offset timing; and determining that there is a synchronization point when the offset timings match for a plurality of groups. 16. The apparatus according to claim 15, wherein the plurality of portions of the spread code are portions separated from each other. 17. A method for storing J _r row correlation detectors and J _c column correlation detectors for inputting a received signal spectrum-spread by a spreading code, and storing coefficients of the row correlation detector and the column correlation detector. A coefficient storage unit for performing the processing, and a spread code synchronization acquisition device having a determination unit that receives outputs of the row correlation detector and the column correlation detector as inputs. The coefficient storage unit stores the spread code as J _r. Divided into J _c blocks, and each frame is divided into J _c blocks,
Each block is divided into a plurality of sub-blocks, and the predetermined sub-block in each of the divided blocks is used as a partial spreading code, and for each frame, the partial spreading codes in each block in the frame are , And J _c generated by adding J _r row multi-valued partial spreading codes generated by adding the partial spreading codes and the partial spreading codes of the block in each frame in each frame. Column multi-valued partial spreading codes, and the row correlation detector is configured to set the row multi-valued partial spreading codes, respectively, between the received signal and the row multi-valued partial spreading codes. Performing correlation detection, the column correlation detector, respectively, the column multi-level partial spreading code is set, performs the correlation detection between the received signal and the column multi-level partial spreading code, And said By comparing the correlation value of the line correlation detector and outputs the maximum correlation value, the row correlation detector and the first
And the correlation value of each of the column correlation detectors is compared, and the column correlation detector and the column-side offset timing that output the maximum correlation value are specified. And determining that there is a synchronization point when the offset timings of the synchronization acquisition timing coincide with each other. 18. The coefficient storage unit according to claim 1, wherein the row correlation detector and the column correlation detector perform one block time for the correlation detection at each block time when performing the correlation detection at a plurality of block times. Storing the row multi-valued partial spreading code and the column multi-valued partial spreading code generated for each time the spreading code is advanced by one block each time the time exceeds the one block time Each time, the row correlation detector sets the row multi-valued partial spreading code for correlation detection at each block time, and the column correlation detector sets the column multiplication for correlation detection at each block time. A quantified partial spreading code is set, wherein the determinator synchronously adds outputs of the row correlation detector and the column correlation detector in units of one block, 18. The spread code synchronization acquisition device according to claim 17, 19. The row correlation detector and the column correlation detector perform correlation detection at an integer multiple of the chip timing of the spreading code, and the determinator determines the correlation at an integer multiple of the chip timing of the spreading code. 19. The synchronization acquisition device according to claim 17, wherein the outputs are compared, and it is determined that the first and second offset timings match when they are within a predetermined range. .