JP3343765B2 - Terminal control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a terminal control device used for an electronic exchange according to a stored program control system.

[0002]

2. Description of the Related Art Conventionally, in such a terminal control device, in particular, a multifunctional telephone controller accommodating a multifunctional telephone as a terminal device has much more information to manage than a general telephone interface circuit, and a multifunctional telephone. Functions such as multi-function keys, LCD display, and lamp multi-color display.

[0003]

However, in the above-mentioned conventional terminal control device, in addition to controlling the terminal device,
The state information indicating the state of the terminal device and the control information for controlling the terminal device have to be transmitted and received with the central control device of the electronic exchange by a predetermined communication procedure. Therefore, there is a problem that not only the program of the MPU which is the control means of the terminal control device becomes complicated, but also that it is difficult to make a trade-off between the central control device and the control means.

Further, since there are many interface circuits between the central control device and the terminal control device and between the terminal control device and the terminal device, a considerable space for mounting components is required, and the size and weight are limited. In addition, there is a problem that the mounting efficiency is reduced due to the space for mounting the components, and the manufacturing cost is increased.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a terminal control device which can reduce a burden of a trade-off between a central control device and the control means. Things.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a data exchange with a central control unit in an electronic exchange.
Terminal control device that transmits data and controls the terminal device to be accommodated.
A readout command from the central control device.
Transmitting the status information indicating the status of the terminal device, a storage unit for storing control information for controlling the terminal device in response to the write command from the central controller, wherein by detecting the state of the terminal device Control means for storing state information in the storage means, reading the control information from the storage means and controlling the terminal device, the central control device and the control means
Arbitrates a period during which the stage can independently access the storage means
And an access arbitration unit .

[0007]

Therefore, according to the present invention, the central control device of the electronic exchange and the terminal control means share the storage means for reading and writing, without performing communication processing between them, and being aware of the mutual restrictions. Since the status information and the control information are transmitted by independent operations without any change, it is possible to reduce the burden of a trade-off between the central control device and the control means.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a system configuration when the present invention is applied to a multifunctional telephone controller for controlling a multifunctional telephone. In FIG. 1, reference numeral 1 denotes a communication path switch (hereinafter, “TSW”) of an electronic exchange that forms a communication path between a central office line or a dedicated line (not shown) and a terminal device to be accommodated.
That. ). A central control unit (hereinafter, referred to as 2) controls the TSW (1) to control the connection between the office line and the terminal device while monitoring the state of the office line and the state of the input / output system of the terminal device. , "CPE"). Reference numeral 10 denotes a multi-function telephone controller (hereinafter referred to as "MTLI") as a terminal control device which is connected to an electronic exchange and performs data control such as LED, LCD, tone, and telephone call on the multi-function telephone.
N ". ), And 11 is a multifunctional telephone (hereinafter, referred to as “MFT”) as a terminal device. Hereinafter, the MTL will be described with reference to FIGS. 2 to 5 and Tables 1 to 21.
The data control of IN (10) will be described.

FIG. 2 is a more detailed block diagram of FIG. As shown in FIG. 2, the inside of the MTLIN (10) includes the MPU (3), the MTLGA (4), and the SPLSIA.
(5), SPLSIB (6), RAM (7), ROM
(8) and a communication circuit (9). further,
MPU (3), MTLGA (4), SPLSIA
(5), SPLSIB (6), RAM (7) and ROM
(8) is connected by a common bus. This bus is
It comprises an 8-bit data bus, a 16-bit address bus, and a control bus. In addition, MTLGA
(4), SPLSIA (5) and SPLSIB (6)
Are implemented as LSIs, respectively.

The MPU (3) is a microprocessor for controlling the MTLIN (10). MTLGA (4)
Performs generation of clocks and various signals, bus control, timing formation of data transmission and reception, and the like. That is, MTLGA
(4) Bus access right adjustment means for adjusting the bus usage right of the CPE (2) and the MPU (3). SPLSIA
(5) performs conversion of highway speed, control of serial data transmission / reception, development of an address bus from the MPU (3), generation of signals, and the like. Furthermore, SPLSIA (5)
Are connected to the TSW (1) via a communication path, and connected to the CPE (2) via a serial data line. Therefore, SP
The LSIA (5) has a shift register for converting serial data into parallel data, as described later.

The SPLSIB (6) performs a communication path determination control and a state monitoring of the MPU (3). RAM (7) is C
This is a common memory of the PE (2) and the MPU (3). In the present embodiment, the period during which the RAM (7) can be accessed is CPE.
(2) and MTLGA divided by MPU (3)
Access is possible by the bus control of (4). Hereinafter, a period during which the CPE (2) can access the RAM (7), that is, a period during which the right to use the bus is obtained is referred to as a CPE mode period, and a period during which the MPU (3) can access the RAM (7) is an MPU mode period. Called. ROM (8) is M
This is the program memory of the PU (3). Call circuit (9)
Controls the communication between the MTLIN (10) and the MFT (11). Further, the communication circuit (9) performs A / A conversion for converting between a digital communication signal and an analog communication signal.
Codec with D and D / A converters (CODE
C) (9a), hybrid circuit (HIC) (9b) for performing 2-wire / 4-wire conversion, and MFT (1) of MFT (11)
12) to the interface circuit (9c).

On the other hand, the inside of the MFT (11)
A communication circuit (111) for controlling a call with a speaker, and an MPU (112) for controlling data such as an LED, LCD, and function keys of an operation display unit and other operation controls are provided. The communication circuit (111) is connected to the MTLIN (1
0) transmitting and receiving call information to and from the call circuit (9);
The PU (112) transmits and receives control data to and from the communication circuit (9).

FIG. 3 shows an SP system interface at the time of MTLIN / DLC order. With this interface, a package and a circuit are specified.
The circuit performs LED and LCD control, tone control, line control, and the like. FIG. 4 shows MFT (1
It represents an external view of the operation display section of 1), and includes a handset (113), an LCD display section (114), an LED display section (115), and an operation key section (116).

FIG. 5 shows the SP in the DSS / MISC order.
And the DSS / MI
LED / LCD control at SC order. The contents of the LED / LCD control include time control, LED control of a local line transmission / reception key, LED control of a station response key, and the like.

Next, the operation of this embodiment will be described with reference to FIGS.

In FIG. 2, SPLSIA (5) receives request data from CPE (2), expands it, and
By the bus control of the TLGA (4), data is written to the RAM (7) during the CPE mode. MPU (3)
The data written in the RAM (7) is read during the U mode period, and the MFT (11) is monitored for the data. If there is any change in the MFT (11), the ACK in the SPLSIA (5) is changed to High level as change data, and the change data is written to the RAM (7) during the MPU mode period by the bus control of the MTLGA (4). .

The CPE (2) performs SPLSIA periodically.
The ACK in (5) is monitored and the change data (ACK
= High), the content is read from the RAM (7) during the CPE mode period. Then, CPE (2)
Will send the order for the read content to SPLSIA
Send to (5). SPLSIA (5) is a CPE
Those that fall under the category of the order of from (2) to select, expand it, RAM by the bus control of MTLGA (4)
Write in (7). The MPU (3) reads this order from the RAM (7), sends it to the MFT (11), and
It controls D / LCD / tone / call.

That is, CPE (2) and MPU (3)
Can access the RAM (7) independently without being restricted by each other.
The program of (3) can be simplified and CPE
The trade-off between (2) and MPU (3) can be facilitated. Further, even when the MPU (3) is changed to another type, the MPU (3) is not restricted by the CPE (2), so that a flexible system configuration can be realized.

In FIGS. 6 to 9, SPLSIA
The operation (5) will be described.

The internal circuit of the SPLSIA (5) can be divided into a communication path control section, a serial data transmission / reception section, an address expansion section, and a buffer section. SPLSIA (5)
Are these LSIs.

FIG. 6 is a circuit diagram of the communication path control unit.

The communication path control section mainly performs conversion of a highway speed and generation of a clock, and a highway speed conversion circuit (201) outputs PCM data (4M highway) of 64 time slots on the input side from the TSW (1). HWR) is converted into parallel data, and PCM data (CODI) of 32 time slots 2M highway is converted by a shift register at the next stage.
N) and sends it to the codec (9a). At the same time, the "AA" pattern of the channel test data is detected in the channel test unit (202) for the parallel data. On the other hand, the 2M highway PCM data (CODOUT) from the codec (9a) is developed into parallel data by the 2M clock, converted into 4M highway PCM data (HWS) by the next-stage shift register, and converted to the TSW
Output to (1).

At the time of the channel test, the "AA" pattern is used as the shift register data instead of the PCM data.
The “AA” pattern detection result is latched for 16 time slots, and 8-bit data (D0 to D0) is controlled by software.
D7) to the data bus.

The clock generation circuit (203) is a C4MP
The counter is driven by the signal and the FRAM signal to generate various timing clock signals. The counter initial value is
Set by PSEL0 and PSEL1 (see FIG. 7).

FIG. 7 is a circuit diagram of the serial data transmitting / receiving section.

The serial data transmitting / receiving section includes a data receiving circuit (204) and a data transmitting circuit (205). The data receiving circuit (204) converts the serial data into parallel data by using a shift register,
The data is latched by a counter activated by the GON, RDSTB, and RD signals, and the data is captured. Package numbers P0-P3 are matched with PSEL0-3 and PCO
Generate M.

Normally, PCOM is set to LOW level, but when P0 to P3 are not used, it is set to High level according to external conditions. The device codes E0 to E3 are output to the outside after latching. When using a device code other than "0001", monitor E0 to E3 externally and set ECOM to H
Set to the high level. Circuit number CCT0-CCT3
And the order types ODR0 to ODR2 are sent to the next circuit, respectively, and the received data D0 to D7 are subjected to parity check and sent to the data bus.

When the received data is a WRITE operation to an LSI internal register, the data transmitting circuit (205) transmits a start bit and a parity check result as transmitted data after receiving the received data. When the WRITE operation is an external register, the HALT signal is output, and after receiving the BA signal, the transmission data is output. When the received data is an internal register READ operation, a start bit / ACK bit / data 8 bits / parity bit is transmitted after receiving the W / R signal. At the time of external register READ, transmission data is output after receiving the BA signal.

FIGS. 8 and 9 are circuit diagrams of the buffer section and the address bus expanding section.

The address bus development unit (206)
Decode the address buses A0 to A15 from (3),
Generate various signals. When accessing an external address, the circuit number (CCT) and the order number (OD
R) as an address.

The buffer section includes an internal buffer and an MPU bus buffer. The internal buffers are buffers for ACK0 to ACK15 and an external data bus, and gate control is performed by the received serial data C0 to C3. ACK0-15
Is written by the MPU bus and reset by serial data.

The MPU bus buffer is a buffer for ACK0 to ACK15, a communication path test result and serial data, and gate control is performed by A0 to A15 of the MPU (3).

Next, referring to FIG. 10 to FIG.
The SIB (6) will be described.

The internal circuit of SPLSIB (6) is divided into a communication path control section, an SD / SCN development section, and an MPU state monitoring section. SPLSIB (6) is an LSI of these.

In FIG. 10 and FIG.
The developing unit will be described.

The SD / SCN developing unit is the MPU (3)
The circuit outputs SD signals (SD00 to SD33) corresponding to the circuit according to 0, A1, A4, and D0 to D3. Also, it receives the SCN signals (SCN00 to SCN33) and sends them to the data bus of the MPU (3).

Referring to FIG. 11, the MPU status monitor will be described.

The MPU status monitor counts a clock signal having a period of 4 ms, and within 64 counts, that is, 256
When the IRQRST signal is not received within the ms period, MP
The MPU (3) is reset by outputting the DOWN signal.

Referring to FIG. 12, the communication path control unit will be described.

The communication path control unit includes package codes 0, 1
(PKGNC 0, 1) and circuit numbers 0, 1 (CCB
0, 1) and codec strobe signals (STB0 to STB3) corresponding to each circuit by C4MP and FRAM.
Occurs.

In FIG. 13, the part surrounded by the dotted line is L
This is an internal circuit of the MTLGA (4) that has been converted to SI.

The MTLGA (4) includes a clock generator (12), a data transmission / reception timing generator (13), a database / address bus controller (14), a BA generator (15), and a device type code decoder (16). ).

FIG. 14 is a circuit diagram of the clock generator (12) in FIG. 13, and its operation will be described.

The clock generator (12) is mainly composed of a data file flip-flop,
The 4.096 MHz clock signal from (1) is latched by data flip-flops (121) and (122),
An E clock (ECLK) and a Q clock (QCLK) to be supplied to the MPU (3) are generated. Each circuit is 4,096
Data control is performed using an E clock and a Q clock together with a clock signal of MHz.

FIG. 15 is a circuit diagram of the data transmission / reception timing forming section (13) in FIG. 13, and its operation will be described.

Data transmission / reception timing forming section (13)
Is mainly composed of a shift register, and SPLSIA is based on the Q clock from the clock generator (12).
CS5 of (5) is converted into CS1 by the shift register (131).
Are converted from serial data to parallel data by a shift register (132), and a clock signal and a reset signal are generated, and clock signals of data flip-flops (171) and (172) for controlling data with the MFT (11) And a reset signal input. The data flip-flops (171) and (172) use the MPU
Data transmitted from (3) to MFT (11) and MF
The received data from T (11) to SPLSIB (6) is controlled.

FIG. 16 shows the address bus in FIG.
FIG. 4 is a circuit diagram of a data bus control unit (14), and its operation will be described.

Address bus / data bus control unit (14)
Is mainly composed of a buffer data flip-flop decoder, and includes a buffer (141) and a buffer (1).
42), buffer (145) and buffer (146)
Controls and determines the addresses of the RAM (7) and the ROM (8) when accessing the MPU (3) and the SPLSIA (5). The address from the MPU (3) to the SPLSIA (5) controls the gate of the buffer (141) and the buffer (142) by the BA signal from the SPLSIA (5), and controls the address bus. Also, M
The addresses of the RAM (7) and the ROM (8) when the PU (3) and the SPLSIA (5) are accessed are controlled by the MAD signal from the BA generator (15) to control the gates of the buffers (145) and (146). are doing. The buffer (143) and the buffer (1413) and the buffer (1414) are composed of the MPU (3) and the SPLSIA.
(5) The direction of the data bus of the RAM (7) and the ROM (8) is controlled. The decoder (144)
From (3), the address buses A13, A14, and A15 are decoded, and the opening and closing timing of the data bus is determined as gate control of the buffer (143). or,
The data buses of the RAM (7) and the ROM (8) are controlled by the MAD signal and the AD signal of the BA generator (15). The MAD signal controls the gate of the buffer (1414), and the AD signal is the buffer (1413). Of the RAM (7) and the data bus of the ROM (8).

MTLIN (10) has an MTLIN order, an MTLIN / DLC order, and a DSS / MISC.
Although there are three orders, these address bus and data bus controls are controlled by data flip-flops (14
7), (149) and (1410) and the buffer (14)
8), (1411) and (1412).

The MTLIN order controls the address bus during a call, is performed by the buffers (1411) and (1412), and performs gate control by the MTG signal from the device type code decoder (16). .

The MTLIN / DLC order refers to the MFT
(11) LCD lighting / flashing / extinguishing address control and L
It controls the CD display address and their data, and is performed by a buffer (148) and a data flip-flop (147).
6) The BRLT signal and M
It receives and controls an RB signal for identifying whether or not LCD control of the FT (11) is performed, and a BRAD signal as gate control.

The DSS / MISC order is an MFT (1
1) Data control of LED lighting / flashing / extinguishing speed, etc., and "-year-month-day" and "-hour-minute-second" on the LCD
The display data is controlled by data flip-flops (149) and (1410). At this time, the DLT signal and the LLT signal are received from the device type code decoding unit (16), and the DLT signal is used as the clock of the data flip-flop (149) as LL.
The T signal is a clock of the data flip-flop (1410). Also, it receives and controls a LAD signal as a gate control.

FIG. 18 is a circuit diagram of the BA generator (15), and its operation will be described.

The BA generation section (15) is mainly composed of a data flip-flop. The HALT signal is received from the SPLSIA (5) by the data flip-flop (151), and latched by the E clock to convert the BA signal. Is occurring. The BA signal controls the gates of the address bus buffers (141) and (142) of the MPU (3) and the data bus buffer (1413), and controls the SPLSI
The address / data bus is released at A (5). Also BA
The signal is controlled as CE of the RAM (7) together with the MAD signal.

The BA generation unit (15) generates an R / W signal from the SPLSIA (5) in addition to the generation of a BA signal.
The 4.096M clock signal from W (1) is
From (3), the R / W signal A15 is supplied to the clock generator (1
2) receive the E clock from each of them, generate OE, WE, and CE of the RAM (7), control reading and writing of the address bus and the data bus, and set the data bus buffer (14).
13), MA as gate control of (1414)
A D signal and an AD signal are generated.

FIG. 19 shows an apparatus type code decoder (1).
It is a circuit diagram of 6), and demonstrates the operation | movement.

The device type code decoding section (16) is mainly composed of a decoder, and develops a necessary order from the exchange body by using a device type code consisting of 4 bits for each package, and outputs the data to the SPLSIA (5). ECOM
・ Sending and operating as PCOM.

The decoder (161) expands the DSS / MISC order, receives the device type codes E0, E1, E2, E3 from the SPLSIA (5), and
Is decoded as gate control. as a result,
The LLT signal is transmitted as the first order, the DLT signal is transmitted as the second order, and the LAD signal is transmitted as the third order. The first order identifies DSS or MISC. The second order designates the address of the LED number of the MFT (11) and designates the LCD display data. The third order is MFT (11)
Are actually turned on or displayed on the LCD.

The decoder (162) is provided with the MTLIN / DL
SPLSIA (5), which expands the C order
Decode the order addresses A4, A5, A6 from
It sends out BRLT and BRAD signals. The BRLT signal and the BRAD signal are sent to the data flip-flop (147) and the buffer (148) of FIG.
Control MTLIN / DLC order.

The RB signal is an LED of the MFT (11).
This is a signal for identifying control or LCD control. MT
SPLSIA as a signal to control the LIN order
(5) The SA000 signal, the BA signal, and the ECOM signal are received, and the MTG signal is generated. The MTG signal is shown in FIG.
Buffer (1411) and buffer (141) described in FIG.
The MTLIN order is controlled as the gate control of 2).

As described above, the terminal control apparatus MTLI
In N (10), CPE (2) which is the central controller
Of data transmission / reception between the RAM and the storage means (7)
Of the terminal device MTF (11) and MPU (MPU)
SPLSIB (6) as a second data relay unit for data transmission / reception with (3) is formed as one LSI, and
MTLGA (4) as a bus use adjusting means for adjusting bus use rights of PE (2) and MPU (3) is one L
By using SI, component mounting space can be reduced,
Mounting on a small-sized substrate is also possible, which has the effect of improving component mounting efficiency, reducing the size and weight of the product, and improving quality.

[0063]

According to the present invention, as is apparent from the above embodiment, the central control unit of the electronic exchange and the MPU (microprocessor) of the terminal control unit for controlling the terminal unit indicate the state of the terminal unit. Since data and control data for controlling the terminal device are commonly used as storage means for writing and reading, and data transmission is performed without taking a specific communication procedure, the MPU program can be simplified, and the A trade-off between the control device and the MPU can be facilitated. Further, even when the MPU is changed to another type, the MPU is not restricted by the central control device, so that a flexible system configuration can be realized.

Further, the first data relay unit for data transmission and reception between the central control unit and the storage unit is one LSI, and the second data relay unit for data transmission and reception between the terminal device and the control unit is one LSI. Furthermore, by using a single LSI as the bus use adjusting means for adjusting the bus use right of the central control device and the control means, the space for mounting components can be reduced, mounting on a small-sized board is also possible, and the efficiency of mounting components is improved. This has the effect of reducing the size and weight of the product and improving the quality.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration when the present invention is applied to a multi-function telephone controller for controlling a multi-function telephone.

FIG. 2 is a more detailed block diagram of FIG.

FIG. 3 is a diagram illustrating an SP interface at the time of MTLIN / DLC order.

FIG. 4 is an external view of an operation display unit of the multifunctional telephone.

FIG. 5 is a diagram illustrating an SP interface in a DSS / MISC order.

FIG. 6 is a circuit diagram of a communication path control unit.

FIG. 7 is a circuit diagram of a serial data transmission / reception unit.

FIG. 8 is a circuit diagram of a buffer unit.

FIG. 9 is a circuit diagram of an address bus development unit.

FIG. 10 is a circuit diagram showing an SD / SCN developing unit.

FIG. 11 is a circuit diagram showing an SD / SCN developing unit.

FIG. 12 is a circuit diagram of a communication path control unit.

FIG. 13 is a diagram illustrating a device type code decoding unit in the MTLGA.

FIG. 14 is a circuit diagram of a clock generator in FIG.

FIG. 15 is a circuit diagram of a data transmission / reception timing forming unit in FIG.

FIG. 16 is a circuit diagram of an address bus / data bus control unit in FIG. 13;

FIG. 17 is a circuit diagram of an address bus / data bus control unit in FIG. 13;

FIG. 18 is a circuit diagram of a BA generator.

FIG. 19 is a circuit diagram of a device type code decoding unit.

[Explanation of symbols]

1 Time switch (TSW) of electronic exchange 2 Central control unit (CPE) of electronic exchange 3 Microprocessor (M) controlling package
PU) 4 MTLGA composed of LSI 5 SPLSIA composed of LSI 6 SPLSIB composed of LSI 7 Common memory (RAM) with central controller 8 Program memory of microprocessor (RO)
M) 9 Circuit for controlling communication between multifunction telephone controller and multifunction telephone 10 Multifunction telephone controller 11 Multifunction telephone 12 Clock generation unit 13 Data transmission / reception timing formation unit 14 Address bus / data bus control unit 15 BA generation unit 16 Device type code decoding unit 17 Data flip-flop that controls data transmission / reception to / from a multifunction telephone

Claims (1)

(57) [Claims] 1. A terminal control device for performing data transmission with a central control device in an electronic exchange and controlling a terminal device to be accommodated therein, wherein the terminal control device controls the terminal device in response to a read command from the central control device. A storage unit for transmitting state information indicating a state, storing control information for controlling the terminal device in response to a write command from the central control device, and detecting the state of the terminal device to obtain the state information. Control means for storing the control information in the storage means and reading the control information from the storage means to control the terminal device; and access for arbitrating a period during which the central control device and the control means can independently access the storage means. A terminal control device comprising arbitration means.