JP3340551B2 - High definition still video camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition still video camera for generating an image signal in a high-definition mode such as a high-vision system.

[0002]

2. Description of the Related Art Conventionally, a still video device in a high-definition mode is provided with an image sensor having a photodiode of, for example, 2 million pixels corresponding to this mode. The reading operation of the pixel signal from the image sensor, the A / D conversion and the storing operation to the memory are performed according to a high-speed read clock unlike a still video device of a standard mode such as the NTSC system.

[0003]

As described above, in the conventional high-definition still video device, since the pixel signals are processed at a high speed, the power consumption in the circuits around the image pickup device is large and the high-speed driving is supported. There was a problem that an expensive circuit was required.

The present invention has been made to solve such a problem, and does not require high-speed driving of an image sensor and its peripheral circuits, that is, obtains a high-definition image signal by a low-power and inexpensive circuit. It is an object of the present invention to provide a still video device capable of performing such operations.

[0005]

A first high-definition still video camera according to the present invention comprises a plurality of image pickup devices and an object image which is optically divided and formed on a light receiving surface of each of the plurality of image pickup devices. An optical element, a plurality of low-speed memories each having a storage capacity for storing an image signal output from each of the image sensors, and a memory for storing almost all image signals output from the plurality of image sensors. A high-speed memory having a recording capacity, and a first memory for storing an image signal output from each of the image sensors in the low-speed memory at a first driving frequency.
And second storage means for reading out the image signals stored in the plurality of low-speed memories at the first drive frequency, synthesizing them into an image signal corresponding to one screen, and storing the image signals in the high-speed memory. Means for reading out the image signal stored in the high-speed memory at a second drive frequency higher than the first drive frequency to form a high-definition image signal.

A second high-definition still video camera according to the present invention comprises: a plurality of image sensors; an optical element for optically dividing a subject image and forming an image on a light receiving surface of each of the plurality of image sensors; A plurality of low-speed memories each having a storage capacity for storing an image signal output from each image sensor, and a first memory for storing the image signal output from each image sensor in the low-speed memory at a first drive frequency Storage means, means for reading out a plurality of image signals stored in the low-speed memory at the first drive frequency and for recording the plurality of image signals in a plurality of recording areas of a recording medium, and a plurality of image signals output from the plurality of image sensors. A high-speed memory having a recording capacity for storing all image signals, and reproducing the image signals recorded in the plurality of recording areas at the first drive frequency and corresponding to one screen. Second storage means for combining the image signal with the high-speed memory and storing the image signal in the high-speed memory; and reading out the image signal stored in the high-speed memory at a second driving frequency higher than the first driving frequency to obtain a high-definition image. Means for forming an image signal.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a block diagram showing a configuration of a high-definition still video camera according to a first embodiment of the present invention.

A subject image obtained through the photographing lens 11 is optically divided into four by an optical path dividing optical element 20 and formed on light receiving surfaces of first to fourth CCDs (solid state image pickup devices) 12 to 15. You. That is, ＣＣＤ of the screen of the subject image is formed on each of the CCDs 12 to 15. C
The CDs 12 to 15 have a configuration according to a standard mode such as the NTSC system, and the number of photodiodes provided on the light receiving surfaces of the CCDs 12 to 15 is, for example, about 400,000 to 500,000.
The operation of reading image signals from the CCDs 12 to 15 is controlled by the CCD drive circuit 16 and is performed at a _first drive frequency f1 corresponding to the standard mode. Optical path splitting optical element 20
The configuration and the subject image formed on the CCDs 12 to 15 will be described later in detail.

Each of the image signals read from the CCDs 12 to 15 is converted into an AGC signal by the camera process circuits 21 to 24.
(Auto gain control), gamma correction, etc. Then, each image signal is converted to an A / D converter 25-2.
The digital signal is converted into a digital signal at 8 and stored in the first to fourth low-speed memories 31 to 34. Each low-speed memory 31-34
Have storage capacities required to store image signals output from the CCDs 12 to 15, respectively. A / D
A / D conversion operation of converters 25 to 28 and low-speed memory 31 to 31
Storing operation to 34 is controlled by the first memory control circuit 35, it takes place in a first drive frequency f _1.

[0010] CCD drive circuit 16 and memory control circuit 35
The, a first synchronizing signal generator 36 is connected for outputting a clock signal of the drive frequency f _1, these circuits 1
6 and 35 drive the CCDs 12 to ₁₅ at a drive frequency f1 based on a command signal output from the system control circuit 37, or drive the A / D converters 25 to 28 and the low-speed memory 3
1 to 34 are controlled.

The image signals stored in the low-speed memories 31 to 34 are read out at the _first drive frequency f ₁ , and are read out of the subject image.
The image is synthesized with an image signal corresponding to the screen and stored in the high-speed memory 42. That is, the high-speed memory 42 is
15 has a storage capacity necessary to store almost all the image signals output from the memory 15. A switch 41 is provided between the low speed memories 31 to 34 and the high speed memory 42.
The switch 41 is controlled to be switched by the system control circuit 37, and one of the first / fourth low speed memories 31 to 34 is selectively connected to the high speed memory 42.

The image signal stored in the high-speed memory 42 is
Second drive frequency f higher than _first drive frequency f ₁
Read in ₂ . The second drive frequency f ₂ is a drive frequency used when reading an image signal from an image sensor in a high-definition mode such as a high-vision system, and the image signal read from the high-speed memory 42 is a high-definition image signal. The high-definition image signal is converted into an analog signal by the D / A converter 44, subjected to predetermined processing by a signal processing circuit (not shown), and output to a display device or the like.

[0013] operation of reading the image signals from the low-speed memory 31 through 34 is controlled by the first memory control circuit 35, it takes place in a first drive frequency f _1, as described above. The operation of storing and reading the image signal in and from the high-speed memory 42 and the D / A conversion operation of the D / A converter 44 are controlled by the second memory control circuit 43. As described above, the storage operation is performed at the first drive frequency f. place in _1, also reading operation is performed in the second drive frequency f _2.

The second memory control circuit 43 has a switch 45
, A first synchronization signal generator 36 and a second synchronization signal generator 4 for outputting a clock signal of a _second drive frequency f _2.
6 are connected. The switch 45 is controlled by the system control circuit 37 to switch one of the first and second synchronization signal generators 36 and 46 to the second memory control circuit 43.
Selective connection to That is, the second memory control circuit 43
Controls the high-speed memory 42 at the drive frequency f ₁ or f ₂ and controls the D / A converter 44 at the drive frequency f ₂ based on a command signal output from the system control circuit 37.

FIG. 2 shows a configuration example of the optical path splitting optical element 20 and C
The arrangement of CDs 12 to 15 is shown. In this example,
The optical path splitting optical element 20 includes three mirror members 21 to 23 having the same shape. Each mirror member 21
23 are right triangular prisms, the first mirror member 21 is disposed perpendicular to the horizontal plane, and the second and third mirror members 22 and 23 are disposed on both sides of the first mirror member 21 in parallel to the horizontal plane. ing. The first CCD 12 is located above the second mirror member 22, and the second CCD 13 is located above the third mirror member 2.
3 above, the third CCD 14 is below the second mirror member 22, the fourth CCD 15 is below the third mirror member 23,
The light receiving surfaces of the CCDs 12 to 15 are opposed to the reflection surfaces R of the mirror members 22 and 23, respectively.

Reference numeral F indicates one screen of an image obtained by the photographing lens 11 (FIG. 1). This screen has a rectangular shape and is divided into four by a horizontal line and a vertical line passing through the center. The image of the upper left split screen F1 is the first mirror member 2
1 and the reflecting surface R on the second mirror member 22
And is imaged on the first CCD 12. The image of the upper right divided screen F <b> 2 is reflected on the right reflection surface R of the first mirror member 21 and the reflection surface R on the third mirror member 23, and is formed on the second CCD 13. Similarly, the image of the lower right divided screen F3 is formed on the third CCD 14, and the image of the lower left divided screen F4 is formed on the fourth CCD 15.

FIG. 3 shows two examples of the relationship between one screen F of an image obtained by the photographing lens 11 and the light receiving surfaces of the CCDs 12 to 15. FIG. 3A shows an example of each CCD.
Has a configuration according to the NTSC system.
The CD has a photodiode of 754 pixels in the horizontal direction and 485 pixels in the vertical direction. Therefore four CCs
By synthesizing the image signals output from D, 1 is composed of 1508 pixels in the horizontal direction and 970 pixels in the vertical direction.
The screen is obtained. The example of FIG. 3B is a case where each CCD has a configuration for a wide screen, and each CCD has a photodiode of 948 pixels in the horizontal direction and 485 pixels in the vertical direction. Therefore, by synthesizing the image signals output from the four CCDs, the horizontal direction is 1896.
One screen consisting of 970 pixels in the vertical direction is obtained.

The operation of the embodiment will be described. Shooting lens 1
1, the divided screens F1 to F4 constituting the image obtained by
Are formed on the respective CCDs 12 to 15 and these C
The image signals read from the CDs 12 to 15 are temporarily stored in the first to fourth low-speed memories 31 to 34 as digital signals. These image signals are stored in the memories 31 to 34.
From the high-speed memory 42 via the switch 41.
And are synthesized as an image signal of one screen. The operation so far is performed by the _first driving frequency f1 used for processing the image signal in the standard mode such as the NTSC system, and a high-speed clock signal is used as in the conventional high definition mode still video apparatus. Absent. Therefore, an expensive circuit corresponding to high-speed driving is unnecessary, and CC
Power consumption in circuits around D12 to D15 can be reduced.

FIG. 4 is a block diagram showing the configuration of a high-definition still video apparatus according to a second embodiment of the present invention. In this figure, parts corresponding to the components of the first embodiment include:
The same reference numerals as in FIG. 1 are used. Hereinafter, only the configuration and operation different from those of the first embodiment will be described.

In the second embodiment, the first to fourth low speed memories 3
The image signals read from 1 to 34 are not directly stored in the high-speed memory 42 but are once recorded on the magnetic disk D. That is, in this embodiment, a motor 51 for rotating and driving the magnetic disk D, a magnetic head 52, and a servo tracking control circuit 53 for rotating the motor 51 at a constant speed and controlling the tracking of the magnetic head 52 are provided. I have. A D / A converter 54, an SV recording processing circuit 55, a recording / reproducing switch 56, an SV recording processing circuit 57, and an A / D converter 58 are provided between the switch 41 and the high-speed memory 42. .

At the time of recording on the magnetic disk D, the recording / reproducing switch 56 connects the magnetic head 52 to the SV recording processing circuit 55. Therefore, the image signals read from the low-speed memories 31 to 34 are converted into analog signals by the D / A converter 54,
The image is subjected to processing such as M modulation, and is recorded on the magnetic disk D via the magnetic head 52 on a total of eight tracks, two tracks per image. Recording mode of the magnetic disk D is still video recording system according to the NTSC system or the like, the recording operation to the magnetic disk D is carried out on the first drive frequency f _1. That is, the A / D converters 25 to 2
8, the low-speed memories 31 to 34 and the D / A converter 54
Controlled by the first memory control circuit 35 at the first drive frequency f ₁ , the SV recording processing circuit 55 operates based on the clock signal of the drive frequency f ₁ output from the first synchronization signal generator 36.

When reading an image signal recorded on the magnetic disk D, the recording / reproducing switch 56 switches the magnetic head 52 to the S position.
It is connected to the V reproduction processing circuit 57. Therefore, the read image signal is subjected to processing such as FM demodulation in an SV reproduction processing circuit 57, converted into a digital signal by an A / D converter 58, and stored in the high-speed memory 42. The read operation and the storage operation to the high speed memory 42 from the magnetic disk D is carried out on the first drive frequency f _1. That is, S
The V recording processing circuit 55 operates based on the clock signal of the driving frequency f ₁ output from the first synchronization signal generator 36, and the A / D converter 58 and the high-speed memory 42 are controlled by the second memory control circuit 35 It is controlled at a drive frequency f ₁ of _one .

The read operation of the image signal from the high-speed memory 42 and the D / A conversion operation of the D / A converter 44 are controlled by a second memory control circuit 43, and are used in a high definition mode such as a high vision system. It takes place in the drive frequency f _2. The second memory control circuit 43 is connected to the first and second synchronizing signal generators 36 and 46 via a switch 45, and is connected to the A / D converter 58 during the A / D conversion operation and to the high-speed memory 42. During the storing operation, it is connected to the first synchronizing signal generator 36 side, and during the reading operation from the high-speed memory 42 and the D / A converting operation by the D / A converter 44, it is connected to the second synchronizing signal generator 46 side. Connected.

As described above, in the second embodiment, the CCDs 12 to
The image signal obtained by 15 is processed at the first drive frequency f ₁ , recorded once on the magnetic disk D, read from the magnetic disk D, and stored in the high-speed memory 42. Therefore, up to the storing operation in the high-speed memory 42,
The high-speed clock signal used in the high definition mode is not used. Therefore, the same effect as in the first embodiment can be obtained.

FIG. 5 is a block diagram showing the configuration of a high-definition still video apparatus according to a third embodiment of the present invention. In FIG. 5, parts corresponding to the components of the first embodiment include:
The same reference numerals as in FIG. 1 are used. Hereinafter, only the configuration and operation different from those of the first embodiment will be described.

The optical path splitting optical element 20 is a half mirror 25
And the image obtained by the photographing lens 11 is 2
The image is divided and formed on the first and second CCDs 12 and 13. The image signals read from the CCDs 12 and 13 are:
A predetermined process is performed in the camera process circuits 21 and 22, the digital signal is converted into digital signals in the A / D converters 25 and 26, and the digital signals are stored in the low-speed memories 31 and 32. The image signals read from the low-speed memories 31 and 32 are stored in the high-speed memory 42 via the switch 41. The operation of reading the image signal from the high-speed memory 42 and the D / A converter 44
/ A conversion operation is performed in the second drive frequency f ₂ for use in the high definition mode such as high-definition system.

The operation up to the storage operation in the high-speed memory 42 is performed at the first drive frequency f ₁ , and no high-speed clock signal is used. Therefore, the first and second embodiments also employ the third embodiment.
The same effect as that of the embodiment can be obtained.

FIG. 6 shows one screen F of an image obtained by the photographing lens 11 and the CCDs 12 to 12 in the third embodiment.
15 shows an example of the relationship with the light receiving surface 15. Each CCD has a photodiode of 1000 pixels in the horizontal direction and 1018 pixels in the vertical direction. Therefore, by synthesizing the image signals output from the two CCDs, one screen having 2000 pixels in the horizontal direction and 1018 pixels in the vertical direction is obtained. One screen of the HDTV system has 1920 pixels in the horizontal direction and 1035 pixels in the vertical direction.
According to the third embodiment, it is possible to cover the effective pixels of the HDTV system in the horizontal direction.

The standard mode and the high-definition mode each have various systems, and are not limited to the NTSC system or the high-vision system.

[0030]

As described above, according to the present invention, there is no need to drive the image sensor and its peripheral circuits at high speed, that is, a high-definition image signal can be obtained with a low power consumption and inexpensive circuit. A fine still video device is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a high definition still video device according to a first embodiment of the present invention.

FIG. 2 is a perspective view illustrating a configuration example of an optical path splitting optical element and an arrangement of CCDs.

FIG. 3 shows one screen of an image obtained by a photographing lens and each C
FIG. 3 is a diagram illustrating a relationship with a light receiving surface of a CD.

FIG. 4 is a block diagram showing a configuration of a high definition still video device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a high definition still video device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between one screen of an image obtained by a photographing lens and a light receiving surface of each CCD in a third embodiment.

[Explanation of symbols]

 Reference Signs List 20 optical path splitting optical element 31-34 low speed memory 42 high speed memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/225 H04N 5/232

Claims (8)

(57) [Claims] A plurality of image sensors, an optical element for optically dividing a subject image to form an image on a light receiving surface of each of the plurality of image sensors, and an image signal output from each of the image sensors. A plurality of low-speed memories each having a storage capacity for storing the same, a high-speed memory having a storage capacity for storing substantially all image signals output from the plurality of image sensors, and image signals output from the respective image sensors First storage means for storing the image signals in the low-speed memory at a first drive frequency, and reading out the image signals stored in the plurality of low-speed memories at the first drive frequency and converting the image signals into image signals corresponding to one screen. A second storage unit for combining and storing the image signals in the high-speed memory; and an image signal stored in the high-speed memory,
Means for reading out at a second drive frequency higher than the first drive frequency to form a high-definition image signal. 2. A semiconductor device comprising: a first synchronizing signal generating means for generating a synchronizing signal of the first driving frequency; and a second synchronizing signal generating means for generating a synchronizing signal of the second driving frequency. The high-definition still video camera according to claim 1, wherein: 3. The second storage means and the high-definition image signal forming means are constituted by a memory control circuit, and one of the first and second synchronization signal generating means is selectively connected to the memory control circuit. 3. The high-definition still video camera according to claim 2, further comprising switch means. 4. The method according to claim 1, wherein the first driving frequency is a driving frequency corresponding to a standard television system, and the second driving frequency is a driving frequency corresponding to an HDTV system. High definition still video camera. 5. A plurality of image sensors, an optical element for optically dividing a subject image and forming an image on a light receiving surface of each of the plurality of image sensors, and an image signal output from each of the image sensors. A plurality of low-speed memories each having a storage capacity for storing the image signals output from each of the image sensors, a first storage unit for storing the image signals in the low-speed memory at a first drive frequency, and Means for reading a plurality of image signals at the first drive frequency and recording the plurality of image signals in a plurality of recording areas of a recording medium; and a recording capacity for storing substantially all image signals output from the plurality of image sensors. A high-speed memory for reproducing the image signals recorded in the plurality of recording areas at the first drive frequency, synthesizing the image signals corresponding to one screen, and storing the image signals in the high-speed memory. And a means for reading out the image signal stored in the high-speed memory at a second drive frequency higher than the first drive frequency to form a high-definition image signal. And high-definition still video camera. 6. A semiconductor device comprising: a first synchronizing signal generating means for generating a synchronizing signal of the first driving frequency; and a second synchronizing signal generating means for generating a synchronizing signal of the second driving frequency. The high-definition still video camera according to claim 5, wherein 7. The second storage means and the high-definition image signal forming means are constituted by a memory control circuit, and one of the first and second synchronization signal generating means is selectively connected to the memory control circuit. The high-definition still video camera according to claim 6, further comprising switch means. 8. The method according to claim 5, wherein the first driving frequency is a driving frequency corresponding to a standard television system, and the second driving frequency is a driving frequency corresponding to an HDTV system. High definition still video camera.