JP3327232B2 - Recording code converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording code converter, and more particularly, to an optical disk device, a magneto-optical disk device,
The present invention relates to a digital recording disk device such as a phase change disk device and a hard disk device, and a recording code conversion device applied to a digital recording VTR.

[0002]

2. Description of the Related Art Conventionally, a digital recording disk device such as an optical disk device, a magneto-optical disk device, a phase change disk device, and a hard disk device for digitally recording digital data or image / audio data and a digital recording VTR do not record data as it is. Then, recording was performed after recording and encoding. A typical example of such recording encoding is 1,7 encoding.

Next, a code conversion table of the 1,7 codes is shown in FIG.
Shown in In the figure, 2-bit bit data is converted into 3-bit channel bits, or 4-bit bit data is converted into 6-bit channel bits and then recorded according to the NRZI rule. Here, the NRZI rule is NoReturnToZeroInverse.
It is an abbreviation of a rule, and refers to a rule that recording is performed while performing inversion by "1" and non-inversion by "0".
Also, in this 1,7 encoding, when decoding pattern deviation occurs due to an error during recording / reproduction or the like, the decoding is restored.
The synchronization signal is inserted every hundreds to thousands of bits. This uses a channel bit pattern that does not appear in normal data so that it can be clearly distinguished from data.

As a recording code conversion device, Japanese Patent Application Laid-Open
What is disclosed in -275347 is known. According to the publication, 8-bit input data is
After conversion into bit codes, NRZI conversion is performed to obtain a recording signal. In such a case, “1” does not continue for 2 or more bits, “0” does not continue for 6 bits or more, and “0” is added at the end.
Are assigned to the first and second conversion tables in common among the 449 13-bit codes of 449 13-bit codes that are not consecutive for 5 bits or more, and 1 codes starting with “1”
Forty-five codes are allocated to the first conversion table, and 145 codes that do not start with “1” or “01” are allocated to the second conversion table. For 145 codes other than the common 111 codes, among the conversion results in the first and second conversion tables, “1” does not continue for 2 bits or more, and “0” does not continue for 6 bits or more. Those who satisfy the conditions are selected.

[0005]

In the conventional recording coding described above, usually, when evaluating the characteristics of the recording code, the minimum inversion interval Tmin, the maximum inversion interval Tmax, the detection window width Twin, and the DC component DC It is common to evaluate by. Here, the smaller the minimum inversion interval, the larger the maximum inversion interval, and the larger the detection window width, the more DC is F
It is desirable to be in the REE state. However, as mentioned above,
7, the minimum inversion interval Tmin = 1.33T, the maximum inversion interval Tmax = 5.33T, and the detection window width Twin =
There is a problem that the DC is not in the Free state at 0.67T. Therefore, in such a recording system, there is a demand for recording encoding in which the minimum inversion interval Tmin is small or the DC is in a free state.

In the latter, the minimum inversion interval is small, the maximum inversion interval and the detection window width are large, and DC is
There is a problem that the conversion pattern is limited because the number of conversion tables is two, although the conversion can be made to the REE state.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and converts 16-bit bit data into 25-bit channel bits using a predetermined conversion table, and then converts the code into a digital recording disk device in accordance with the NRZI rule. A recording encoding device for recording channel bits, wherein the predetermined conversion table includes first to third conversion tables,
Of the 25 channel bits having a bit pattern, "1" does not continue for 2 or more bits, "0" does not continue for 8 or more bits except at the end of the table, and 7 bits do not continue at the end of the table. Among the bit patterns, in the first conversion table, the CDS is positive and the first is “01”, “001”, “0001”,
“00001”, “000001”, “000000”
The second conversion table is composed of a 65536-bit pattern in which all bit patterns starting from "1" and a specific bit pattern starting from "1" are added.
DS is negative and initially "01", "001",
“0001”, “00001”, “000001”,
6 which includes all bit patterns starting from "0000001" and specific bit patterns starting from "1"
The third conversion table C is composed of 5536 bit patterns, and the third conversion table C is composed of the remaining bit patterns. By optimally selecting the first to third conversion tables, the shortest continuous bit number is reduced to 2 bits and the longest It is an object of the present invention to provide a recording code conversion apparatus capable of reducing the number of continuous bits to 8 bits and reducing DC.

[0008]

To achieve the structure above object to an aspect of, the invention according to claim 1, 1
The 6-bit bit data is converted into 2 by a predetermined conversion table.
After transcoding into 5 channel bits, NR
A recording encoding device for recording the code-converted channel bits on a digital recording disk device in accordance with the ZI rule, wherein the predetermined conversion table includes first to third conversion tables, and a 25-bit pattern having a 33554432 bit pattern. For the channel bits,
Of the bit patterns in which "1" does not continue for more than 2 bits, "0" does not continue for more than 8 bits except at the end of the table, and 7 bits do not continue at the end of the table, the first conversion In the table, the CDS is positive, and the first is “01”, “001”, “0001”, “00”.
001 "," 000001 ", and 6500000 bit patterns including a specific bit pattern starting from" 1 "and a specific bit pattern starting from" 1 ". The second conversion table has a negative CDS. Yes, and the first is "01", "001", "000"
1 "," 00001 "," 000001 "," 0000 "
All bit patterns starting from “001” and “1” at the beginning
The conversion table C is composed of a 65536 bit pattern to which a specific bit pattern starting from
Is composed of the remaining bit patterns. By optimally selecting the first to third conversion tables, the shortest continuous bit number is set to 2 bits, the longest continuous bit number is set to 8 bits, and DC is reduced. There is a configuration.

[0009] The invention according to claim 2 is based on claim 1.
Wherein the combination of the first conversion table and the second conversion table is such that when one is a positive CDS and the other is a negative CDS and one starts from “1”, When the other always starts from "0" and one starts from "01", the other is not specified and may be blank. The third conversion table includes the first conversion table and the second conversion table. The bit pattern not used in the conversion table is arbitrarily arranged.

Further, according to a third aspect of the present invention, in the recording code conversion apparatus according to the first or second aspect,
In the third conversion table, the leading part of the code-converted channel bits is the same bit data and the CDS
Correspond to the same bit data as the bit data of the first conversion table or the second conversion table having the opposite polarity.

Further, according to a fourth aspect of the present invention, in the recording code conversion apparatus according to any one of the first to third aspects, the first to third conversion tables include a last part of a bit pattern and a next part. At the connection point at the beginning of the bit pattern,
Under the condition that the minimum number of continuous bits is set to 2 bits and the maximum number of continuous bits is set to 8 bits, the DSV after one symbol conversion is selected so as to be the most reduced.

Further, according to a fifth aspect of the present invention, in the recording code conversion apparatus according to the fourth aspect, the selection is made by 1
The configuration is such that a conversion table for reducing the total absolute value of the DSV is selected from the first to third conversion tables while performing the tentative code conversion for the longest period exceeding the symbol.

Further, according to the present invention, the NRZI data is converted after converting the 16-bit bit data into the 25-bit channel bits by a predetermined conversion table.
A recording encoding device for recording the code-converted channel bits on a digital recording disk device in accordance with rules, wherein the predetermined conversion table includes first to third conversion tables and a 25-bit channel having a 355544432 bit pattern. For the bit, "1"
Are not continuous for more than 2 bits, "0" is not continuous for more than Tmax bits except at the end of the table, and (Tmax-k) bits are not continuous at the end of the table. , CDS is positive and “1” or “0” is 1 to 1 at the beginning (Tmax−1)
After the continuation of bits, the second conversion table is composed of a pattern starting from “1”. In the second conversion table, CDS is negative and “1” or “0” is 1 to (Tmax) at the beginning.
-1) After consecutive bits, it is composed of a pattern starting from "1". Table C is composed of the remaining patterns. By selecting these tables optimally, the minimum number of consecutive bits is reduced to 2 bits and the maximum The number of continuous bits is set to Tmax, and DC is reduced.

According to a seventh aspect of the present invention, in the recording code conversion apparatus according to the sixth aspect, one of the combination of the first conversion table and the second conversion table is a positive CDS and the other is a negative CDS. When one starts from “1”, the other always starts from “0”, and one starts from a pattern in which “1” appears after “0” continues for 1 to k bits. When doing so, the other is not specified and may be blank, and the third conversion table is configured to arbitrarily arrange patterns not used in the first conversion table and the second conversion table.

Further, according to an eighth aspect of the present invention, in the recording code conversion apparatus according to the sixth or seventh aspect,
In the third conversion table, the leading part of the code-converted channel bits is the same bit data and the CDS
Correspond to the same bit data as the bit data of the first conversion table or the second conversion table having the opposite polarity. Further, according to a ninth aspect of the present invention, in the recording code conversion apparatus according to any one of the sixth to eighth aspects, the first to third conversion tables include a last part of a bit pattern and a next bit pattern. At the connection point at the head, the DSV after one-symbol conversion is selected to be the lowest while satisfying the condition that the minimum number of continuous bits is set to 2 bits and the maximum number of continuous bits is set to Tmax. The configuration is as follows.

According to a tenth aspect of the present invention, in the recording code conversion apparatus according to the ninth aspect, the selection is made by:
The configuration is such that a conversion table for reducing the total absolute value of the DSV is selected from the first to third conversion tables while performing the provisional code conversion for the longest period exceeding one symbol.

Further, according to an eleventh aspect of the present invention, in the recording code conversion apparatus according to any one of the first to tenth aspects, the channel bits are configured such that "1" does not exist in 25-bit data. is there.

According to a twelfth aspect of the present invention, in the recording code conversion apparatus according to any one of the first to tenth aspects, the channel bits have a continuous pattern of "10" in 25-bit data. There is no configuration.

According to a thirteenth aspect of the present invention, in the recording code conversion device according to any one of the first to twelfth aspects, the first and second conversion tables may include any one of the patterns or , A set of two patterns or a plurality of patterns are used as synchronization signals, and the patterns are excluded from the first and second conversion tables and are not used as data.

Further, according to a fourteenth aspect of the present invention, in the recording code conversion apparatus according to any one of the first to twelfth aspects, the third conversion table includes an arbitrary one pattern or a plurality of patterns. The pattern is used as a synchronization signal, and its pattern is removed from the third conversion table and is not used as data.

[0021] effects present invention, after the code conversion channel bit 25-bit by 16-bit bit data a predetermined conversion table, a digital recording disk apparatus according to NRZI rule when recording channel bits this code conversion, Of the patterns in which “1” does not continue for more than 2 bits, “0” does not continue for more than Tmax bits other than at the end of the table, and (Tmax−k) bits do not continue at the end of the table, the first conversion In the table, the CDS is positive and “1” or “0” is 1 to (Tmax) at the beginning.
-1) After a continuation of bits, a pattern starting from "1" is formed.

In the second conversion table, CDS is negative and "1" or "0" is 1 to (T
After a maximum of (max-1) bits, the pattern is formed by a pattern starting from "1", and the third conversion table is formed by the remaining patterns. Further, regarding the combination of the first conversion table and the second conversion table, one CDS is made positive and the other CDS is made negative, and when one starts from “1”, the other always becomes “0”. ".

At this time, if one starts with a pattern in which "1" appears after "0" continues for 1 to K bits, the other is not defined and may be blank (unused). Thus, the minimum inversion interval Tmin
Is 1.12T, the maximum inversion interval Tmax is 5.12T to 4.48T, the detection window width Twin is 0.64T, and
Put DC in Free state.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows that 16-bit data
4 shows an example of a conversion table for converting to channel bits. The combination of 16-bit data is 65
There are 536 bit patterns, and the combination of 25 channel bits allocated therefrom is 3355 bits in total.
There are 4432 bit patterns. And this 335
In the 34432 bit pattern, "1" does not continue for 2 bits or more, "1" does not exist for 12 bits or more of 25 bits, "0" does not exist for 8 bits or more, and " A combination of bit data in which 0 ″ is not continuous for 7 bits or more has a 158816 bit pattern.

Here, "1" is not continuous for 2 bits or more is a condition for setting the minimum number of continuous bits to 2 bits, and "1" is not present for 12 bits or more in 25 bits is "101010". This is a condition for preventing the occurrence of a PLL shift due to the continuation of the shortest continuous bit pattern due to the large number of “1” as in “. The condition that “0” is not continuous for 8 bits or more is a condition for setting the longest continuous bit number to 8 bits. If “0” does not continue for 7 bits or more at the end of a symbol, the beginning of the next symbol that follows is “0”.
When starting with 1, this is a condition for setting the maximum number of consecutive bits at the connection point to 8 bits.

Here, CDS (CodeWordDig)
italSum) is defined as a value obtained by subtracting the number of “L” bits from the number of “H” bits as a DC level value after converting 25-channel bit data according to the NRZ / NRZI rule. This is a value obtained by integrating 25 bits starting from “L” and converting “L” to −1 and “H” to +1 when channel bits are converted according to the NRZ / NRZI rule.

For example, “00001010000010”
In the channel bit data composed of “00100101010”, starting from “L”, NRZ / N
When converted according to the RZI rule, "LLLLHHLLL
LLLHHHHLLLLHLLHH ", and when" L "is -1 and" H "is +1 and 25 bits are integrated,
It can be seen that the CDS is -5.

When the data converted according to the NRZ / NRZI rule starts from "L" in the above 158816 bit patterns, the CDS is positive, and the bit pattern shown below depends on the first bit pattern. Will exist. The table starting from "1" at the beginning has a 39637 bit pattern. The table starting from “01” is 21506
Bit pattern exists. The table starting from “001” at the beginning is 1124
There are 9 bit patterns. The table starting from “0001” is 561
There is an 8-bit pattern. The table starting from “00001” is 26
There are 58 bit patterns. The table starting from "000001" is 1
There are 173 bit patterns. The table that starts with "0000001" first
There are 473 bit patterns. The table starting from “00000001” at the beginning has a 168-bit pattern.

When the data converted according to the NRZ / NRZI rule starts from "L", the CDS is negative, and the following bit pattern exists according to the first bit pattern. The table starting from "1" at the beginning has a 21371 bit pattern. A table starting from “01” at the beginning is 16629
Bit pattern exists. The table starting from “001” at the beginning is 1257
There are two bit patterns. The table starting from “0001” is 925
There is an 8-bit pattern. The table starting from “00001” is 66
There is a 32-bit pattern. The table starting from "000001" is 4
There are 628 bit patterns. The table that starts with "0000001" first
There are 3150 bit patterns. The table starting from "00000001" has a 2094 bit pattern.

Next, when the data after the NRZI conversion starts from “L” as the table A, the table with the positive CDS is determined by the 65536-bit pattern, and the table B is determined.
When the data after NRZI conversion starts from “L”, a table with a negative CDS is determined as a 65536-bit pattern, and a table for CDS adjustment is determined as a table C as a remaining 27744-bit pattern.

As for the table A, the CDS is positive and the first is "01", "001", "0001".
"000001""0000001""00000000"
The table starting from "1" adopts all 42845 patterns, and further adds 22691 patterns in the table 39637 patterns starting from "1" to 65
536 patterns. The remaining 16946 patterns starting from “1” at the beginning are defined as Table C. Further, as for the table A, the first is "1""01"
“001” “0001” “00001” “00000”
1 "," 0000001 "," 00000001 ".
5618, 2658, 1173, 473 and 168 bit patterns are arranged in this order.

Next, as for the table B, the CDS is negative and the first is "01""001""0001".
"000001""0000001""00000000"
The table starting from "1" adopts all 5,4963 patterns, and the table starts with "1" and adds 10573 patterns in the 21371 patterns.
536 patterns. The remaining 10798 patterns starting from “1” at the beginning are set as table C. Further, in the table B, "1""01""001"
“0001” “00001” “000001” “000
0001 "and" 00000001 "in the table 2094, 3150, 4628, 6632, 925
8, 12,572, 16629, and 10573 bit patterns are arranged in this order.

Next, as for the table C, when the NRZI-converted data starts from "L", the CDS is negative and the pattern starting from "1" is not used in the table B. In the table A, the 10798 pattern is also started from “1” at the beginning, and
The data is arranged from the same start position as the data where the DS is correct, so that selection for reducing the absolute value of the DSV can be easily performed. Also, among the patterns whose CDS is positive and whose pattern starts with “1”, 16946 patterns that are not used in the table A are stored in the table B, and the data whose pattern starts with “1” and whose CDS is negative Are arranged from the same rearmost position as the arrangement, so that selection for reducing the absolute value of DSV can be easily performed. Remaining 3
The 7792 pattern is blank (unused).

The conversion table composed of the tables A to C described above is added with 25-bit conversion data.
Data such as CDS or INV is stored. This INV starts from “L” and sets the channel bit to NR.
When Z / NRZI conversion is performed, the processing ends with “L” or “H”
Is the data indicating whether to end with "0" in the former case.
In the latter case, it becomes "1". That is, if there is an even number of “1” in the channel bits,
INV = "0", and if there is an odd number, INV = "1".

For example, “00001010000010”
In the channel bit data “001001001010”, since 7 bits of “1” exist, INV =
It becomes “1”, and after NRZ / NRZI conversion, ends with “H” if started from “L” and ends with “L” if started from “H”.
Ends with

1 using the above-described tables A to C
Conversion from 6-bit data to 25-channel bits is performed as follows. DSV and NZI are newly established. This DSV is a DC level value of the entire stream, and NZI is a value indicating the current “L” or “H” of the entire stream.
When "L", NZI = "0", when "H", NZI =
It becomes “1”. In addition, DSV = 0, N
It is assumed that ZI = 0.

The 16-bit data is converted into 25-channel bit data. Table A is used for the first symbol. At the same time, the DSS and NZI after the first symbol conversion are obtained by substituting the CDS value indicating the table into the DSV and substituting the INV value into the NZI.

Even after the second symbol, 16-bit data is converted into 25-channel bit data. Here, 277 of the patterns A, B or 65536 are used.
Regarding the 44 patterns, an optimum table is further selected from the table C by the following method.

(1) By selecting a certain table, a continuation of "1" or a continuation of "0" of 8 bits or more at the connection point between the immediately preceding 25 channel bit data and the target 25 channel bit data. When it occurs, it excludes the table from selection. As a result, when there is only one selectable table, that table is selected.

(2) When the number of selectable tables is two or more, the table in which the absolute value of DSV is reduced is selected. That is, when the immediately preceding NZI is “0”, 2
Since the five channel bits start from "L", the DSV is calculated by adding the immediately preceding DSV and the CDS value to the selectable table, and the table having the smaller absolute value is selected. If the DSVs have the same value, either table may be selected. Also, immediately before NZI
Is “1”, the 25 channel bits start from “H”.
And (-1 * CDS) are added to calculate a new DSV, and the table having the smaller absolute value is selected. DS
If V has the same value, either table may be selected. In the case described above, the table in which the absolute value of the DSV becomes smaller is selected for each symbol. However, the table in which the provisional code conversion is performed over a longer period and the absolute value of the total DSV is reduced is selected. Is also good.

After selecting the table, DSV and NZI are updated. When the immediately preceding NZI is “0”, the 25 channel bits start from “L”.
Add DS value and assign to new DSV. Assign INV to the new NZI. When the immediately preceding NZI is “1”, the 25 channel bits start from “H”.
The immediately preceding DSV value and the (-1 * CDS) value are added and assigned to a new DSV, and the inverted data of INV (INV =
"1" is assigned to the new NZI when "0", and "0" when INV = "1". Then repeat ~

The modulation code is output after the parallel / serial conversion of the 25-channel bit data and the NRZ / NRZI conversion. The inverse conversion (decoding) of 16 to 25 using this table is performed as follows. The input modulation code is
After NRZI / NRZ conversion and serial / parallel conversion, 25 channel bits are converted into 16-bit data and output.

FIG. 2 shows a circuit block for realizing the above conversion system. In FIG.
Input from the input unit 201 as bits. The 16-bit data 202 whose timing is adjusted by the 1-clock latch D is stored in the 16-25 modulation ROM 2.
03 is input. This 16-25 modulation ROM 203
Stores tables A, B, and C, and one table is finally selected from these tables. Here, from the tables A, B, and C, the 25-bit channel bit data 204 and the 8-bit flag data 205
Is output. The 8-bit flag data includes a 7-bit CDS indicated by a 2's complement and 1-bit INV.

M in 25 channel bit data 204
The SB7 bit data 207 is the LSB 7 bit data 2 in the 25 channel bit data 204 one clock before.
08 and to the condition determination circuit 206. In the condition determination circuit 206, the connection of "1" or "0" at the connection point between the LSB 7-bit data 208 one clock before and the MSB 7-bit data 207 corresponding to the tables A, B, and C of the main clock. It is determined whether or not there is a continuation of 8 bits or more. If either of them exists, the selection non-permission flag 209 of the corresponding table is set to “1”.

Next, of the flag data, the 7-bit C
The DS data 211 and the 7-bit DSV data 215 and 216 in the flag data one clock before are input to the DSV calculation circuit 210 as 1-bit NZI data 212. The DSV calculation circuit 210 calculates new DSV data 213 from the DSV data 215 and 216 one clock before and the CDS data 211 corresponding to the tables A, B and C of the main clock.

Here, the NZI data 21 one clock before
2 when NZI = "0", NRZ / N
In order to start the data after the RZI conversion from “L”, the CDS data 211 of the main clock is added to the DSV data 212 of the previous clock to form new DSV data 213. However, the NZI data 212 of the previous clock is NZI =
When “1”, the data after NRZ / NRZI conversion starts from “H” in this clock, so that D
The new DSV data 213 is obtained by adding the (-1 * CDS) data 211 of this clock to the SV data 212.
Then, new DSV data 213 is output. Also,
The comparison / selection circuit 214 receives the 25-bit channel bit data 204, the 8-bit flag data 205, the selection non-permission flag 209, and the new DSV data 213 corresponding to the tables A, B, and C.

Here, first, the selection non-permission flag 209 is set.
Is “1”, that is, non-permitted tables are not selected,
The absolute value of the new DSV data 213 is compared among the selectable tables, and the table having the smallest value is finally selected. From the selected table, it outputs to the 25-channel bit data 217 and simultaneously outputs the 7 MSB bits in the 25-channel bit data 217 to the condition determination circuit 208 in the next clock. Also, a new 7-bit DSV data 2 calculated from the selected table 2
15 is output.

Here, the comparison / selection circuit 214 has a DSV
A limiter circuit (not shown) is built in when data exceeds the range of 7 bits. At the same time, the INV of the selected table and the NZI data 212 one clock before are output.
And outputs new NZI data 216 by taking the exclusive OR of The 25 channel bit data 217 has a parallel /
Serialized by a serial conversion circuit (P / S) 218, the NRZ /
The NRZI conversion is performed by the NRZI conversion circuit 219 and output as a modulated bit stream 220.

FIG. 3 shows a circuit block for realizing the above inverse conversion system. In the figure, an input modulation code 301 is converted into N by an NRZI / NRZ conversion 302.
It is converted to RZ and serial / parallel converter (S / P) 303
And the timing is adjusted by the D-flip-flop 304. The 25-channel demodulation ROM 305 stores 25 channel bit data in 16 bits.
Converted to bit data. This RO for 25-16 demodulation
M305 incorporates all tables A, B, and C, and outputs bit data for all channel bits. Further, 16-bit data 307 is output via the D flip-flop 306.

Next, FIG. 4 shows a modification of the conversion table shown in FIG. Referring to FIG.
The CDS is positive, and all of the table 39637 patterns starting from "1" and the table 21506 patterns starting from "01" are all adopted, and the first is "0".
43 out of 11249 patterns in table 11249 starting from 01 "
A total of 65536 patterns is obtained by adding 93 patterns. The remaining first is 6856 patterns in the 11249 patterns starting from “001”, and the first is “0001” “000”
Tables 5618, 2658, 1173, 47 starting from "001""0000001""00000001"
Table C is a total of 16946 patterns of 3,168 patterns. In the table A, "1" and "0" are initially set.
Tables 39637 and 21 starting from “1” “001”
506, 4393 bit patterns are arranged in this order.

Regarding the table B, the CDS is negative, and the table 213 starts from “1” at the beginning.
Table 1 with 71 patterns, first starting with "01"
65,536 patterns obtained by adding all 6629 patterns, the table 12572 pattern starting from "001", and the table 9258 pattern starting from "0001", and adding 5706 patterns in the 6632 pattern starting from "00001" And Table 6 starting with “00001”
926 patterns out of 632 patterns, the first being “00000”
Tables 4628, 3150, and 2094 patterns starting from “1”, “00000001”, and “00000001” have a total of 10798 patterns as Table C. In Table B, “00001”, “0001”, and “0” are initially set.
Table 5706 starting from “01” “01” “1”
9258, 12572, 16629, and 21371 bit patterns are arranged in this order.

As for the table C, the NRZI
When the converted data starts from "L", the CDS is positive and the first is "00000001""0000"
001 "" 000001 "" 00001 "" 0001 "
Of the patterns starting from “001”, 16946 patterns not used in table A are arranged from the beginning, and C
DS is negative and “00000001” at the beginning
Of the patterns starting from “0000001” and “000001”, the 10798 pattern not used in the table B is placed at the end, and the remaining 37792 patterns are blank (unused).

FIG. 5 shows another modification. FIG. 11 is an example of a table that realizes Tmax = 7T.
In the figure, there are a total of 65536 patterns of 16-bit data combinations, and 2
The combination of 5 channel bits is 335544 in total.
There are 32 patterns. In this 33554432 pattern, “1” is not continuous for 2 bits or more, and “1” is 25 bits.
There are 135200 patterns of data combinations in which no more than 12 bits are present, no "0" is continuous for more than 7 bits, and no "0" is continuous for more than 6 bits at the end of the symbol.

Here, that "1" does not continue for 2 bits or more is a condition for setting the minimum inversion interval to 2T.
When "1" does not exist in 12 bits or more out of 25 bits,
This is a condition for preventing the occurrence of a PLL shift from occurring when the number of “1” s becomes large as in “101010. “0” is 7
"Consecutive bits or more" is a condition for setting the maximum inversion interval to 7T. The condition that “0” does not continue for 6 bits or more at the end of the symbol is a condition for setting the maximum inversion interval to 7T at the connection point when the head of the next symbol that follows starts at “01”.

Of the above 135200 bit pattern,
When the data converted according to the NRZ / NRZI rule starts from “L”, the CDS is positive, and the following bit patterns are present according to the first bit pattern. The table starting from "1" at the beginning has a 34286 bit pattern. The table starting from “01” at the beginning is 18557
Bit pattern exists. The table starting from “001” is 9603
Bit pattern exists. The table starting from “0001” at the beginning is 472
There are 5 bit patterns. The table starting from “00001” is 21
There are 74 bit patterns. The table starting from “000001” is 9
There are 23 bit patterns. The table that starts with "0000001" first
There are 352 bit patterns.

When the data converted according to the NRZ / NRZI rule starts from "L", the CDS is negative, and the following bit patterns exist according to the first bit pattern. The table starting from "1" at the beginning has a 17871 bit pattern. The table starting from “01” is 14284
Bit pattern exists. The table starting from “001” at the beginning is 1105
There is an 8-bit pattern. The table starting from “0001” is 827
There is a 0 bit pattern. The table starting with “00001” is 59
There are 99 bit patterns. The table starting from "000001" is 4
There are 217 bit patterns. The table that starts with "0000001" first
There are 2881 bit patterns.

Next, when the data after the NRZI conversion starts from “L” as the table A, the table in which the CDS is positive is determined by the 65536-bit pattern, and the table B is determined.
When the data after NRZI conversion starts from “L”, a 65536-bit pattern is determined for a table with a negative CDS. However, table A having a positive CDS has no problem because the number of candidates is larger than 70620 patterns and 65536 patterns. However, table B having a negative CDS has 95580 candidates having 64580 patterns and 95536 patterns.
A part of the table B becomes blank because it is smaller by six patterns. Therefore, by associating the pattern starting with “01” of the table A with the 956 pattern of the table B, the conversion is always performed using the pattern of the table A, and the conditions of Tmin and Tmax are satisfied.
As table C, the remaining CDS adjustment table is 508.
It is determined to be a 4-bit pattern.

Here, regarding the table A, the CDS is positive and the first is "01", "001", "000".
The table starting from "1", "000001", and "0000001" adopts all 36334 patterns, and further adds 29,202 patterns among the 34,286 patterns starting from "1" to make 65536 patterns. The remaining 5084 patterns to be started are table C. In table A, the first is "1""01""001""0001""0000".
1 "," 000001 ", and" 0000001 "are stored in 29202, 18557, 9603, and 472 tables.
5,2174,923,352 patterns are arranged in this order.

As for the table B, the CDS is negative and "1", "01", "001" and "0"
001 "00001" 000001 "0000
The table starting from “01” adopts all the 64580 patterns. At this time, 956 patterns become blank, but by associating the pattern starting with “01” of table A, the pattern of table A must be used. And the conditions of Tmin and Tmax are satisfied.
1 "000001" 00001 "0001" 0
01, "01", table 2881 starting from "1",
4217, 5999, 8270, 11058, 1428
4, 17871 patterns. A space of 956 patterns is inserted between the pattern starting from “01” and the pattern starting from “1”.

Regarding the table C, when the NRZI-converted data starts from “L”, the CDS is positive, and 5084 of the patterns starting from “1” that are not used in the table A The pattern is placed at the end, and the remaining 60452 patterns are blank (unused)
And

By the way, a shift of the break of the conversion may occur due to a shift of the PLL or the like. In order to recover from this, a synchronization signal is periodically inserted into the stream in advance. The synchronization signal is any one of the tables A and B, two patterns in the set,
Or use multiple patterns. The pattern used as the synchronization signal is removed from the table, and is not used as data. Alternatively, one or a plurality of arbitrary patterns in the table C are used as the synchronization signal. As described above, a plurality of tables can exist.

What is important in realizing the present invention is that
It suffices that the combination of 25 channel bits satisfies the following conditions. "1" does not continue for 2 or more bits "1" does not exist for i bits or more in 25 bits "0" does not exist for (Tmax) bits or more "0" does not continue for (Tmax-1) bits at the end of the symbol Yes, as a combination of table A and table B, one is a positive CDS and the other is a negative CDS When one starts from “1”, the other is always “0”
However, when one starts from “01”, the other is not defined and may be blank (unused).

Further, when the conditions are generalized, this 25-bit combination only needs to satisfy the following conditions. "1" does not continue for 2 bits or more "1" does not exist for i bits or more in 25 bits "0" does not continue for (Tmax) bits or more "0" does not continue for (Tmax-K) bits or more at the end of the symbol As a combination of tables A and B, one is a positive CDS and the other is a negative CDS. When one starts from “1”, the other is always “0”.
However, if one is “0”, 1 bit to K
When starting from a pattern in which “1” appears after consecutive bits, the other is not defined and may be blank (unused).

Therefore, as long as the above condition is satisfied, the tables A and B may be exchanged, the entire tables A, B and C may be exchanged vertically, the tables A and B may be exchanged, and the tables A and B may be exchanged. The entirety of B and C may be exchanged upside down, or the table C may be deleted. Of course, the data may be replaced at random regardless of the embodiment of FIGS. Further, in the above-described example, it is assumed that “1” does not exist in 12 bits or more out of 25 bits, but this may be a numerical value other than 12 bits, or this condition may not be present. Further, for example, a condition that the continuation of “10” is j patterns or less may be set. As long as the above condition is satisfied, the maximum inversion interval Tmax is 8
It is also possible to have T, 7T and below, or 9T and above. Further, in the present embodiment, the tables A, B, and C are selected by the DSV, but may be selected by other methods.
For example, a configuration may be adopted in which the number of inversions is selected so as to increase.

[0065]

As described above, according to the present invention, 16-bit bit data is code-converted into a 25-bit channel bit by a predetermined conversion table, and then the code-converted channel bit is converted into a digital recording disk device in accordance with the NRZI rule. Is recorded, "1" does not continue for 2 bits or more, and "0" is T except for the end of the table.
It does not continue for more than max bits, and (T
Among the patterns in which max-k) bits are not continuous, the first conversion table indicates that the CDS is positive, and that the first "1" or "0" is 1 to (Tmax-1) bits and then becomes "1". ".

In the second conversion table, CDS is negative, and "1" or "0" is 1 to (T
After a maximum of (max-1) bits, the pattern is formed by a pattern starting from "1", and the third conversion table is formed by the remaining patterns. Further, regarding the combination of the first conversion table and the second conversion table, one CDS is made positive and the other CDS is made negative, and when one starts from “1”, the other always becomes “0”. ".

At this time, if one starts with a pattern in which "1" appears after "0" continues for 1 to K bits on the other hand, the other is not defined and may be blank (unused). Thus, the minimum inversion interval Tmin
Is 1.12T, the maximum inversion interval Tmax is 5.12T to 4.48T, the detection window width Twin is 0.64T, and
It is possible to provide a recording code conversion device capable of setting DC in a Free state.

[Brief description of the drawings]

FIG. 1 is a diagram showing a code conversion table for 16-bit data and 25-channel bit data in a recording code conversion device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a code conversion circuit for 16-bit data and 25-channel bit data in a recording code conversion device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a code inversion circuit for 16-bit data and 25-channel bit data in a recording code conversion apparatus according to an embodiment of the present invention.

FIG. 4 is a diagram showing a modified example of a code conversion table for 16-bit data and 25-channel bit data in the recording code conversion apparatus according to one embodiment of the present invention.

FIG. 5 is a diagram showing another modified example of the code conversion table for 16-bit data and 25-channel bit data in the recording code conversion device according to one embodiment of the present invention.

FIG. 6 is a diagram showing a code conversion table for 16-bit data and 25-channel bit data in a conventional recording code conversion device.

[Explanation of symbols]

210 Data input 202 Modulation ROM input data 203 16-25 Modulation ROM 204 25-bit data output from modulation ROM 205 Flag output from modulation ROM 206 Condition determination circuit 207 MSB 7 bits during 25-bit data output 208 1 clock LSB 7 bits in 25-bit data output previously modulated 209 Condition judgment circuit output 210 DSV calculation circuit 211 Flag output from modulation ROM 212 DSV and NZI data up to data end point one clock before 213 Data end of this clock DSV data up to the point 214 Comparison selection circuit 215 DSV data up to the data end point one clock before 216 NZI data up to the data end point one clock before 217 25-bit conversion data output 218 Parallel / serial conversion circuit 21 NRZ / NRZI converting circuit 220 data output

Claims (14)

(57) [Claims] 1. A recording encoding apparatus for encoding a 16-bit bit data into a 25-bit channel bit according to a predetermined conversion table, and recording the code-converted channel bit on a digital recording disk device in accordance with the NRZI rule. The predetermined conversion table includes first to third conversion tables, and is a case where two or more “1” s are not continuous for 25-bit channel bits, and is “0” except at the end of the table. Is a bit pattern in which no more than 8 bits are continuous and 7 bits are not continuous at the end of the table, the first conversion table has a positive CDS and the first is "01", "001", "000
1 "," 00001 "," 000001 "," 0000 "
All bit patterns starting from “001” and “1” at the beginning
, The second conversion table has a negative CDS, and the first is "01", "001", "0001", "0000".
1 "," 000001 ", and a bit pattern obtained by adding a specific bit pattern starting from" 000001 "and a first bit pattern starting from" 1 ". By selecting the first to third conversion tables optimally, the shortest continuous bit number is set to 2 bits, the longest continuous bit number is set to 8 bits, and DC is reduced. Code conversion device. 2. The recording code conversion apparatus according to claim 1, wherein one of the first conversion table and the second conversion table is a positive CDS and the other is a negative CDS, and one is a negative CDS. When starting from “1”, the other always starts from “0”, and when one starts from “01”, the other is not specified and may be blank.
A recording code conversion device, wherein bit patterns not used in the first conversion table and the second conversion table are arbitrarily arranged in the third conversion table. 3. The recording code conversion device according to claim 1 or 2, wherein the third conversion table is configured such that a head portion of the code-converted channel bits is the same bit data, and the CDS is a CDS.
Correspond to the same bit data as the bit data of the first conversion table or the second conversion table having the opposite polarity. 4. The recording code conversion apparatus according to claim 1, wherein the first to third conversion tables are connected to a last part of a bit pattern and a first part of a next bit pattern. At this point, while satisfying the conditions for realizing that the shortest continuous bit number is 2 bits and the longest continuous bit number is 8 bits,
A recording code conversion apparatus characterized in that a DSV after one symbol conversion is selected so as to be most reduced. 5. The recording code conversion apparatus according to claim 4, wherein the selection is to perform a provisional code conversion for the longest period exceeding one symbol while reducing the absolute value of the total DSV. A recording code conversion apparatus, wherein a table is selected from the first to third conversion tables. 6. A recording encoding apparatus for encoding 16-bit bit data into 25-bit channel bits according to a predetermined conversion table, and recording the code-converted channel bits on a digital recording disk device in accordance with NRZI rules. The predetermined conversion table includes first to third conversion tables. Of the 25-bit channel bits, “1” is not continuous for more than 2 bits, and “0” is Tmax bits except at the end of the table. Of the patterns that are not continuous and the (Tmax−k) bits are not continuous at the end of the table, the first conversion table has a positive CDS and the first “1” or “0” is 1 to 1. The second conversion table is composed of a pattern starting from “1” after (Tmax−1) bits have been continued. , CDS are negative, and at the beginning, "1" or "0" is composed of a pattern starting from "1" after 1 to (Tmax-1) consecutive bits, and Table C is composed of the remaining patterns. By selecting these tables optimally, the minimum number of consecutive bits is set to 2 bits, and the maximum number of consecutive bits is set to Tmax.
A recording code conversion device characterized by reducing DC. 7. The recording code conversion apparatus according to claim 6, wherein one of the first conversion table and the second conversion table is a positive CDS and the other is a negative CDS, and one of the combinations is a negative CDS. When starting from "1", the other always starts from "0". When one starts from a pattern in which "1" appears after "0" continues for 1 to k bits, the other is specified. A recording code conversion apparatus, wherein a pattern not used in the first conversion table and the second conversion table is arbitrarily arranged in the third conversion table. 8. The recording code conversion device according to claim 6, wherein the third conversion table is configured such that a head portion of the code-converted channel bits is the same bit data and a CDS
Correspond to the same bit data as the bit data of the first conversion table or the second conversion table having the opposite polarity. 9. The recording code conversion apparatus according to claim 6, wherein the first to third conversion tables are configured to connect a last part of a bit pattern and a first part of a next bit pattern. At this point, while satisfying the conditions for realizing that the shortest continuous bit number is 2 bits and the longest continuous bit number is Tmax,
A recording code conversion apparatus characterized in that a DSV after one symbol conversion is selected so as to be most reduced. 10. The recording code conversion apparatus according to claim 9, wherein the selection is to perform a provisional code conversion for the longest period exceeding one symbol while reducing the absolute value of the total DSV. A recording code conversion apparatus, wherein a table is selected from the first to third conversion tables. 11. The recording code conversion apparatus according to claim 1, wherein the channel bit is “1” in 25-bit data.
A recording code conversion device characterized in that there is no such code. 12. The recording code conversion apparatus according to claim 1, wherein said channel bit is "1" in 25-bit data.
A recording code conversion apparatus characterized in that a continuous pattern of 0 "does not exist. 13. The recording code conversion device according to claim 1, wherein the first and second conversion tables are each composed of an arbitrary one of them.
A pattern or a set of two patterns or a plurality of patterns is used as a synchronization signal, and the pattern is removed from the first and second conversion tables and is not used as data. Recording code conversion device. 14. The recording code conversion apparatus according to any one of claims 1 to 12, wherein the third conversion table uses any one pattern or a plurality of patterns as a synchronization signal. And the pattern is removed from the third conversion table and is not used as data.