JP3326617B2 - Accumulator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an accumulator circuit suitable for use in a frame difference detection circuit of a high-definition television receiver and the like, and more particularly to an accumulator circuit capable of shortening the accumulated processing time.

[0002]

2. Description of the Related Art In a high-definition television receiver adopting the MUSE system or the like, the compensation operation of a motion vector compensation circuit differs depending on whether a video is a moving image or a still image. In some cases, a frame difference detection circuit 10 as shown in FIG. 6 is used.

[0003] In a frame difference detection circuit 10 shown in FIG. 1, a luminance signal of an input video signal is supplied to a terminal 11, which is delayed by one frame in a frame delay circuit 12.
The frame delay luminance signal is subtracted from the current luminance signal, and a frame difference signal is detected. The absolute value of the frame difference signal is further detected by an absolute value detection circuit 14, which is further supplied to an accumulator circuit 20 and accumulated within a predetermined time.

When the frame difference detection output (cumulative output) output from the terminal 16 is equal to or more than a predetermined value, it is regarded as a moving image. Processing operations are controlled as desired.

As an accumulator circuit 20 used for such a frame difference detection process, there is a case where a circuit configuration as shown in FIG. 7 is used. FIG. 1 shows the most popular circuit configuration, which includes an adder 21 capable of high-speed processing, a memory (RAM in this example) 22 for storing the added output, and an AND circuit 23. The adder 21 has an n-bit 2-input adder configuration, and has a terminal 2
0a and the AND circuit 23
Are input, and the result of addition of the two (n +
The added output of k) bits (k is an integer) is stored in the RAM 22. The addition output read from the RAM 22 is output to the output terminal 20b and is input to the AND circuit 23. A clear signal is further supplied to the AND circuit 23 from a terminal 24, and the initial state of the accumulator is set.

[0006]

By the way, in the accumulator circuit configured as described above, the addition result itself stored in the RAM 22 is returned to the input side, added again to the input signal, and the accumulated result is stored in the RAM 22. Like that. In many cases, an adder having a relatively long word length is used as the adder 21.

For this reason, as the cumulative number increases, the delay time associated with the carry in the adder 21 increases, and the operating speed decreases. The only way to shorten the addition processing time is to use an adder capable of high-speed processing as the adder 21. However, as is well known, an adder capable of high-speed processing has a large circuit scale and is expensive.

The present invention has been made to solve such a conventional problem, and proposes an accumulator circuit capable of improving the processing speed without using an adder capable of high-speed processing.

[0009]

In order to solve the above-mentioned problems, the present invention provides an n-bit lower accumulator having an n-bit two-input adder and a memory for storing the output of the adder, and an n-bit lower accumulator. A digital input signal composed of n bits is supplied to the lower accumulator, added to the previous accumulated output, output as an n-bit signal, and output from the input signal. The MSB and the carry signal obtained from the adder are supplied to the upper bit determination circuit, and the upper bit k (k is an integer of 1 or more) at that time is determined based on both signals, and the (n + k) bits are determined. The signal is output from an accumulator circuit.

[0010]

In FIG. 1, an n-bit input signal is added to an n-bit addition output signal (a signal passed through an initialization gate) read from a RAM 32 in a lower accumulator 20A. The addition output is also n bits.

The most significant bit MSB of the input signal is supplied to an upper bit decision circuit 20B together with the carry signal output from the adder 31. Upper bit determination circuit 20B
In FIG. 2, as shown in FIG. 2, whether the input signal is positive or negative and the content of the carry signal at that time (carry or borrow), the increase / decrease processing in the increase / decrease circuit 41 (“+1” with respect to the output of the RAM 42)
Process or “−1” process) is controlled.

That is, in the upper bit determination circuit 20B, when the input signal is positive, the carry signal from the adder 31 is likely to be a carry, so that "+1" is calculated in advance, and the lower addition result is calculated. When the carry signal becomes "1", the calculated value is used as an upper bit. Similarly, when the input signal is negative, the carry signal is likely to be borrowed. In this case, "-1" is calculated in advance, and the carry signal of the lower addition result is actually "1".
When, the calculated value is used as upper bits.

As described above, if the upper bits are calculated separately from the lower bit addition processing, even if the cumulative number increases,
Accordingly, the processing time does not increase.

[0014]

Next, a case where an example of an accumulator circuit according to the present invention is applied to the above-described frame difference detection circuit system will be described in detail with reference to the drawings.

FIG. 1 is a system diagram showing an example of an accumulator circuit 20 according to the present invention, which comprises a lower accumulator 20A and an upper bit decision circuit 20B. The lower accumulator 20A has an adder 31 having a normal processing speed. The adder 31 receives an n-bit input signal from a terminal 20a and an addition output (n bits also) as a previous addition result. , Are added.

The addition output is a memory (RAM in this example) 32
And this is stored. N which is the memory output
The bit addition output is output to the terminal 20b as an addition result and is also supplied to the AND circuit 33. AND circuit 33
Since a clear signal (CLEAR bar) is supplied from the terminal 24 in addition to the addition output, the addition output becomes a gate output (logical product output) as it is after an initial stage such as when the power is turned on. The gated addition output is supplied to the above-described adder 31 as a result of the immediately preceding addition.

As shown in the figure, the upper bit decision circuit 20B includes an increase / decrease circuit 41, a memory (RAM in this example) 42 for storing the increase / decrease output, and a logic circuit for generating a signal for controlling the RAM 42. It is composed of a group (an exclusive OR circuit 43 and a NOR circuit 44).

The increase / decrease circuit 41 determines in advance whether the result of addition in the adder 31 is a carry or a borrow, based on the value of the input signal, and determines the higher-order bits of k bits (k is an integer) according to the result of the determination. (In this example, a 2-bit configuration). Therefore, the most significant bit MSB of the input signal supplied to the terminal 20a is supplied to the increase / decrease control terminal of the increase / decrease circuit 41, and the MSB is “0” as shown in FIG.
Depending on whether it is "1" or not, it is determined whether "+1" or "-1" is given to the previous upper bit signal input thereto.

The upper bit signal output from the increase / decrease circuit 41 is supplied to a RAM 42 functioning as a memory, and when a carry is added to the addition result or when the MSB of the input signal is "1", the upper bit signal is output. Is stored. Therefore, the MSB of the input signal and the carry signal are supplied to the exclusive OR circuit 43, and the exclusive OR output thereof is supplied to the enable terminal WE of the RAM 42 via the OR circuit 44. The OR circuit 44 is supplied with an inverted clear signal.

In the presence of this clear signal, rewriting of the RAM 42 is forced at the time of initialization, and 0, which is the output of the initialized counter, is written. In other cases, as shown in FIG. 2, when the MSB of the input signal is "1" or when the carry signal is "1", that is, when the addition result has a carry, the RAM 42 writes. When the RAM 42 is enabled, the RAM 42
Is stored in memory.

The memory output is supplied to the output terminal 20b as an upper bit signal, and is output as an (n + k) -bit addition output. Upper bit signal is further increased / decreased by 4
1 is input as the previous upper bit signal. The carry signal (carry signal) obtained from the adder 31 includes a carry signal (borrow signal) for convenience.

In FIG. 1, ADRS supplied to the terminal 26 is an address signal for the RAMs 32 and 42. In addition, in the increase / decrease circuit 41, “INI” is a terminal used for initialization, and is supplied with a clear signal. The process in this initialization is a bit extension process, and when the MSB is “0” as shown in FIG.
When it is “1”, it is bit-extended to “11”, and each value is RA as an upper bit signal.
M42 is written.

The adding operation of FIG. 1 is as arranged in FIG. 2, and the input signal is positive (its MSB is "0").
In the case of, the increase / decrease circuit 41 performs a process of "+1". When the carry signal is "0", writing to the RAM 42 is prohibited, so that the present upper bit signal is the same as the previous upper bit signal.
However, when the carry signal is "1", that is, when it is a carry, writing to the RAM 42 is permitted, the upper bit signal is written, and the new upper bit signal is used as the current upper bit signal. Is done.

On the other hand, when the input signal is negative (that is, its MSB is "1"), the increase / decrease circuit 41 performs a process of "-1" to the previous upper bit signal.
When the carry signal is "0" and therefore borrowed, the upper bit signal which has been "-1" is stored in the RAM4.
2 and the new upper bit signal is used as the current upper bit signal. However, when the carry signal is “1”, the exclusive-OR output becomes “0”, so that the write processing to the RAM 42 is not performed. Therefore, at this time, the previous upper bit signal is used as it is as the current upper bit signal.

FIG. 3 shows an example of a more specific addition processing operation. FIG. 3 shows a case of a 4-bit input (16 signals including positive and negative from -8 to +7). An example of the addition process of F (=-1) + 3 + 7 = 9 is shown. In the case where four channels (addresses P, Q, R, and S) are prepared as addresses in the RAM 32, the address P is used in the figure. In the initial stage of the addition operation, a bit expansion process is performed in the increase / decrease circuit 41, and the value is stored in the RAM. In the next cycle, "3" is input, and the MS at that time is input.
Since B is “0”, the increase / decrease circuit performs processing of “+1”, and the addition result becomes a borrow. Therefore, the upper bit signal “00” output from the increase / decrease circuit 41 is stored in the RAM 42.
Is written to. In the next cycle, “7” is input this time. Since the addition result at this time is neither a carry nor a borrow, the output of the increase / decrease circuit 41 is not written to the RAM 42. Therefore, the high-order bit signal remains at the high-order bit signal “00” of the previous cycle, and “9” is obtained as the final accumulated result (addition output).

FIG. 4 shows another example of the present invention. The figure shows R
In this case, registers 35 and 45 are used in place of the AMs 32 and 42. A predetermined clock CK is supplied to a terminal 26 instead of an address signal, and an OR circuit 44 supplies a clock enable terminal CK.E of the register 45. The output enable signal is supplied as a clock control signal. Only when this clock control signal is obtained, the register 45 is rewritten, so that the operation is the same as that of FIG.

FIG. 5 shows still another embodiment of the present invention. This embodiment is a modification of FIG. 4, in which the upper bit decision circuit 20B is replaced by one counter 46. The MSB of the input signal is supplied to the initial value set terminal of the counter 20B and also to the up / down control terminal,
The output of the exclusive OR circuit 43 is supplied to the count enable terminal CE. Also, a clear signal is supplied to the load terminal LOAD and a predetermined clock CK
Are supplied to the clock input terminal CK.

When the MSB is "0", there is a high possibility that the addition result is a carry.
Control is performed by a count-up process to perform the “1” process. When the MSB is “1”, there is a high possibility that the addition result will be a borrow, and in this case, control is performed so as to count down. When the exclusive OR output is "1", the count operation is controlled so that the count operation is always performed, and the count itself is used as the upper bit signal of this time. Others are the same as those described above, and the description thereof is omitted.

In the above-mentioned embodiment, when a RAM is used, and further speed-up is required due to the access time of the RAM, etc., a high-speed operation is performed in the input portion, the output portion or the RAM itself of the RAM. May be placed.

[0030]

As described above, in the accumulator circuit according to the present invention, the carry operation and the carry operation are performed separately from the lower bit addition processing operation, and finally, the lower bit addition processing output and the carry operation are carried out. In this case, the output associated with the carry is used as the final addition output.

In the case where the processing is performed separately as described above,
Since there is no increase in delay time due to carry processing of the adder or increase in addition processing time due to an increase in the word length to be handled, the processing time can be reduced without using a high-speed adder as an adder. Can be achieved.

Since an adder or the like for high-speed processing is not used, the circuit size is reduced and the cost can be reduced accordingly. Therefore, the present invention is extremely suitable for application to the above-described motion vector compensating circuit or the like which requires a long-time accumulation process.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of an accumulator circuit according to the present invention.

FIG. 2 is an explanatory diagram of a processing mode for explaining the operation.

FIG. 3 is a timing chart showing an example of the addition processing operation.

FIG. 4 is a system diagram showing another example of the present invention.

FIG. 5 is a system diagram showing another example of the present invention.

FIG. 6 is a system diagram illustrating an example of a frame difference detection circuit.

FIG. 7 is a system diagram showing an example of a conventional accumulator circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Frame difference detection circuit 20 Accumulator circuit 20A Lower accumulator 20B Upper bit determination circuit 31 Adder 32,42 RAM 41 Increase / decrease circuit

Claims (1)

(57) [Claims] 1. An n-bit lower accumulator having an n-bit two-input adder and a memory for storing an added output thereof, and a higher-order bit decision circuit, wherein a digital input signal composed of n bits is provided. It is supplied to the lower accumulator, added to the previous accumulated output, and output as an n-bit signal. The MSB of the input signal and the carry signal obtained from the adder are used as the upper bit decision circuit. Supplied to
An accumulator circuit wherein the upper bit k (k is an integer of 1 or more) at that time is determined based on both signals, and (n + k) bits are output from the accumulator circuit.